284 lines
10 KiB
C
284 lines
10 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _MT6769_VPU_HW_H_
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#define _MT6769_VPU_HW_H_
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#include "vpu_reg.h"
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#include "vpu_drv.h"
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#define VPU_MAX_NUM_CODE_SEGMENTS (50)
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#define VPU_MAX_NUM_ALGOS (50)
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#define VPU_MAX_NUM_STEPS (8)
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#define VPU_MAX_NUM_OPPS (8)
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/* MVA */
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#define VPU_MVA_RESET_VECTOR (0x7DA00000)
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#define VPU2_MVA_RESET_VECTOR (0x7E300000)
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#define VPU3_MVA_RESET_VECTOR (0x7EC00000)
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#define VPU_MVA_MAIN_PROGRAM (0x7DB00000)
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#define VPU2_MVA_MAIN_PROGRAM (0x7E400000)
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#define VPU3_MVA_MAIN_PROGRAM (0x7ED00000)
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#define VPU_MVA_KERNEL_LIB (0x7DE00000)
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#define VPU2_MVA_KERNEL_LIB (0x7E700000)
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#define VPU3_MVA_KERNEL_LIB (0x7F000000)
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#define VPU_MVA_SHARED_DATA (0x7F500000)
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#define VPU_MVA_RESERVED_END (0x82600000)
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/* Sum of all parts */
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#define VPU_SIZE_BINARY_CODE (0x02A10000)
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/* Size */
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#define VPU_SIZE_RESET_VECTOR (0x00100000)
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#define VPU_SIZE_MAIN_PROGRAM (0x00300000)
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#define VPU_SIZE_ALGO_KERNEL_LIB (0x00500000)
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#define VPU_SIZE_ALGO_AREA (0x00500000)
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#define VPU_SIZE_MAIN_PROGRAM_IMEM (0x00030000)
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#define VPU_SIZE_SHARED_DATA (0x00600000)
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#define VPU_NUMS_IMAGE_HEADER (3)
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/* Offset */
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#define VPU_OFFSET_RESET_VECTOR (0x00000000)
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#define VPU_OFFSET_MAIN_PROGRAM (0x00100000)
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#define VPU_OFFSET_ALGO_AREA (0x00C00000)
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#define VPU_OFFSET_MAIN_PROGRAM_IMEM (VPU_SIZE_BINARY_CODE - 0xC0000)
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#define VPU_OFFSET_IMAGE_HEADERS (VPU_SIZE_BINARY_CODE - 0x30000)
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#define VPU_DDR_SHIFT_RESET_VECTOR (0x00400000)
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#define VPU_DDR_SHIFT_IRAM_DATA (0x00030000)
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struct vpu_code_segment {
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uint32_t vpu_core; /* core index*/
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uint32_t offset; /* offset from this partition */
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uint32_t dst_addr; /* the DDR position is IPU can realize. */
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uint32_t length; /* total size for this segment */
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uint32_t file_size; /* file size to copy */
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};
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struct vpu_algo_info {
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uint32_t vpu_core; /* core index*/
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uint32_t offset;
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uint32_t length;
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char name[32];
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};
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struct vpu_dvfs_steps {
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uint32_t values[VPU_MAX_NUM_STEPS];
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uint8_t count;
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uint8_t index;
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uint8_t opp_map[VPU_MAX_NUM_OPPS];
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};
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struct vpu_dvfs_opps {
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struct vpu_dvfs_steps vcore;
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struct vpu_dvfs_steps dsp; /* ipu_conn */
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struct vpu_dvfs_steps dspcore[MTK_VPU_CORE]; /* ipu_core# */
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struct vpu_dvfs_steps ipu_if; /* ipusys_vcore, interface */
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uint8_t index;
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uint8_t count;
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};
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/*
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* The VPU program is stored in EMMC Partitions, and the little kernel will
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* load it to DDR. There are three partitions for different purpose, and little
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* kernel will merge them to contiguous physical memory. The buffer layout in
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* DDR is as follows:
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*
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* Using the layout, VPU driver could map these binary data
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* to the specific mva for VPU booting.
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*
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* [offset] [mapping mva]
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* 0x00000000 +-----------------------+ 0x50000000
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* | Reset vector of VPU |
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* | code [512KB] |
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* 0x00080000 +-----------------------+ 0x60000000
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* | Main Program |
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* | [1.5MB] |
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* 0x00200000 +-----------------------+ 0x60180000
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* | Reserved for algo |
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* | instruction [12.5MB] |
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* 0x00E80000 +-----------------------+ 0x6E000000
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* | Main Program IMEM |
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* | [256KM] |
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* 0x00EC0000 +-----------------------+ no mva
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* | Merged image header |
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* | [256KB] |
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* +-----------------------+
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*
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* The last part of buffer, named "merged image header", will put a array of
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* struct vpu_image_header, whose size is 3. All VPU driver needs to know is
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* algo's offset for algo loading.
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*
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*/
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struct vpu_image_header {
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uint32_t version;
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uint32_t build_date;
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uint32_t header_desc[8];
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uint32_t header_size;
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uint32_t image_size;
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uint32_t code_segment_count;
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struct vpu_code_segment code_segments[VPU_MAX_NUM_CODE_SEGMENTS];
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uint32_t algo_info_count;
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struct vpu_algo_info algo_infos[VPU_MAX_NUM_ALGOS];
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uint32_t reserved[32];
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};
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/*
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* VPU driver uses the spare register to exchange data with VPU program
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* (VPU code)
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* The below tables show the usage of spare register:
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*
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* Command: GET_ALGO_INFO
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* +-----------------+--------------------------------------------+-----------+
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* | Field | Description | Filled By |
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* +-----------------+--------------------------------------------+-----------+
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* |FLD_XTENSA_INFO1 | 0x82(GET_ALGO_INFO) | Driver |
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* |FLD_XTENSA_INFO5 | num of ports | VPU Code |
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* |FLD_XTENSA_INFO6 | pointer to the array of struct port | Driver |
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* |FLD_XTENSA_INFO7 | [info] pointer to property buffer | Driver |
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* |FLD_XTENSA_INFO8 | [info] size of property buffer(1024) | Driver |
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* |FLD_XTENSA_INFO9 | [info] num of property description | VPU Code |
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* |FLD_XTENSA_INFO10| [info] pointer to the array of struct desc | Driver |
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* |FLD_XTENSA_INFO11| [sett] num of property description | VPU Code |
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* |FLD_XTENSA_INFO12| [sett] pointer to the array of struct desc | Driver |
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* +-----------------+--------------------------------------------+-----------+
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*
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* Command: DO_LOADER
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* +-----------------+---------------------------------------+-----------+
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* | Field | Description | Filled By |
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* +-----------------+---------------------------------------+-----------+
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* |FLD_XTENSA_INFO1 | 0x01(DO_LOADER) | Driver |
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* |FLD_XTENSA_INFO12| pointer to the algo's start-address | Driver |
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* |FLD_XTENSA_INFO13| size of the algo | Driver |
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* |FLD_XTENSA_INFO14| function entry point (optional) | Driver |
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* |FLD_XTENSA_INFO15| VPU frequency (KHz) | Driver |
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* |FLD_XTENSA_INFO16| VPU IF frequency (KHz) | Driver |
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* +-----------------+---------------------------------------+-----------+
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*
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* Command: DO_D2D
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* +-----------------+---------------------------------------+-----------+
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* | Field | Description | Filled By |
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* +-----------------+---------------------------------------+-----------+
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* |FLD_XTENSA_INFO1 | 0x22(DO_D2D) | Driver |
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* |FLD_XTENSA_INFO12| num of buffers | Driver |
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* |FLD_XTENSA_INFO13| pointer to the array of struct buffer | Driver |
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* |FLD_XTENSA_INFO14| pointer to setting buffer | Driver |
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* |FLD_XTENSA_INFO15| size of setting buffer | Driver |
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* +-----------------+---------------------------------------+-----------+
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*
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* Command: GET_SWVER
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* +-----------------+---------------------------------------+-----------+
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* | Field | Description | Filled By |
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* +-----------------+---------------------------------------+-----------+
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* |FLD_XTENSA_INFO1 | 0x40(GET_SWVER) | Driver |
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* |FLD_XTENSA_INFO20| Software version | VPU Code |
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* +-----------------+---------------------------------------+-----------+
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*
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* Command: SET_DEBUG
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* +-----------------+---------------------------------------+-----------+
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* | Field | Description | Filled By |
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* +-----------------+---------------------------------------+-----------+
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* |FLD_XTENSA_INFO1 | 0x40(SET_DEG) | Driver |
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* |FLD_XTENSA_INFO21| mva of log buffer | Driver |
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* |FLD_XTENSA_INFO22| length of log buffer | Driver |
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* |FLD_XTENSA_INFO23| system time in us | Driver |
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* +-----------------+---------------------------------------+-----------+
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*/
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/**
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* vpu_hw_boot_sequence - do booting sequence
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* @core: core index of device
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*/
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int vpu_hw_boot_sequence(int core);
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/**
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* vpu_set_debug - set log buffer and size to VPU
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*/
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int vpu_hw_set_debug(int core);
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/**
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* vpu_hw_enable_jtag - start dsp debug via jtag
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*/
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int vpu_hw_enable_jtag(bool enabled);
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/**
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* vpu_hw_enque_request - do DRAM-to-DRAM processing,
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* and it will block until done.
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* @core: core index of device
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* @req: the pointer to request
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*/
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int vpu_hw_enque_request(int core, struct vpu_request *req);
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/**
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* vpu_hw_processing_request - do whole processing for enque request,
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* including check algo, load algo, run d2d.
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* @core: core index of device
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* @req: the pointer to request
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*/
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int vpu_hw_processing_request(int core, struct vpu_request *req);
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/**
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* vpu_thermal_en_throttle_cb - for thermal callback, do vcore or freq control.
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* @vcore_opp: upper bound for vcore opp
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* @vpu_opp: upper bound for dsp freq
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*/
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int32_t vpu_thermal_en_throttle_cb(uint8_t vcore_opp, uint8_t vpu_opp);
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/**
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* vpu_thermal_dis_throttle_cb - for thermal callback, disable throttle.
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*/
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int32_t vpu_thermal_dis_throttle_cb(void);
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/**
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* vpu_dump_debug_stack - for vpu timeout debug.
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*/
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void vpu_dump_debug_stack(int core, int size);
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/**
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* vpu_dump_code_segment - for vpu timeout debug,
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* dump code segment in algo execution area.
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*/
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void vpu_dump_code_segment(int core);
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/**
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* vpu_dump_algo_segment - for vpu timeout debug,
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* dump source algo segment from bin file.
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*/
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void vpu_dump_algo_segment(int core, int algo_id, int size);
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/**
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* Working buffer's offset
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*
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* [offset]
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* 0x00000000 +-----------------------+
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* | Command Buffer |
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* | [8KB] |
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* 0x00002000 +-----------------------+
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* | Log Buffer |
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* | [8KB] |
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* +-----------------------+
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*
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* the first 16 bytes of log buffer:
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* @tail_addr: the mva of log end, which always points to '\0'
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*
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* +-----------+----------------------+
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* | 0 ~ 3 | 4 ~ 15 |
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* +-----------+----------------------+
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* |{tail_addr}| {reserved} |
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* +-----------+----------------------+
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*/
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#define VPU_OFFSET_COMMAND (0x00000000)
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#define VPU_OFFSET_LOG (0x00002000)
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#define VPU_SIZE_LOG_BUF (0x00010000)
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#define VPU_SIZE_LOG_SHIFT (0x00000300)
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#define VPU_SIZE_LOG_HEADER (0x00000010)
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#define VPU_SIZE_WORK_BUF (0x00012000)
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#endif
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