263 lines
6.6 KiB
C
263 lines
6.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __MT_MSDC_H__
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#define __MT_MSDC_H__
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#include <mt-plat/sync_write.h>
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#if defined(CONFIG_MACH_MT6768) && defined(CONFIG_MTK_PMQOS)
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#include <linux/soc/mediatek/mtk-pm-qos.h>
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#endif
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#define HOST_MAX_NUM (2)
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#define TUNE_NONE (0) /* No need tune */
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#define TUNE_CMD_CRC (0x1 << 0) /* transfer cmd crc */
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#define TUNE_DATA_WRITE (0x1 << 1) /* transfer data crc */
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#define TUNE_DATA_READ (0x1 << 2) /* transfer data crc */
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#define TUNE_CMD_TMO (0x1 << 3) /* transfer cmd tmo */
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#define TUNE_AUTOK_PASS (0x1 << 4) /* autok pass flag */
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enum {
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MODE_PIO = 0,
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MODE_DMA = 1,
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MODE_SIZE_DEP = 2,
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MODE_NONE = 3,
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};
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static inline unsigned int uffs(unsigned int x)
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{
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unsigned int r = 1;
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if (!x)
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return 0;
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if (!(x & 0xffff)) {
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x >>= 16;
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r += 16;
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}
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if (!(x & 0xff)) {
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x >>= 8;
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r += 8;
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}
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if (!(x & 0xf)) {
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x >>= 4;
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r += 4;
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}
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if (!(x & 3)) {
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x >>= 2;
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r += 2;
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}
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if (!(x & 1)) {
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x >>= 1;
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r += 1;
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}
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return r;
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}
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#define MSDC_READ8(reg) __raw_readb(reg)
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#define MSDC_READ16(reg) __raw_readw(reg)
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#define MSDC_READ32(reg) __raw_readl(reg)
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#define MSDC_WRITE8(reg, val) mt_reg_sync_writeb(val, reg)
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#define MSDC_WRITE16(reg, val) mt_reg_sync_writew(val, reg)
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#define MSDC_WRITE32(reg, val) mt_reg_sync_writel(val, reg)
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#define UNSTUFF_BITS(resp, start, size) \
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({ \
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const int __size = size; \
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const u32 __mask = (__size < 32 ? 1 << __size : 0) - 1; \
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const int __off = 3 - ((start) / 32); \
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const int __shft = (start) & 31; \
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u32 __res; \
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__res = resp[__off] >> __shft; \
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if (__size + __shft > 32) \
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__res |= resp[__off-1] << ((32 - __shft) % 32); \
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__res & __mask; \
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})
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#define MSDC_SET_BIT32(reg, bs) \
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do { \
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unsigned int tv = MSDC_READ32(reg);\
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tv |= (u32)(bs); \
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MSDC_WRITE32(reg, tv); \
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} while (0)
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#define MSDC_CLR_BIT32(reg, bs) \
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do { \
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unsigned int tv = MSDC_READ32(reg);\
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tv &= ~((u32)(bs)); \
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MSDC_WRITE32(reg, tv); \
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} while (0)
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#define MSDC_SET_FIELD(reg, field, val) \
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do { \
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unsigned int tv = MSDC_READ32(reg); \
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tv &= ~(field); \
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tv |= ((val) << (uffs((unsigned int)field) - 1)); \
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MSDC_WRITE32(reg, tv); \
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} while (0)
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#define MSDC_GET_FIELD(reg, field, val) \
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do { \
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unsigned int tv = MSDC_READ32(reg); \
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val = ((tv & (field)) >> (uffs((unsigned int)field) - 1)); \
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} while (0)
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#define GET_FIELD(reg, field_shift, field_mask, val) \
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(val = (reg >> field_shift) & field_mask)
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struct mt_gpdma_desc {
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u32 gpd_info;
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#define GPDMA_DESC_HWO (0x1 << 0)
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#define GPDMA_DESC_BDP (0x1 << 1)
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#define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
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#define GPDMA_DESC_INT (0x1 << 16)
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#define GPDMA_DESC_NEXT_H4 (0xf << 24)
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#define GPDMA_DESC_PTR_H4 (0xf << 28)
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u32 next;
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u32 ptr;
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u32 gpd_data_len;
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#define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
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#define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */
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u32 arg;
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u32 blknum;
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u32 cmd;
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};
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struct mt_bdma_desc {
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u32 bd_info;
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#define BDMA_DESC_EOL (0x1 << 0)
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#define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */
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#define BDMA_DESC_BLKPAD (0x1 << 17)
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#define BDMA_DESC_DWPAD (0x1 << 18)
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#define BDMA_DESC_NEXT_H4 (0xf << 24)
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#define BDMA_DESC_PTR_H4 (0xf << 28)
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u32 next;
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u32 ptr;
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u32 bd_data_len;
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#define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */
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#define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */
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};
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struct msdc_dma {
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struct scatterlist *sg; /* I/O scatter list */
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struct mt_gpdma_desc *gpd; /* pointer to gpd array */
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struct mt_bdma_desc *bd; /* pointer to bd array */
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dma_addr_t gpd_addr; /* the physical address of gpd array */
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dma_addr_t bd_addr; /* the physical address of bd array */
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};
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struct msdc_save_para {
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u32 msdc_cfg;
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u32 iocon;
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u32 sdc_cfg;
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u32 pad_tune;
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u32 patch_bit0;
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u32 patch_bit1;
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u32 patch_bit2;
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u32 pad_ds_tune;
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u32 pad_cmd_tune;
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u32 emmc50_cfg0;
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u32 emmc50_cfg3;
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u32 sdc_fifo_cfg;
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u32 emmc_top_control;
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u32 emmc_top_cmd;
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u32 emmc50_pad_ds_tune;
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};
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struct msdc_tune_para {
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u32 iocon;
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u32 pad_tune;
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u32 pad_cmd_tune;
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u32 emmc_top_control;
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u32 emmc_top_cmd;
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};
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struct msdc_host {
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struct device *dev;
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const struct mtk_mmc_compatible *dev_comp;
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struct mmc_host *mmc; /* mmc structure */
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int cmd_rsp;
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spinlock_t lock;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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int error;
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void __iomem *base; /* host base address */
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void __iomem *top_base; /* host top register base address */
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struct msdc_dma dma; /* dma channel */
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u64 dma_mask;
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u32 timeout_ns; /* data timeout ns */
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u32 timeout_clks; /* data timeout clks */
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_default;
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struct pinctrl_state *pins_uhs;
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struct pinctrl_state *pins_pull_down;
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struct delayed_work req_timeout;
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int irq; /* host interrupt */
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struct clk *src_clk; /* msdc source clock */
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struct clk *h_clk; /* msdc h_clk */
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struct clk *bus_clk; /* bus clock which used to access register */
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struct clk *src_clk_cg; /* msdc source clock control gate */
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struct clk *crypto_clk; /* msdc crypto clock */
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void __iomem *crypto_clk_base; /*dbg use: for dump aes clk cg*/
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u32 mclk; /* mmc subsystem clock frequency */
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u32 src_clk_freq; /* source clock frequency */
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#ifdef CONFIG_MACH_MT8173
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u32 sclk; /* SD/MS bus clock frequency */
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#endif
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unsigned char timing;
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bool vqmmc_enabled;
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#ifdef CONFIG_MACH_MT8173
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u32 host_id;
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#endif
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u32 latch_ck;
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u32 hs400_ds_delay;
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u32 hs400_ds_dly3;
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u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
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u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
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#ifdef CONFIG_MACH_MT8173
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u32 hs200_cmd_resp_sel; /* cmd response sample selection */
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/* valid after tune response && final delay != 0xffffffff */
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bool tune_response_valid;
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u8 tune_response_delay; /* saved tune response value */
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#endif
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bool hs400_cmd_resp_sel_rising;
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/* cmd response sample selection for HS400 */
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bool hs400_mode; /* current eMMC will run at hs400 mode */
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bool hs400_tuning; /* hs400 mode online tuning */
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bool cqhci; /* support eMMC hw cmdq */
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bool is_autok_done;
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bool internal_cd; /* Use internal card-detect logic */
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bool block_bad_card;
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u8 card_inserted; /* the status of card inserted */
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int retune_times;
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u32 need_tune;
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int power_cycle_cnt;
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u32 data_timeout_cont; /* data continuous timeout */
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struct msdc_save_para save_para; /* used when gate HCLK */
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struct msdc_tune_para def_tune_para; /* default tune setting */
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struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
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struct cqhci_host *cq_host;
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#if defined(CONFIG_MACH_MT6768) && defined(CONFIG_MTK_PMQOS)
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struct mtk_pm_qos_request pm_qos;
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#endif
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};
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#endif
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