232 lines
7.6 KiB
C
232 lines
7.6 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _DT_BINDINGS_GCE_MT6768_H
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#define _DT_BINDINGS_GCE_MT6768_H
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#include "mt6382-gce.h"
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/* assign timeout 0 also means default */
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#define CMDQ_NO_TIMEOUT 0xffffffff
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#define CMDQ_TIMEOUT_DEFAULT 1000
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/* GCE thread priority */
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#define CMDQ_THR_PRIO_LOWEST 0
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#define CMDQ_THR_PRIO_1 1
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#define CMDQ_THR_PRIO_2 2
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#define CMDQ_THR_PRIO_3 3
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#define CMDQ_THR_PRIO_4 4
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#define CMDQ_THR_PRIO_5 5
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#define CMDQ_THR_PRIO_6 6
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#define CMDQ_THR_PRIO_HIGHEST 7
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/* CPR count in 32bit register */
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#define GCE_CPR_COUNT 128
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/* GCE subsys table */
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#define SUBSYS_1300XXXX 0
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#define SUBSYS_1400XXXX 1
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#define SUBSYS_1401XXXX 2
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#define SUBSYS_1402XXXX 3
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#define SUBSYS_1502XXXX 4
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#define SUBSYS_1880XXXX 5
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#define SUBSYS_1881XXXX 6
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#define SUBSYS_1882XXXX 7
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#define SUBSYS_1883XXXX 8
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#define SUBSYS_1884XXXX 9
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#define SUBSYS_1000XXXX 10
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#define SUBSYS_1001XXXX 11
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#define SUBSYS_1002XXXX 12
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#define SUBSYS_1003XXXX 13
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#define SUBSYS_1004XXXX 14
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#define SUBSYS_1005XXXX 15
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#define SUBSYS_1020XXXX 16
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#define SUBSYS_1028XXXX 17
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#define SUBSYS_1700XXXX 18
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#define SUBSYS_1701XXXX 19
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#define SUBSYS_1702XXXX 20
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#define SUBSYS_1703XXXX 21
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#define SUBSYS_1800XXXX 22
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#define SUBSYS_1801XXXX 23
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#define SUBSYS_1802XXXX 24
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#define SUBSYS_1804XXXX 25
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#define SUBSYS_1805XXXX 26
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#define SUBSYS_1808XXXX 27
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#define SUBSYS_180aXXXX 28
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#define SUBSYS_180bXXXX 29
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/* GCE hardware events */
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#define CMDQ_EVENT_MDP_RDMA0_SOF 0
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#define CMDQ_EVENT_MDP_CCORR0_SOF 1
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#define CMDQ_EVENT_MDP_RSZ0_SOF 2
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#define CMDQ_EVENT_MDP_RSZ1_SOF 3
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#define CMDQ_EVENT_MDP_WDMA_SOF 4
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#define CMDQ_EVENT_MDP_WROT0_SOF 5
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#define CMDQ_EVENT_MDP_TDSHP0_SOF 6
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#define CMDQ_EVENT_DISP_OVL0_SOF 7
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#define CMDQ_EVENT_DISP_2L_OVL0_SOF 8
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#define CMDQ_EVENT_DISP_RDMA0_SOF 9
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#define CMDQ_EVENT_DISP_WDMA0_SOF 10
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#define CMDQ_EVENT_DISP_COLOR0_SOF 11
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#define CMDQ_EVENT_DISP_CCORR0_SOF 12
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#define CMDQ_EVENT_DISP_AAL0_SOF 13
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#define CMDQ_EVENT_DISP_GAMMA0_SOF 14
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#define CMDQ_EVENT_DISP_DITHER0_SOF 15
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#define CMDQ_EVENT_DISP_DSI0_SOF 16
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#define CMDQ_EVENT_DISP_RSZ0_SOF 17
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#define CMDQ_EVENT_IMG_DL_RELAY_SOF 18
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#define CMDQ_EVENT_DISP_PWM0_SOF 19
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#define CMDQ_EVENT_MDP_RDMA0_EOF 20
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#define CMDQ_EVENT_MDP_CCORR0_FRAME_DONE 21
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#define CMDQ_EVENT_MDP_RSZ0_EOF 22
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#define CMDQ_EVENT_MDP_RSZ1_EOF 23
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#define CMDQ_EVENT_MDP_WROT0_W_EOF 24
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#define CMDQ_EVENT_MDP_WDMA_EOF 25
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#define CMDQ_EVENT_MDP_TDSHP0_EOF 26
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#define CMDQ_EVENT_DISP_OVL0_EOF 27
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#define CMDQ_EVENT_DISP_2L_OVL0_EOF 28
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#define CMDQ_EVENT_DISP_RSZ0_EOF 29
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#define CMDQ_EVENT_DISP_RDMA0_EOF 30
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#define CMDQ_EVENT_DISP_WDMA0_EOF 31
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#define CMDQ_EVENT_DISP_COLOR0_EOF 32
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#define CMDQ_EVENT_DISP_CCORR0_EOF 33
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#define CMDQ_EVENT_DISP_AAL0_EOF 34
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#define CMDQ_EVENT_DISP_GAMMA0_EOF 35
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#define CMDQ_EVENT_DISP_DITHER0_EOF 36
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#define CMDQ_EVENT_DISP_DSI0_EOF 37
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#define CMDQ_EVENT_MUTEX0_STREAM_EOF 130
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#define CMDQ_EVENT_MUTEX1_STREAM_EOF 131
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#define CMDQ_EVENT_MUTEX2_STREAM_EOF 132
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#define CMDQ_EVENT_MUTEX3_STREAM_EOF 133
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#define CMDQ_EVENT_MUTEX4_STREAM_EOF 134
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#define CMDQ_EVENT_MUTEX5_STREAM_EOF 135
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#define CMDQ_EVENT_MUTEX6_STREAM_EOF 136
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#define CMDQ_EVENT_MUTEX7_STREAM_EOF 137
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#define CMDQ_EVENT_MUTEX8_STREAM_EOF 138
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#define CMDQ_EVENT_MUTEX9_STREAM_EOF 139
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#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 140
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#define CMDQ_EVENT_DSI0_TE 141
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#define CMDQ_EVENT_DSI0_IRQ_EVENT 142
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#define CMDQ_EVENT_DSI0_DONE_EVENT 143
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#define CMDQ_EVENT_DISP_WDMA0_RST_DONE 147
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#define CMDQ_EVENT_MDP_WDMA_RST_DONE 148
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#define CMDQ_EVENT_MDP_WROT0_RST_DONE 149
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#define CMDQ_EVENT_MDP_RDMA0_RST_DONE 151
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#define CMDQ_EVENT_DISP_OVL0_RST_DONE 152
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#define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 257
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#define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 258
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#define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 259
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#define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 260
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#define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 261
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#define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 262
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#define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 263
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#define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 264
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#define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 265
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#define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 266
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#define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 267
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#define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 268
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#define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 269
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#define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 270
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#define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 271
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#define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 272
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#define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 273
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#define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 274
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#define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 275
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#define CMDQ_EVENT_DVE_EOF 276
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#define CMDQ_EVENT_WMF_EOF 277
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#define CMDQ_EVENT_RSC_EOF 278
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#define CMDQ_EVENT_VENC_FRAME_DONE 289
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#define CMDQ_EVENT_VENC_PAUSE_DONE 290
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#define CMDQ_EVENT_JPEG_ENC_EOF 291
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#define CMDQ_EVENT_VENC_MB_DONE 292
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#define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 293
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#define CMDQ_EVENT_ISP_FRAME_DONE_B 322
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#define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 323
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#define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 324
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#define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 325
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#define CMDQ_EVENT_ISP_TSF_DONE 326
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#define CMDQ_EVENT_SENINF_0_FIFO_FULL 327
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#define CMDQ_EVENT_SENINF_1_FIFO_FULL 328
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#define CMDQ_EVENT_SENINF_2_FIFO_FULL 329
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#define CMDQ_EVENT_SENINF_3_FIFO_FULL 330
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#define CMDQ_EVENT_SENINF_4_FIFO_FULL 331
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#define CMDQ_EVENT_SENINF_5_FIFO_FULL 332
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#define CMDQ_EVENT_SENINF_6_FIFO_FULL 333
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#define CMDQ_EVENT_SENINF_7_FIFO_FULL 334
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#define CMDQ_EVENT_DSI0_TE_INFRA 898
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/* CMDQ sw tokens
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* Following definitions are gce sw token which may use by clients
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* event operation API.
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* Note that token 512 to 639 may set secure
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*/
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/* end of hw event and begin of sw token */
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#define CMDQ_MAX_HW_EVENT 512
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/* Config thread notify trigger thread */
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#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640
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/* Trigger thread notify config thread */
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#define CMDQ_SYNC_TOKEN_STREAM_EOF 641
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/* Block Trigger thread until the ESD check finishes. */
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#define CMDQ_SYNC_TOKEN_ESD_EOF 642
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#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643
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/* check CABC setup finish */
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#define CMDQ_SYNC_TOKEN_CABC_EOF 644
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/* Notify normal CMDQ there are some secure task done
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* MUST NOT CHANGE, this token sync with secure world
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*/
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#define CMDQ_SYNC_SECURE_THR_EOF 647
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/* CMDQ use sw token */
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#define CMDQ_SYNC_TOKEN_USER_0 649
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#define CMDQ_SYNC_TOKEN_USER_1 650
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#define CMDQ_SYNC_TOKEN_POLL_MONITOR 651
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#define CMDQ_SYNC_TOKEN_TPR_LOCK 652
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/* ISP sw token */
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#define CMDQ_SYNC_TOKEN_MSS 665
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#define CMDQ_SYNC_TOKEN_MSF 666
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/* GPR access tokens (for HW register backup)
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* There are 15 32-bit GPR, 3 GPR form a set
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* (64-bit for address, 32-bit for value)
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* MUST NOT CHANGE, these tokens sync with MDP
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*/
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#define CMDQ_SYNC_TOKEN_GPR_SET_0 700
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#define CMDQ_SYNC_TOKEN_GPR_SET_1 701
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#define CMDQ_SYNC_TOKEN_GPR_SET_2 702
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#define CMDQ_SYNC_TOKEN_GPR_SET_3 703
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#define CMDQ_SYNC_TOKEN_GPR_SET_4 704
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/* Resource lock event to control resource in GCE thread */
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#define CMDQ_SYNC_RESOURCE_WROT0 710
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#define CMDQ_SYNC_RESOURCE_WROT1 711
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/* event for gpr timer, used in sleep and poll with timeout */
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#define CMDQ_TOKEN_GPR_TIMER_R0 994
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#define CMDQ_TOKEN_GPR_TIMER_R1 995
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#define CMDQ_TOKEN_GPR_TIMER_R2 996
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#define CMDQ_TOKEN_GPR_TIMER_R3 997
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#define CMDQ_TOKEN_GPR_TIMER_R4 998
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#define CMDQ_TOKEN_GPR_TIMER_R5 999
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#define CMDQ_TOKEN_GPR_TIMER_R6 1000
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#define CMDQ_TOKEN_GPR_TIMER_R7 1001
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#define CMDQ_TOKEN_GPR_TIMER_R8 1002
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#define CMDQ_TOKEN_GPR_TIMER_R9 1003
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#define CMDQ_TOKEN_GPR_TIMER_R10 1004
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#define CMDQ_TOKEN_GPR_TIMER_R11 1005
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#define CMDQ_TOKEN_GPR_TIMER_R12 1006
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#define CMDQ_TOKEN_GPR_TIMER_R13 1007
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#define CMDQ_TOKEN_GPR_TIMER_R14 1008
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#define CMDQ_TOKEN_GPR_TIMER_R15 1009
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#define CMDQ_EVENT_MAX 0x3FF
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/* CMDQ sw tokens END */
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#endif
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