91 lines
3.4 KiB
C
91 lines
3.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef _DTS_IOMMU_PORT_MT6768_H_
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#define _DTS_IOMMU_PORT_MT6768_H_
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#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
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/* Local arbiter ID */
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#define MTK_M4U_TO_LARB(id) (((id) >> 5) & 0xf)
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/* PortID within the local arbiter */
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#define MTK_M4U_TO_PORT(id) ((id) & 0x1f)
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#define MTK_IOMMU_LARB_NR (5)
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/* larb0 -- 8*/
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#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(0, 0)
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#define M4U_PORT_DISP_2L_OVL0_LARB0 MTK_M4U_ID(0, 1)
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#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(0, 2)
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#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(0, 3)
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#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(0, 4)
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#define M4U_PORT_MDP_WDMA0 MTK_M4U_ID(0, 5)
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#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(0, 6)
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#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(0, 7)
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/* larb1 -- 9*/
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#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(1, 0)
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#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(1, 1)
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#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(1, 2)
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#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(1, 3)
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#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(1, 4)
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#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(1, 5)
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#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(1, 6)
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#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(1, 7)
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#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(1, 8)
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/* larb2 -- 12*/
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#define M4U_PORT_CAM_IMGI MTK_M4U_ID(2, 0)
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#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(2, 1)
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#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(2, 2)
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#define M4U_PORT_CAM_VIPI MTK_M4U_ID(2, 3)
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#define M4U_PORT_CAM_LCEI MTK_M4U_ID(2, 4)
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#define M4U_PORT_CAM_FD_RP MTK_M4U_ID(2, 5)
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#define M4U_PORT_CAM_FD_WR MTK_M4U_ID(2, 6)
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#define M4U_PORT_CAM_FD_RB MTK_M4U_ID(2, 7)
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#define M4U_PORT_CAM_DPE_RDMA MTK_M4U_ID(2, 8)
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#define M4U_PORT_CAM_DPE_WDMA MTK_M4U_ID(2, 9)
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#define M4U_PORT_CAM_RSC_RDMA MTK_M4U_ID(2, 10)
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#define M4U_PORT_CAM_RSC_WDMA MTK_M4U_ID(2, 11)
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/*larb3 -- 21*/
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#define M4U_PORT_CAM_IMGO MTK_M4U_ID(3, 0)
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#define M4U_PORT_CAM_RRZO MTK_M4U_ID(3, 1)
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#define M4U_PORT_CAM_AAO MTK_M4U_ID(3, 2)
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#define M4U_PORT_CAM_AFO MTK_M4U_ID(3, 3)
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#define M4U_PORT_CAM_LSCI0 MTK_M4U_ID(3, 4)
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#define M4U_PORT_CAM_LSCI1 MTK_M4U_ID(3, 5)
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#define M4U_PORT_CAM_PDO MTK_M4U_ID(3, 6)
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#define M4U_PORT_CAM_BPCI MTK_M4U_ID(3, 7)
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#define M4U_PORT_CAM_LCSO MTK_M4U_ID(3, 8)
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#define M4U_PORT_CAM_RSSO_A MTK_M4U_ID(3, 9)
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#define M4U_PORT_CAM_RSSO_B MTK_M4U_ID(3, 10)
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#define M4U_PORT_CAM_UFEO MTK_M4U_ID(3, 11)
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#define M4U_PORT_CAM_SOC0 MTK_M4U_ID(3, 12)
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#define M4U_PORT_CAM_SOC1 MTK_M4U_ID(3, 13)
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#define M4U_PORT_CAM_SOC2 MTK_M4U_ID(3, 14)
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#define M4U_PORT_CAM_CCUI MTK_M4U_ID(3, 15)
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#define M4U_PORT_CAM_CCUO MTK_M4U_ID(3, 16)
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#define M4U_PORT_CAM_CACI MTK_M4U_ID(3, 17)
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#define M4U_PORT_CAM_RAWI_A MTK_M4U_ID(3, 18)
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#define M4U_PORT_CAM_RAWI_B MTK_M4U_ID(3, 19)
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#define M4U_PORT_CAM_CCUG MTK_M4U_ID(3, 20)
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/*larb4 -- 11*/
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#define M4U_PORT_VENC_RCPU MTK_M4U_ID(4, 0)
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#define M4U_PORT_VENC_REC MTK_M4U_ID(4, 1)
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#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(4, 2)
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#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(4, 3)
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#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(4, 4)
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#define M4U_PORT_JPGENC_RDMA MTK_M4U_ID(4, 5)
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#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(4, 6)
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#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(4, 7)
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#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(4, 8)
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#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(4, 9)
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#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(4, 10)
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#define M4U_PORT_UNKNOWN (M4U_PORT_VENC_REF_CHROMA + 1)
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#define M4U_PORT_NR (61)
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/* for pusedo ccu device */
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#define CCU_PSEUDO_LARBID (MTK_IOMMU_LARB_NR + 1)
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#define MISC_PSEUDO_LARBID (MTK_IOMMU_LARB_NR + 2)
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#endif
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