330 lines
9.6 KiB
C
330 lines
9.6 KiB
C
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/*
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* OMAP Smartreflex Defines and Routines
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*
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* Author: Thara Gopinath <thara@ti.com>
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*
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* Copyright (C) 2010 Texas Instruments, Inc.
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* Thara Gopinath <thara@ti.com>
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*
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* Copyright (C) 2008 Nokia Corporation
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* Kalle Jokiniemi
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Lesly A M <x0080970@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __POWER_SMARTREFLEX_H
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#define __POWER_SMARTREFLEX_H
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#include <linux/types.h>
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#include <linux/platform_device.h>
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#include <linux/delay.h>
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#include <linux/platform_data/voltage-omap.h>
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/*
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* Different Smartreflex IPs version. The v1 is the 65nm version used in
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* OMAP3430. The v2 is the update for the 45nm version of the IP
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* used in OMAP3630 and OMAP4430
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*/
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#define SR_TYPE_V1 1
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#define SR_TYPE_V2 2
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/* SMART REFLEX REG ADDRESS OFFSET */
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#define SRCONFIG 0x00
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#define SRSTATUS 0x04
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#define SENVAL 0x08
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#define SENMIN 0x0C
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#define SENMAX 0x10
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#define SENAVG 0x14
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#define AVGWEIGHT 0x18
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#define NVALUERECIPROCAL 0x1c
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#define SENERROR_V1 0x20
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#define ERRCONFIG_V1 0x24
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#define IRQ_EOI 0x20
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#define IRQSTATUS_RAW 0x24
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#define IRQSTATUS 0x28
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#define IRQENABLE_SET 0x2C
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#define IRQENABLE_CLR 0x30
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#define SENERROR_V2 0x34
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#define ERRCONFIG_V2 0x38
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/* Bit/Shift Positions */
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/* SRCONFIG */
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#define SRCONFIG_ACCUMDATA_SHIFT 22
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#define SRCONFIG_SRCLKLENGTH_SHIFT 12
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#define SRCONFIG_SENNENABLE_V1_SHIFT 5
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#define SRCONFIG_SENPENABLE_V1_SHIFT 3
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#define SRCONFIG_SENNENABLE_V2_SHIFT 1
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#define SRCONFIG_SENPENABLE_V2_SHIFT 0
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#define SRCONFIG_CLKCTRL_SHIFT 0
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#define SRCONFIG_ACCUMDATA_MASK (0x3ff << 22)
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#define SRCONFIG_SRENABLE BIT(11)
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#define SRCONFIG_SENENABLE BIT(10)
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#define SRCONFIG_ERRGEN_EN BIT(9)
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#define SRCONFIG_MINMAXAVG_EN BIT(8)
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#define SRCONFIG_DELAYCTRL BIT(2)
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/* AVGWEIGHT */
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#define AVGWEIGHT_SENPAVGWEIGHT_SHIFT 2
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#define AVGWEIGHT_SENNAVGWEIGHT_SHIFT 0
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/* NVALUERECIPROCAL */
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#define NVALUERECIPROCAL_SENPGAIN_SHIFT 20
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#define NVALUERECIPROCAL_SENNGAIN_SHIFT 16
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#define NVALUERECIPROCAL_RNSENP_SHIFT 8
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#define NVALUERECIPROCAL_RNSENN_SHIFT 0
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/* ERRCONFIG */
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#define ERRCONFIG_ERRWEIGHT_SHIFT 16
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#define ERRCONFIG_ERRMAXLIMIT_SHIFT 8
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#define ERRCONFIG_ERRMINLIMIT_SHIFT 0
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#define SR_ERRWEIGHT_MASK (0x07 << 16)
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#define SR_ERRMAXLIMIT_MASK (0xff << 8)
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#define SR_ERRMINLIMIT_MASK (0xff << 0)
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#define ERRCONFIG_VPBOUNDINTEN_V1 BIT(31)
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#define ERRCONFIG_VPBOUNDINTST_V1 BIT(30)
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#define ERRCONFIG_MCUACCUMINTEN BIT(29)
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#define ERRCONFIG_MCUACCUMINTST BIT(28)
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#define ERRCONFIG_MCUVALIDINTEN BIT(27)
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#define ERRCONFIG_MCUVALIDINTST BIT(26)
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#define ERRCONFIG_MCUBOUNDINTEN BIT(25)
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#define ERRCONFIG_MCUBOUNDINTST BIT(24)
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#define ERRCONFIG_MCUDISACKINTEN BIT(23)
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#define ERRCONFIG_VPBOUNDINTST_V2 BIT(23)
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#define ERRCONFIG_MCUDISACKINTST BIT(22)
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#define ERRCONFIG_VPBOUNDINTEN_V2 BIT(22)
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#define ERRCONFIG_STATUS_V1_MASK (ERRCONFIG_VPBOUNDINTST_V1 | \
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ERRCONFIG_MCUACCUMINTST | \
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ERRCONFIG_MCUVALIDINTST | \
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ERRCONFIG_MCUBOUNDINTST | \
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ERRCONFIG_MCUDISACKINTST)
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/* IRQSTATUS */
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#define IRQSTATUS_MCUACCUMINT BIT(3)
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#define IRQSTATUS_MCVALIDINT BIT(2)
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#define IRQSTATUS_MCBOUNDSINT BIT(1)
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#define IRQSTATUS_MCUDISABLEACKINT BIT(0)
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/* IRQENABLE_SET and IRQENABLE_CLEAR */
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#define IRQENABLE_MCUACCUMINT BIT(3)
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#define IRQENABLE_MCUVALIDINT BIT(2)
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#define IRQENABLE_MCUBOUNDSINT BIT(1)
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#define IRQENABLE_MCUDISABLEACKINT BIT(0)
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/* Common Bit values */
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#define SRCLKLENGTH_12MHZ_SYSCLK 0x3c
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#define SRCLKLENGTH_13MHZ_SYSCLK 0x41
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#define SRCLKLENGTH_19MHZ_SYSCLK 0x60
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#define SRCLKLENGTH_26MHZ_SYSCLK 0x82
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#define SRCLKLENGTH_38MHZ_SYSCLK 0xC0
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/*
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* 3430 specific values. Maybe these should be passed from board file or
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* pmic structures.
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*/
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#define OMAP3430_SR_ACCUMDATA 0x1f4
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#define OMAP3430_SR1_SENPAVGWEIGHT 0x03
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#define OMAP3430_SR1_SENNAVGWEIGHT 0x03
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#define OMAP3430_SR2_SENPAVGWEIGHT 0x01
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#define OMAP3430_SR2_SENNAVGWEIGHT 0x01
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#define OMAP3430_SR_ERRWEIGHT 0x04
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#define OMAP3430_SR_ERRMAXLIMIT 0x02
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enum sr_instance {
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OMAP_SR_MPU, /* shared with iva on omap3 */
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OMAP_SR_CORE,
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OMAP_SR_IVA,
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OMAP_SR_NR,
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};
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struct omap_sr {
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char *name;
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struct list_head node;
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struct platform_device *pdev;
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struct omap_sr_nvalue_table *nvalue_table;
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struct voltagedomain *voltdm;
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struct dentry *dbg_dir;
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unsigned int irq;
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int srid;
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int ip_type;
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int nvalue_count;
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bool autocomp_active;
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u32 clk_length;
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u32 err_weight;
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u32 err_minlimit;
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u32 err_maxlimit;
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u32 accum_data;
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u32 senn_avgweight;
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u32 senp_avgweight;
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u32 senp_mod;
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u32 senn_mod;
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void __iomem *base;
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};
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/**
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* test_cond_timeout - busy-loop, testing a condition
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* @cond: condition to test until it evaluates to true
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* @timeout: maximum number of microseconds in the timeout
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* @index: loop index (integer)
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*
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* Loop waiting for @cond to become true or until at least @timeout
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* microseconds have passed. To use, define some integer @index in the
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* calling code. After running, if @index == @timeout, then the loop has
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* timed out.
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*
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* Copied from omap_test_timeout */
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#define sr_test_cond_timeout(cond, timeout, index) \
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({ \
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for (index = 0; index < timeout; index++) { \
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if (cond) \
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break; \
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udelay(1); \
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} \
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})
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/**
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* struct omap_sr_pmic_data - Strucutre to be populated by pmic code to pass
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* pmic specific info to smartreflex driver
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*
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* @sr_pmic_init: API to initialize smartreflex on the PMIC side.
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*/
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struct omap_sr_pmic_data {
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void (*sr_pmic_init) (void);
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};
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/**
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* struct omap_smartreflex_dev_attr - Smartreflex Device attribute.
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*
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* @sensor_voltdm_name: Name of voltdomain of SR instance
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*/
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struct omap_smartreflex_dev_attr {
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const char *sensor_voltdm_name;
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};
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/*
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* The smart reflex driver supports CLASS1 CLASS2 and CLASS3 SR.
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* The smartreflex class driver should pass the class type.
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* Should be used to populate the class_type field of the
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* omap_smartreflex_class_data structure.
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*/
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#define SR_CLASS1 0x1
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#define SR_CLASS2 0x2
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#define SR_CLASS3 0x3
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/**
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* struct omap_sr_class_data - Smartreflex class driver info
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*
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* @enable: API to enable a particular class smaartreflex.
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* @disable: API to disable a particular class smartreflex.
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* @configure: API to configure a particular class smartreflex.
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* @notify: API to notify the class driver about an event in SR.
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* Not needed for class3.
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* @notify_flags: specify the events to be notified to the class driver
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* @class_type: specify which smartreflex class.
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* Can be used by the SR driver to take any class
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* based decisions.
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*/
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struct omap_sr_class_data {
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int (*enable)(struct omap_sr *sr);
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int (*disable)(struct omap_sr *sr, int is_volt_reset);
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int (*configure)(struct omap_sr *sr);
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int (*notify)(struct omap_sr *sr, u32 status);
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u8 notify_flags;
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u8 class_type;
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};
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/**
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* struct omap_sr_nvalue_table - Smartreflex n-target value info
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*
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* @efuse_offs: The offset of the efuse where n-target values are stored.
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* @nvalue: The n-target value.
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* @errminlimit: The value of the ERRMINLIMIT bitfield for this n-target
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* @volt_nominal: microvolts DC that the VDD is initially programmed to
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*/
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struct omap_sr_nvalue_table {
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u32 efuse_offs;
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u32 nvalue;
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u32 errminlimit;
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unsigned long volt_nominal;
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};
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/**
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* struct omap_sr_data - Smartreflex platform data.
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*
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* @name: instance name
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* @ip_type: Smartreflex IP type.
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* @senp_mod: SENPENABLE value of the sr CONFIG register
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* @senn_mod: SENNENABLE value for sr CONFIG register
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* @err_weight ERRWEIGHT value of the sr ERRCONFIG register
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* @err_maxlimit ERRMAXLIMIT value of the sr ERRCONFIG register
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* @accum_data ACCUMDATA value of the sr CONFIG register
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* @senn_avgweight SENNAVGWEIGHT value of the sr AVGWEIGHT register
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* @senp_avgweight SENPAVGWEIGHT value of the sr AVGWEIGHT register
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* @nvalue_count: Number of distinct nvalues in the nvalue table
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* @enable_on_init: whether this sr module needs to enabled at
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* boot up or not.
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* @nvalue_table: table containing the efuse offsets and nvalues
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* corresponding to them.
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* @voltdm: Pointer to the voltage domain associated with the SR
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*/
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struct omap_sr_data {
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const char *name;
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int ip_type;
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u32 senp_mod;
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u32 senn_mod;
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u32 err_weight;
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u32 err_maxlimit;
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u32 accum_data;
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u32 senn_avgweight;
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u32 senp_avgweight;
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int nvalue_count;
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bool enable_on_init;
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struct omap_sr_nvalue_table *nvalue_table;
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struct voltagedomain *voltdm;
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};
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extern struct omap_sr_data omap_sr_pdata[OMAP_SR_NR];
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#ifdef CONFIG_POWER_AVS_OMAP
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/* Smartreflex module enable/disable interface */
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void omap_sr_enable(struct voltagedomain *voltdm);
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void omap_sr_disable(struct voltagedomain *voltdm);
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void omap_sr_disable_reset_volt(struct voltagedomain *voltdm);
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/* API to register the pmic specific data with the smartreflex driver. */
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void omap_sr_register_pmic(struct omap_sr_pmic_data *pmic_data);
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/* Smartreflex driver hooks to be called from Smartreflex class driver */
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int sr_enable(struct omap_sr *sr, unsigned long volt);
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void sr_disable(struct omap_sr *sr);
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int sr_configure_errgen(struct omap_sr *sr);
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int sr_disable_errgen(struct omap_sr *sr);
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int sr_configure_minmax(struct omap_sr *sr);
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/* API to register the smartreflex class driver with the smartreflex driver */
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int sr_register_class(struct omap_sr_class_data *class_data);
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#else
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static inline void omap_sr_enable(struct voltagedomain *voltdm) {}
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static inline void omap_sr_disable(struct voltagedomain *voltdm) {}
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static inline void omap_sr_disable_reset_volt(
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struct voltagedomain *voltdm) {}
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static inline void omap_sr_register_pmic(
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struct omap_sr_pmic_data *pmic_data) {}
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#endif
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#endif
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