331 lines
9.2 KiB
C
331 lines
9.2 KiB
C
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/*
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* Copyright (C) 1999-2002 Andre Hedrick <andre@linux-ide.org>
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* Copyright (C) 2007 MontaVista Software, Inc. <source@mvista.com>
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*
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#include <linux/init.h>
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#include <asm/io.h>
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#define DRV_NAME "aec62xx"
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struct chipset_bus_clock_list_entry {
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u8 xfer_speed;
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u8 chipset_settings;
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u8 ultra_settings;
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};
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static const struct chipset_bus_clock_list_entry aec6xxx_33_base [] = {
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{ XFER_UDMA_6, 0x31, 0x07 },
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{ XFER_UDMA_5, 0x31, 0x06 },
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{ XFER_UDMA_4, 0x31, 0x05 },
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{ XFER_UDMA_3, 0x31, 0x04 },
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{ XFER_UDMA_2, 0x31, 0x03 },
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{ XFER_UDMA_1, 0x31, 0x02 },
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{ XFER_UDMA_0, 0x31, 0x01 },
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{ XFER_MW_DMA_2, 0x31, 0x00 },
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{ XFER_MW_DMA_1, 0x31, 0x00 },
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{ XFER_MW_DMA_0, 0x0a, 0x00 },
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{ XFER_PIO_4, 0x31, 0x00 },
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{ XFER_PIO_3, 0x33, 0x00 },
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{ XFER_PIO_2, 0x08, 0x00 },
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{ XFER_PIO_1, 0x0a, 0x00 },
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{ XFER_PIO_0, 0x00, 0x00 },
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{ 0, 0x00, 0x00 }
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};
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static const struct chipset_bus_clock_list_entry aec6xxx_34_base [] = {
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{ XFER_UDMA_6, 0x41, 0x06 },
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{ XFER_UDMA_5, 0x41, 0x05 },
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{ XFER_UDMA_4, 0x41, 0x04 },
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{ XFER_UDMA_3, 0x41, 0x03 },
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{ XFER_UDMA_2, 0x41, 0x02 },
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{ XFER_UDMA_1, 0x41, 0x01 },
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{ XFER_UDMA_0, 0x41, 0x01 },
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{ XFER_MW_DMA_2, 0x41, 0x00 },
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{ XFER_MW_DMA_1, 0x42, 0x00 },
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{ XFER_MW_DMA_0, 0x7a, 0x00 },
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{ XFER_PIO_4, 0x41, 0x00 },
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{ XFER_PIO_3, 0x43, 0x00 },
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{ XFER_PIO_2, 0x78, 0x00 },
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{ XFER_PIO_1, 0x7a, 0x00 },
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{ XFER_PIO_0, 0x70, 0x00 },
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{ 0, 0x00, 0x00 }
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};
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/*
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* TO DO: active tuning and correction of cards without a bios.
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*/
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static u8 pci_bus_clock_list (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
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{
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for ( ; chipset_table->xfer_speed ; chipset_table++)
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if (chipset_table->xfer_speed == speed) {
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return chipset_table->chipset_settings;
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}
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return chipset_table->chipset_settings;
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}
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static u8 pci_bus_clock_list_ultra (u8 speed, struct chipset_bus_clock_list_entry * chipset_table)
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{
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for ( ; chipset_table->xfer_speed ; chipset_table++)
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if (chipset_table->xfer_speed == speed) {
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return chipset_table->ultra_settings;
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}
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return chipset_table->ultra_settings;
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}
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static void aec6210_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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struct ide_host *host = pci_get_drvdata(dev);
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struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
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u16 d_conf = 0;
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u8 ultra = 0, ultra_conf = 0;
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u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;
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const u8 speed = drive->dma_mode;
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unsigned long flags;
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local_irq_save(flags);
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/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */
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pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);
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tmp0 = pci_bus_clock_list(speed, bus_clock);
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d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);
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pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);
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tmp1 = 0x00;
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tmp2 = 0x00;
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pci_read_config_byte(dev, 0x54, &ultra);
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tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));
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ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
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tmp2 = ((ultra_conf << (2*drive->dn)) | (tmp1 & ~(3 << (2*drive->dn))));
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pci_write_config_byte(dev, 0x54, tmp2);
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local_irq_restore(flags);
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}
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static void aec6260_set_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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struct ide_host *host = pci_get_drvdata(dev);
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struct chipset_bus_clock_list_entry *bus_clock = host->host_priv;
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u8 unit = drive->dn & 1;
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u8 tmp1 = 0, tmp2 = 0;
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u8 ultra = 0, drive_conf = 0, ultra_conf = 0;
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const u8 speed = drive->dma_mode;
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unsigned long flags;
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local_irq_save(flags);
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/* high 4-bits: Active, low 4-bits: Recovery */
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pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);
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drive_conf = pci_bus_clock_list(speed, bus_clock);
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pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);
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pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);
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tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));
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ultra_conf = pci_bus_clock_list_ultra(speed, bus_clock);
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tmp2 = ((ultra_conf << (4*unit)) | (tmp1 & ~(7 << (4*unit))));
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pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);
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local_irq_restore(flags);
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}
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static void aec_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
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{
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drive->dma_mode = drive->pio_mode;
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hwif->port_ops->set_dma_mode(hwif, drive);
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}
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static int init_chipset_aec62xx(struct pci_dev *dev)
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{
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/* These are necessary to get AEC6280 Macintosh cards to work */
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if ((dev->device == PCI_DEVICE_ID_ARTOP_ATP865) ||
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(dev->device == PCI_DEVICE_ID_ARTOP_ATP865R)) {
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u8 reg49h = 0, reg4ah = 0;
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/* Clear reset and test bits. */
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pci_read_config_byte(dev, 0x49, ®49h);
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pci_write_config_byte(dev, 0x49, reg49h & ~0x30);
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/* Enable chip interrupt output. */
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pci_read_config_byte(dev, 0x4a, ®4ah);
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pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);
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/* Enable burst mode. */
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pci_read_config_byte(dev, 0x4a, ®4ah);
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pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);
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}
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return 0;
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}
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static u8 atp86x_cable_detect(ide_hwif_t *hwif)
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{
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struct pci_dev *dev = to_pci_dev(hwif->dev);
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u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;
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pci_read_config_byte(dev, 0x49, &ata66);
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return (ata66 & mask) ? ATA_CBL_PATA40 : ATA_CBL_PATA80;
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}
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static const struct ide_port_ops atp850_port_ops = {
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.set_pio_mode = aec_set_pio_mode,
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.set_dma_mode = aec6210_set_mode,
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};
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static const struct ide_port_ops atp86x_port_ops = {
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.set_pio_mode = aec_set_pio_mode,
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.set_dma_mode = aec6260_set_mode,
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.cable_detect = atp86x_cable_detect,
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};
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static const struct ide_port_info aec62xx_chipsets[] = {
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{ /* 0: AEC6210 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_aec62xx,
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.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
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.port_ops = &atp850_port_ops,
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.host_flags = IDE_HFLAG_SERIALIZE |
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IDE_HFLAG_NO_ATAPI_DMA |
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IDE_HFLAG_NO_DSC |
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IDE_HFLAG_OFF_BOARD,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA2,
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},
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{ /* 1: AEC6260 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_aec62xx,
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.port_ops = &atp86x_port_ops,
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.host_flags = IDE_HFLAG_NO_ATAPI_DMA | IDE_HFLAG_NO_AUTODMA |
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IDE_HFLAG_OFF_BOARD,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA4,
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},
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{ /* 2: AEC6260R */
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.name = DRV_NAME,
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.init_chipset = init_chipset_aec62xx,
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.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
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.port_ops = &atp86x_port_ops,
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.host_flags = IDE_HFLAG_NO_ATAPI_DMA |
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IDE_HFLAG_NON_BOOTABLE,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA4,
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},
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{ /* 3: AEC6280 */
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.name = DRV_NAME,
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.init_chipset = init_chipset_aec62xx,
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.port_ops = &atp86x_port_ops,
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.host_flags = IDE_HFLAG_NO_ATAPI_DMA |
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IDE_HFLAG_OFF_BOARD,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA5,
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},
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{ /* 4: AEC6280R */
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.name = DRV_NAME,
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.init_chipset = init_chipset_aec62xx,
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.enablebits = {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
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.port_ops = &atp86x_port_ops,
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.host_flags = IDE_HFLAG_NO_ATAPI_DMA |
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IDE_HFLAG_OFF_BOARD,
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.pio_mask = ATA_PIO4,
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.mwdma_mask = ATA_MWDMA2,
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.udma_mask = ATA_UDMA5,
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}
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};
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/**
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* aec62xx_init_one - called when a AEC is found
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* @dev: the aec62xx device
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* @id: the matching pci id
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*
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* Called when the PCI registration layer (or the IDE initialization)
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* finds a device matching our IDE device tables.
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*
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* NOTE: since we're going to modify the 'name' field for AEC-6[26]80[R]
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* chips, pass a local copy of 'struct ide_port_info' down the call chain.
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*/
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static int aec62xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
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{
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const struct chipset_bus_clock_list_entry *bus_clock;
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struct ide_port_info d;
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u8 idx = id->driver_data;
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int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
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int err;
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if (bus_speed <= 33)
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bus_clock = aec6xxx_33_base;
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else
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bus_clock = aec6xxx_34_base;
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err = pci_enable_device(dev);
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if (err)
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return err;
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d = aec62xx_chipsets[idx];
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if (idx == 3 || idx == 4) {
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unsigned long dma_base = pci_resource_start(dev, 4);
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if (inb(dma_base + 2) & 0x10) {
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printk(KERN_INFO DRV_NAME " %s: AEC6880%s card detected"
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"\n", pci_name(dev), (idx == 4) ? "R" : "");
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d.udma_mask = ATA_UDMA6;
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}
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}
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err = ide_pci_init_one(dev, &d, (void *)bus_clock);
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if (err)
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pci_disable_device(dev);
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return err;
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}
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static void aec62xx_remove(struct pci_dev *dev)
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{
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ide_pci_remove(dev);
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pci_disable_device(dev);
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}
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static const struct pci_device_id aec62xx_pci_tbl[] = {
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{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
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{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860), 1 },
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{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP860R), 2 },
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{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865), 3 },
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{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP865R), 4 },
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{ 0, },
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};
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MODULE_DEVICE_TABLE(pci, aec62xx_pci_tbl);
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static struct pci_driver aec62xx_pci_driver = {
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.name = "AEC62xx_IDE",
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.id_table = aec62xx_pci_tbl,
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.probe = aec62xx_init_one,
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.remove = aec62xx_remove,
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.suspend = ide_pci_suspend,
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.resume = ide_pci_resume,
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};
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static int __init aec62xx_ide_init(void)
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{
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return ide_pci_register_driver(&aec62xx_pci_driver);
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}
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static void __exit aec62xx_ide_exit(void)
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{
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pci_unregister_driver(&aec62xx_pci_driver);
|
||
|
|
}
|
||
|
|
|
||
|
|
module_init(aec62xx_ide_init);
|
||
|
|
module_exit(aec62xx_ide_exit);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Andre Hedrick");
|
||
|
|
MODULE_DESCRIPTION("PCI driver module for ARTOP AEC62xx IDE");
|
||
|
|
MODULE_LICENSE("GPL");
|