530 lines
10 KiB
C
530 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/io.h>
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#include <linux/export.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/cpumask.h>
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#include <linux/cpu.h>
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/* #include <mt-plat/mtk_io.h> */
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/* #include <mt-plat/sync_write.h> */
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/* include <mt-plat/mtk_secure_api.h> */
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#include "mt6765_dcm_internal.h"
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#include "mtk_dcm.h"
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#define DEBUGLINE dcm_pr_info("%s %d\n", __func__, __LINE__)
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static short dcm_cpu_cluster_stat;
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static short dcm_debug_stat;
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unsigned int all_dcm_type =
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(ARMCORE_DCM_TYPE | MCUSYS_DCM_TYPE | MCSI_DCM_TYPE
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| STALL_DCM_TYPE | RGU_DCM_TYPE
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| GIC_SYNC_DCM_TYPE | INFRA_DCM_TYPE
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| DDRPHY_DCM_TYPE | EMI_DCM_TYPE | DRAMC_DCM_TYPE
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);
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unsigned int init_dcm_type =
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(ARMCORE_DCM_TYPE | MCUSYS_DCM_TYPE | MCSI_DCM_TYPE
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| STALL_DCM_TYPE
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| GIC_SYNC_DCM_TYPE | INFRA_DCM_TYPE
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);
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#if defined(__KERNEL__) && defined(CONFIG_OF)
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unsigned long dcm_infracfg_ao_base;
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unsigned long dcm_mcucfg_base;
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unsigned long dcm_mp0_cpucfg_base;
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unsigned long dcm_mp1_cpucfg_base;
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unsigned long dcm_mcu_misccfg_base;
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unsigned long dcm_chn0_emi_base;
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unsigned long dcm_chn1_emi_base;
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unsigned long dcm_gce_base;
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unsigned long dcm_audio_base;
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unsigned long dcm_efusec_base;
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unsigned long dcm_mfgcfg_base;
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unsigned long dcm_mmsys_config_base;
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unsigned long dcm_smi_common_base;
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unsigned long dcm_smi_larb0_base;
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unsigned long dcm_smi_larb2_base;
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unsigned long dcm_smi_larb1_base;
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unsigned long dcm_venc_base;
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unsigned long dcm_jpgenc_base;
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#define DCM_NODE "mediatek,mt6765-dcm"
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#endif /* #if defined(__KERNEL__) && defined(CONFIG_OF) */
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short is_dcm_bringup(void)
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{
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#ifdef DCM_BRINGUP
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dcm_pr_info("%s: skipped for bring up\n", __func__);
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return 1;
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#else
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return 0;
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#endif
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}
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/*****************************************
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* following is implementation per DCM module.
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* 1. per-DCM function is 1-argu with ON/OFF/MODE option.
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*****************************************/
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int dcm_topckg(int on)
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{
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return 0;
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}
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void dcm_infracfg_ao_emi_indiv(int on)
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{
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}
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int dcm_infra_preset(int on)
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{
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return 0;
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}
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int dcm_infra(int on)
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{
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dcm_infracfg_ao_audio(on);
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dcm_infracfg_ao_icusb(on);
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dcm_infracfg_ao_infra_mem(on);
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dcm_infracfg_ao_infra_peri(on);
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dcm_infracfg_ao_p2p_dsi_csi(on);
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dcm_infracfg_ao_ssusb(on);
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return 0;
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}
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int dcm_peri(int on)
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{
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return 0;
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}
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int dcm_armcore(int on)
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{
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dcm_mcu_misccfg_bus_arm_pll_divider_dcm(on);
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dcm_mcu_misccfg_mp0_arm_pll_divider_dcm(on);
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dcm_mcu_misccfg_mp1_arm_pll_divider_dcm(on);
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return 0;
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}
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int dcm_mcusys(int on)
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{
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dcm_mcu_misccfg_adb400_dcm(on);
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dcm_mcu_misccfg_bus_sync_dcm(on);
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dcm_mcu_misccfg_bus_clock_dcm(on);
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dcm_mcu_misccfg_bus_fabric_dcm(on);
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dcm_mcu_misccfg_l2_shared_dcm(on);
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dcm_mcu_misccfg_mp0_sync_dcm_enable(on);
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dcm_mcu_misccfg_mp1_sync_dcm_enable(on);
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dcm_mcu_misccfg_mcu_misc_dcm(on);
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return 0;
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}
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int dcm_mcusys_preset(int on)
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{
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return 0;
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}
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int dcm_big_core_preset(void)
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{
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return 0;
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}
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int dcm_big_core(int on)
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{
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return 0;
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}
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int dcm_stall_preset(int on)
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{
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reg_write(SYNC_DCM_CLUSTER_CONFIG, 0x063f0000);
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return 0;
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}
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int dcm_stall(int on)
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{
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dcm_mcu_misccfg_mp0_stall_dcm(on);
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dcm_mcu_misccfg_mp1_stall_dcm(on);
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return 0;
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}
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int dcm_gic_sync(int on)
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{
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dcm_mcu_misccfg_gic_sync_dcm(on);
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return 0;
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}
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int dcm_last_core(int on)
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{
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return 0;
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}
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int dcm_rgu(int on)
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{
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dcm_mp0_cpucfg_mp0_rgu_dcm(on);
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dcm_mp1_cpucfg_mp1_rgu_dcm(on);
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return 0;
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}
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int dcm_dramc_ao(int on)
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{
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return 0;
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}
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int dcm_ddrphy(int on)
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{
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return 0;
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}
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int dcm_emi(int on)
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{
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dcm_chn0_emi_dcm_emi_group(on);
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dcm_chn1_emi_dcm_emi_group(on);
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return 0;
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}
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int dcm_lpdma(int on)
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{
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return 0;
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}
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int dcm_pwrap(int on)
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{
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return 0;
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}
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int dcm_mcsi_preset(int on)
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{
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return 0;
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}
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int dcm_mcsi(int on)
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{
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dcm_mcucfg_mcsi_dcm(on);
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return 0;
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}
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void dcm_dump_regs(void)
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{
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dcm_pr_info("\n******** dcm dump register *********\n");
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/* MCUSYS reg */
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/* ARMCORE reg */
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/* STALL reg */
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/* INFRA_AO reg */
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REG_DUMP(PERI_BUS_DCM_CTRL);
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REG_DUMP(DFS_MEM_DCM_CTRL);
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REG_DUMP(PERI_BUS_DCM_CTRL);
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REG_DUMP(INFRA_MISC);
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REG_DUMP(MEM_DCM_CTRL);
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REG_DUMP(INFRA_BUS_DCM_CTRL);
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REG_DUMP(PERI_BUS_DCM_CTRL);
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REG_DUMP(P2P_RX_CLK_ON);
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REG_DUMP(PERI_BUS_DCM_CTRL);
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REG_DUMP(PERI_BUS_DCM_CTRL);
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REG_DUMP(PERI_BUS_DCM_CTRL);
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/* INFRA_AO_MEM reg */
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/* SUB INFRA reg */
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/* INFRA EMI reg */
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/* emi */
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REG_DUMP(CHN0_EMI_CHN_EMI_CONB);
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REG_DUMP(CHN1_EMI_CHN_EMI_CONB);
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/* dramc */
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/* ddrphy */
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}
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void get_default(unsigned int *type, int *state)
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{
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#ifndef DCM_DEFAULT_ALL_OFF
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/** enable all dcm **/
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*type = init_dcm_type;
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*state = DCM_DEFAULT;
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#else /* DCM_DEFAULT_ALL_OFF */
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*type = all_dcm_type;
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*state = DCM_OFF;
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#endif /* #ifndef DCM_DEFAULT_ALL_OFF */
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}
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void get_init_type(unsigned int *type)
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{
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*type = init_dcm_type;
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}
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void get_all_type(unsigned int *type)
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{
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*type = all_dcm_type;
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}
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void get_init_by_k_type(unsigned int *type)
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{
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#ifdef ENABLE_DCM_IN_LK
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*type = INIT_DCM_TYPE_BY_K;
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#else
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*type = init_dcm_type;
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#endif
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}
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void set_debug_mode(unsigned int mode)
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{
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dcm_debug_stat = mode;
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}
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struct DCM_OPS dcm_ops = {
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.dump_regs = (DCM_FUNC_VOID_VOID) dcm_dump_regs,
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.get_default = (DCM_FUNC_VOID_UINTR_INTR) get_default,
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.get_init_type = (DCM_FUNC_VOID_UINTR) get_init_type,
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.get_all_type = (DCM_FUNC_VOID_UINTR) get_all_type,
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.get_init_by_k_type = (DCM_FUNC_VOID_UINTR) get_init_by_k_type,
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.set_debug_mode = (DCM_FUNC_VOID_UINT) set_debug_mode,
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};
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struct DCM_BASE dcm_base_array[] = {
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DCM_BASE_INFO(dcm_infracfg_ao_base),
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DCM_BASE_INFO(dcm_mcucfg_base),
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DCM_BASE_INFO(dcm_mp0_cpucfg_base),
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DCM_BASE_INFO(dcm_mp1_cpucfg_base),
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DCM_BASE_INFO(dcm_mcu_misccfg_base),
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DCM_BASE_INFO(dcm_chn0_emi_base),
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DCM_BASE_INFO(dcm_chn1_emi_base),
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DCM_BASE_INFO(dcm_gce_base),
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DCM_BASE_INFO(dcm_audio_base),
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DCM_BASE_INFO(dcm_efusec_base),
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DCM_BASE_INFO(dcm_mfgcfg_base),
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DCM_BASE_INFO(dcm_mmsys_config_base),
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DCM_BASE_INFO(dcm_smi_common_base),
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DCM_BASE_INFO(dcm_smi_larb0_base),
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DCM_BASE_INFO(dcm_smi_larb2_base),
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DCM_BASE_INFO(dcm_smi_larb1_base),
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DCM_BASE_INFO(dcm_venc_base),
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DCM_BASE_INFO(dcm_jpgenc_base),
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};
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struct DCM dcm_array[NR_DCM_TYPE] = {
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{
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.typeid = ARMCORE_DCM_TYPE,
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.name = "ARMCORE_DCM",
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.func = (DCM_FUNC) dcm_armcore,
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.current_state = ARMCORE_DCM_MODE1,
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.default_state = ARMCORE_DCM_MODE1,
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.disable_refcnt = 0,
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},
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{
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.typeid = MCUSYS_DCM_TYPE,
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.name = "MCUSYS_DCM",
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.func = (DCM_FUNC) dcm_mcusys,
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.current_state = MCUSYS_DCM_ON,
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.default_state = MCUSYS_DCM_ON,
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.disable_refcnt = 0,
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},
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{
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.typeid = INFRA_DCM_TYPE,
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.name = "INFRA_DCM",
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.func = (DCM_FUNC) dcm_infra,
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.current_state = INFRA_DCM_ON,
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.default_state = INFRA_DCM_ON,
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.disable_refcnt = 0,
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},
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{
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.typeid = PERI_DCM_TYPE,
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.name = "PERI_DCM",
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.func = (DCM_FUNC) dcm_peri,
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.current_state = PERI_DCM_ON,
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.default_state = PERI_DCM_ON,
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.disable_refcnt = 0,
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},
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{
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.typeid = EMI_DCM_TYPE,
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.name = "EMI_DCM",
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.func = (DCM_FUNC) dcm_emi,
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.current_state = EMI_DCM_ON,
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.default_state = EMI_DCM_ON,
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.disable_refcnt = 0,
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},
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{
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.typeid = DRAMC_DCM_TYPE,
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.name = "DRAMC_DCM",
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.func = (DCM_FUNC) dcm_dramc_ao,
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.current_state = DRAMC_AO_DCM_ON,
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.default_state = DRAMC_AO_DCM_ON,
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.disable_refcnt = 0,
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},
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{
|
||
|
|
.typeid = DDRPHY_DCM_TYPE,
|
||
|
|
.name = "DDRPHY_DCM",
|
||
|
|
.func = (DCM_FUNC) dcm_ddrphy,
|
||
|
|
.current_state = DDRPHY_DCM_ON,
|
||
|
|
.default_state = DDRPHY_DCM_ON,
|
||
|
|
.disable_refcnt = 0,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.typeid = STALL_DCM_TYPE,
|
||
|
|
.name = "STALL_DCM",
|
||
|
|
.func = (DCM_FUNC) dcm_stall,
|
||
|
|
.current_state = STALL_DCM_ON,
|
||
|
|
.default_state = STALL_DCM_ON,
|
||
|
|
.disable_refcnt = 0,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.typeid = BIG_CORE_DCM_TYPE,
|
||
|
|
.name = "BIG_CORE_DCM",
|
||
|
|
.func = (DCM_FUNC) dcm_big_core,
|
||
|
|
.current_state = BIG_CORE_DCM_ON,
|
||
|
|
.default_state = BIG_CORE_DCM_ON,
|
||
|
|
.disable_refcnt = 0,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.typeid = GIC_SYNC_DCM_TYPE,
|
||
|
|
.name = "GIC_SYNC_DCM",
|
||
|
|
.func = (DCM_FUNC) dcm_gic_sync,
|
||
|
|
.current_state = GIC_SYNC_DCM_ON,
|
||
|
|
.default_state = GIC_SYNC_DCM_ON,
|
||
|
|
.disable_refcnt = 0,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.typeid = LAST_CORE_DCM_TYPE,
|
||
|
|
.name = "LAST_CORE_DCM",
|
||
|
|
.func = (DCM_FUNC) dcm_last_core,
|
||
|
|
.current_state = LAST_CORE_DCM_ON,
|
||
|
|
.default_state = LAST_CORE_DCM_ON,
|
||
|
|
.disable_refcnt = 0,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.typeid = RGU_DCM_TYPE,
|
||
|
|
.name = "RGU_CORE_DCM",
|
||
|
|
.func = (DCM_FUNC) dcm_rgu,
|
||
|
|
.current_state = RGU_DCM_ON,
|
||
|
|
.default_state = RGU_DCM_ON,
|
||
|
|
.disable_refcnt = 0,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.typeid = TOPCKG_DCM_TYPE,
|
||
|
|
.name = "TOPCKG_DCM",
|
||
|
|
.func = (DCM_FUNC) dcm_topckg,
|
||
|
|
.current_state = TOPCKG_DCM_ON,
|
||
|
|
.default_state = TOPCKG_DCM_ON,
|
||
|
|
.disable_refcnt = 0,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.typeid = LPDMA_DCM_TYPE,
|
||
|
|
.name = "LPDMA_DCM",
|
||
|
|
.func = (DCM_FUNC) dcm_lpdma,
|
||
|
|
.current_state = LPDMA_DCM_ON,
|
||
|
|
.default_state = LPDMA_DCM_ON,
|
||
|
|
.disable_refcnt = 0,
|
||
|
|
},
|
||
|
|
{
|
||
|
|
.typeid = MCSI_DCM_TYPE,
|
||
|
|
.name = "MCSI_DCM",
|
||
|
|
.func = (DCM_FUNC) dcm_mcsi,
|
||
|
|
.current_state = MCSI_DCM_ON,
|
||
|
|
.default_state = MCSI_DCM_ON,
|
||
|
|
.disable_refcnt = 0,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
void dcm_set_hotplug_nb(void) {}
|
||
|
|
|
||
|
|
short dcm_get_cpu_cluster_stat(void)
|
||
|
|
{
|
||
|
|
return dcm_cpu_cluster_stat;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**/
|
||
|
|
void dcm_array_register(void)
|
||
|
|
{
|
||
|
|
mt_dcm_array_register(dcm_array, &dcm_ops);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*From DCM COMMON*/
|
||
|
|
|
||
|
|
#ifdef CONFIG_OF
|
||
|
|
int mt_dcm_dts_map(void)
|
||
|
|
{
|
||
|
|
struct device_node *node;
|
||
|
|
unsigned int i;
|
||
|
|
/* dcm */
|
||
|
|
node = of_find_compatible_node(NULL, NULL, DCM_NODE);
|
||
|
|
if (!node) {
|
||
|
|
dcm_pr_info("error: cannot find node %s\n", DCM_NODE);
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
for (i = 0; i < ARRAY_SIZE(dcm_base_array); i++) {
|
||
|
|
//*dcm_base_array[i].base= (unsigned long)of_iomap(node, i);
|
||
|
|
*(dcm_base_array[i].base) = (unsigned long)of_iomap(node, i);
|
||
|
|
|
||
|
|
if (!*(dcm_base_array[i].base)) {
|
||
|
|
dcm_pr_info("error: cannot iomap base %s\n",
|
||
|
|
dcm_base_array[i].name);
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
/* infracfg_ao */
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#else
|
||
|
|
int mt_dcm_dts_map(void)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
#endif /* #ifdef CONFIG_PM */
|
||
|
|
|
||
|
|
|
||
|
|
void dcm_pre_init(void)
|
||
|
|
{
|
||
|
|
dcm_pr_info("weak function of %s\n", __func__);
|
||
|
|
}
|
||
|
|
|
||
|
|
static int __init mt6765_dcm_init(void)
|
||
|
|
{
|
||
|
|
int ret = 0;
|
||
|
|
|
||
|
|
if (is_dcm_bringup())
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
if (is_dcm_initialized())
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
if (mt_dcm_dts_map()) {
|
||
|
|
dcm_pr_notice("%s: failed due to DTS failed\n", __func__);
|
||
|
|
return -1;
|
||
|
|
}
|
||
|
|
|
||
|
|
dcm_array_register();
|
||
|
|
|
||
|
|
ret = mt_dcm_common_init();
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void __exit mt6765_dcm_exit(void)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
MODULE_SOFTDEP("pre:mtk_dcm.ko");
|
||
|
|
module_init(mt6765_dcm_init);
|
||
|
|
module_exit(mt6765_dcm_exit);
|
||
|
|
|
||
|
|
MODULE_LICENSE("GPL v2");
|
||
|
|
MODULE_DESCRIPTION("MediaTek DCM driver");
|