139 lines
4.3 KiB
Plaintext
139 lines
4.3 KiB
Plaintext
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* DMA40 DMA Controller
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Required properties:
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- compatible: "stericsson,dma40"
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- reg: Address range of the DMAC registers
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- reg-names: Names of the above areas to use during resource look-up
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- interrupt: Should contain the DMAC interrupt number
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- #dma-cells: must be <3>
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- memcpy-channels: Channels to be used for memcpy
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Optional properties:
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- dma-channels: Number of channels supported by hardware - if not present
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the driver will attempt to obtain the information from H/W
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- disabled-channels: Channels which can not be used
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Example:
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dma: dma-controller@801c0000 {
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compatible = "stericsson,db8500-dma40", "stericsson,dma40";
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reg = <0x801C0000 0x1000 0x40010000 0x800>;
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reg-names = "base", "lcpa";
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interrupt-parent = <&intc>;
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interrupts = <0 25 0x4>;
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#dma-cells = <2>;
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memcpy-channels = <56 57 58 59 60>;
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disabled-channels = <12>;
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dma-channels = <8>;
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};
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Clients
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Required properties:
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- dmas: Comma separated list of dma channel requests
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- dma-names: Names of the aforementioned requested channels
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Each dmas request consists of 4 cells:
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1. A phandle pointing to the DMA controller
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2. Device signal number, the signal line for single and burst requests
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connected from the device to the DMA40 engine
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3. The DMA request line number (only when 'use fixed channel' is set)
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4. A 32bit mask specifying; mode, direction and endianness
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[NB: This list will grow]
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0x00000001: Mode:
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Logical channel when unset
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Physical channel when set
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0x00000002: Direction:
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Memory to Device when unset
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Device to Memory when set
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0x00000004: Endianness:
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Little endian when unset
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Big endian when set
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0x00000008: Use fixed channel:
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Use automatic channel selection when unset
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Use DMA request line number when set
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0x00000010: Set channel as high priority:
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Normal priority when unset
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High priority when set
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Existing signal numbers for the DB8500 ASIC. Unless specified, the signals are
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bidirectional, i.e. the same for RX and TX operations:
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0: SPI controller 0
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1: SD/MMC controller 0 (unused)
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2: SD/MMC controller 1 (unused)
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3: SD/MMC controller 2 (unused)
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4: I2C port 1
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5: I2C port 3
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6: I2C port 2
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7: I2C port 4
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8: Synchronous Serial Port SSP0
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9: Synchronous Serial Port SSP1
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10: Multi-Channel Display Engine MCDE RX
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11: UART port 2
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12: UART port 1
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13: UART port 0
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14: Multirate Serial Port MSP2
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15: I2C port 0
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16: USB OTG in/out endpoints 7 & 15
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17: USB OTG in/out endpoints 6 & 14
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18: USB OTG in/out endpoints 5 & 13
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19: USB OTG in/out endpoints 4 & 12
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20: SLIMbus or HSI channel 0
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21: SLIMbus or HSI channel 1
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22: SLIMbus or HSI channel 2
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23: SLIMbus or HSI channel 3
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24: Multimedia DSP SXA0
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25: Multimedia DSP SXA1
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26: Multimedia DSP SXA2
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27: Multimedia DSP SXA3
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28: SD/MM controller 2
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29: SD/MM controller 0
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30: MSP port 1 on DB8500 v1, MSP port 3 on DB8500 v2
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31: MSP port 0 or SLIMbus channel 0
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32: SD/MM controller 1
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33: SPI controller 2
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34: i2c3 RX2 TX2
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35: SPI controller 1
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36: USB OTG in/out endpoints 3 & 11
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37: USB OTG in/out endpoints 2 & 10
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38: USB OTG in/out endpoints 1 & 9
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39: USB OTG in/out endpoints 8
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40: SPI controller 3
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41: SD/MM controller 3
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42: SD/MM controller 4
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43: SD/MM controller 5
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44: Multimedia DSP SXA4
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45: Multimedia DSP SXA5
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46: SLIMbus channel 8 or Multimedia DSP SXA6
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47: SLIMbus channel 9 or Multimedia DSP SXA7
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48: Crypto Accelerator 1
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49: Crypto Accelerator 1 TX or Hash Accelerator 1 TX
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50: Hash Accelerator 1 TX
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51: memcpy TX (to be used by the DMA driver for memcpy operations)
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52: SLIMbus or HSI channel 4
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53: SLIMbus or HSI channel 5
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54: SLIMbus or HSI channel 6
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55: SLIMbus or HSI channel 7
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56: memcpy (to be used by the DMA driver for memcpy operations)
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57: memcpy (to be used by the DMA driver for memcpy operations)
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58: memcpy (to be used by the DMA driver for memcpy operations)
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59: memcpy (to be used by the DMA driver for memcpy operations)
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60: memcpy (to be used by the DMA driver for memcpy operations)
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61: Crypto Accelerator 0
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62: Crypto Accelerator 0 TX or Hash Accelerator 0 TX
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63: Hash Accelerator 0 TX
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Example:
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uart@80120000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x80120000 0x1000>;
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interrupts = <0 11 0x4>;
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dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
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<&dma 13 0 0x0>; /* Logical - MemToDev */
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dma-names = "rx", "rx";
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};
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