94 lines
2 KiB
C
94 lines
2 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#ifndef __HELIO_DVFSRC_MT6768_H
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#define __HELIO_DVFSRC_MT6768_H
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#include <mach/upmu_hw.h>
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#define PMIC_VCORE_ADDR PMIC_RG_BUCK_VCORE_VOSEL
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#define VCORE_BASE_UV 500000
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#define VCORE_STEP_UV 6250
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/* DVFSRC_BASIC_CONTROL 0x0 */
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#define DVFSRC_EN_SHIFT 0
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#define DVFSRC_EN_MASK 0x1
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#define DVFSRC_OUT_EN_SHIFT 8
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#define DVFSRC_OUT_EN_MASK 0x1
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#define FORCE_EN_CUR_SHIFT 14
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#define FORCE_EN_CUR_MASK 0x1
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#define FORCE_EN_TAR_SHIFT 15
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#define FORCE_EN_TAR_MASK 0x1
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/* DVFSRC_SW_REQ 0x4 */
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#define EMI_SW_AP_SHIFT 0
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#define EMI_SW_AP_MASK 0x3
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#define VCORE_SW_AP_SHIFT 2
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#define VCORE_SW_AP_MASK 0x3
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/* DVFSRC_SW_REQ2 0x8 */
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#define EMI_SW_AP2_SHIFT 0
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#define EMI_SW_AP2_MASK 0x3
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#define VCORE_SW_AP2_SHIFT 2
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#define VCORE_SW_AP2_MASK 0x3
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/* DVFSRC_VCORE_REQUEST 0x48 */
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#define VCORE_SCP_GEAR_SHIFT 30
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#define VCORE_SCP_GEAR_MASK 0x3
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/* DVFSRC_VCORE_REQUEST2 0x4C */
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#define VCORE_QOS_GEAR0_SHIFT 24
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#define VCORE_QOS_GEAR0_MASK 0x3
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/* DVFSRC_LEVEL 0xDC */
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#define CURRENT_LEVEL_SHIFT 16
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#define CURRENT_LEVEL_MASK 0xFFFF
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/* DVFSRC_FORCE 0x300 */
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#define TARGET_FORCE_SHIFT 0
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#define TARGET_FORCE_MASK 0xFFFF
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#define CURRENT_FORCE_SHIFT 16
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#define CURRENT_FORCE_MASK 0xFFFF
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/* met profile table index */
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enum met_info_index {
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INFO_OPP_IDX = 0,
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INFO_FREQ_IDX,
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INFO_VCORE_IDX,
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INFO_SPM_LEVEL_IDX,
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INFO_MAX,
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};
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enum met_src_index {
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SRC_MD2SPM_IDX,
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DDR_OPP_IDX,
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DDR_SW_REQ1_PMQOS_IDX,
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DDR_SW_REQ2_CM_IDX,
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DDR_EMI_TOTAL_IDX,
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DDR_QOS_BW_IDX,
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VCORE_OPP_IDX,
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VCORE_SW_REQ1_PMQOS_IDX,
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VCORE_SW_REQ2_CM_IDX,
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VCORE_SCP_IDX,
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SRC_TOTAL_EMI_BW_IDX,
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SRC_PMQOS_TATOL_IDX,
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SRC_PMQOS_BW0_IDX,
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SRC_PMQOS_BW1_IDX,
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SRC_PMQOS_BW2_IDX,
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SRC_PMQOS_BW3_IDX,
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SRC_PMQOS_BW4_IDX,
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SRC_MD_REQ_OPP,
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BWMON_TOTAL_BW_IDX,
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BWMON_CPU_BW_IDX,
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BWMON_GPU_BW_IDX,
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BWMON_MM_BW_IDX,
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SRC_MAX
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};
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extern void dvfsrc_enable_dvfs_freq_hopping(int gps_on);
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extern int dvfsrc_get_dvfs_freq_hopping_status(void);
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#endif /* __HELIO_DVFSRC_MT6768_H */
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