319 lines
8 KiB
C
319 lines
8 KiB
C
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/*
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* Copyright © 2007 Dave Mueller
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Dave Mueller <dave.mueller@gmx.ch>
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*
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*/
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#include "dvo.h"
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/* register definitions according to the TFP410 data sheet */
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#define TFP410_VID 0x014C
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#define TFP410_DID 0x0410
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#define TFP410_VID_LO 0x00
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#define TFP410_VID_HI 0x01
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#define TFP410_DID_LO 0x02
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#define TFP410_DID_HI 0x03
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#define TFP410_REV 0x04
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#define TFP410_CTL_1 0x08
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#define TFP410_CTL_1_TDIS (1<<6)
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#define TFP410_CTL_1_VEN (1<<5)
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#define TFP410_CTL_1_HEN (1<<4)
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#define TFP410_CTL_1_DSEL (1<<3)
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#define TFP410_CTL_1_BSEL (1<<2)
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#define TFP410_CTL_1_EDGE (1<<1)
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#define TFP410_CTL_1_PD (1<<0)
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#define TFP410_CTL_2 0x09
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#define TFP410_CTL_2_VLOW (1<<7)
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#define TFP410_CTL_2_MSEL_MASK (0x7<<4)
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#define TFP410_CTL_2_MSEL (1<<4)
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#define TFP410_CTL_2_TSEL (1<<3)
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#define TFP410_CTL_2_RSEN (1<<2)
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#define TFP410_CTL_2_HTPLG (1<<1)
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#define TFP410_CTL_2_MDI (1<<0)
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#define TFP410_CTL_3 0x0A
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#define TFP410_CTL_3_DK_MASK (0x7<<5)
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#define TFP410_CTL_3_DK (1<<5)
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#define TFP410_CTL_3_DKEN (1<<4)
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#define TFP410_CTL_3_CTL_MASK (0x7<<1)
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#define TFP410_CTL_3_CTL (1<<1)
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#define TFP410_USERCFG 0x0B
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#define TFP410_DE_DLY 0x32
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#define TFP410_DE_CTL 0x33
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#define TFP410_DE_CTL_DEGEN (1<<6)
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#define TFP410_DE_CTL_VSPOL (1<<5)
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#define TFP410_DE_CTL_HSPOL (1<<4)
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#define TFP410_DE_CTL_DEDLY8 (1<<0)
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#define TFP410_DE_TOP 0x34
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#define TFP410_DE_CNT_LO 0x36
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#define TFP410_DE_CNT_HI 0x37
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#define TFP410_DE_LIN_LO 0x38
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#define TFP410_DE_LIN_HI 0x39
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#define TFP410_H_RES_LO 0x3A
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#define TFP410_H_RES_HI 0x3B
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#define TFP410_V_RES_LO 0x3C
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#define TFP410_V_RES_HI 0x3D
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struct tfp410_priv {
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bool quiet;
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};
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static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
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{
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struct tfp410_priv *tfp = dvo->dev_priv;
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struct i2c_adapter *adapter = dvo->i2c_bus;
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u8 out_buf[2];
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u8 in_buf[2];
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struct i2c_msg msgs[] = {
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{
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.addr = dvo->slave_addr,
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.flags = 0,
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.len = 1,
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.buf = out_buf,
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},
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{
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.addr = dvo->slave_addr,
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.flags = I2C_M_RD,
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.len = 1,
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.buf = in_buf,
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}
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};
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out_buf[0] = addr;
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out_buf[1] = 0;
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if (i2c_transfer(adapter, msgs, 2) == 2) {
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*ch = in_buf[0];
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return true;
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}
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if (!tfp->quiet) {
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DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
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addr, adapter->name, dvo->slave_addr);
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}
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return false;
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}
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static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
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{
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struct tfp410_priv *tfp = dvo->dev_priv;
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struct i2c_adapter *adapter = dvo->i2c_bus;
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u8 out_buf[2];
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struct i2c_msg msg = {
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.addr = dvo->slave_addr,
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.flags = 0,
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.len = 2,
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.buf = out_buf,
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};
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out_buf[0] = addr;
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out_buf[1] = ch;
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if (i2c_transfer(adapter, &msg, 1) == 1)
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return true;
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if (!tfp->quiet) {
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DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
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addr, adapter->name, dvo->slave_addr);
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}
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return false;
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}
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static int tfp410_getid(struct intel_dvo_device *dvo, int addr)
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{
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u8 ch1, ch2;
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if (tfp410_readb(dvo, addr+0, &ch1) &&
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tfp410_readb(dvo, addr+1, &ch2))
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return ((ch2 << 8) & 0xFF00) | (ch1 & 0x00FF);
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return -1;
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}
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/* Ti TFP410 driver for chip on i2c bus */
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static bool tfp410_init(struct intel_dvo_device *dvo,
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struct i2c_adapter *adapter)
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{
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/* this will detect the tfp410 chip on the specified i2c bus */
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struct tfp410_priv *tfp;
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int id;
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tfp = kzalloc(sizeof(struct tfp410_priv), GFP_KERNEL);
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if (tfp == NULL)
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return false;
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dvo->i2c_bus = adapter;
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dvo->dev_priv = tfp;
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tfp->quiet = true;
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if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) {
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DRM_DEBUG_KMS("tfp410 not detected got VID %X: from %s "
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"Slave %d.\n",
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id, adapter->name, dvo->slave_addr);
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goto out;
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}
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if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) {
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DRM_DEBUG_KMS("tfp410 not detected got DID %X: from %s "
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"Slave %d.\n",
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id, adapter->name, dvo->slave_addr);
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goto out;
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}
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tfp->quiet = false;
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return true;
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out:
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kfree(tfp);
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return false;
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}
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static enum drm_connector_status tfp410_detect(struct intel_dvo_device *dvo)
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{
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enum drm_connector_status ret = connector_status_disconnected;
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u8 ctl2;
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if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) {
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if (ctl2 & TFP410_CTL_2_RSEN)
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ret = connector_status_connected;
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else
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ret = connector_status_disconnected;
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}
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return ret;
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}
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static enum drm_mode_status tfp410_mode_valid(struct intel_dvo_device *dvo,
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struct drm_display_mode *mode)
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{
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return MODE_OK;
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}
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static void tfp410_mode_set(struct intel_dvo_device *dvo,
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const struct drm_display_mode *mode,
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const struct drm_display_mode *adjusted_mode)
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{
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/* As long as the basics are set up, since we don't have clock dependencies
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* in the mode setup, we can just leave the registers alone and everything
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* will work fine.
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*/
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/* don't do much */
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return;
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}
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/* set the tfp410 power state */
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static void tfp410_dpms(struct intel_dvo_device *dvo, bool enable)
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{
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u8 ctl1;
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if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1))
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return;
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if (enable)
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ctl1 |= TFP410_CTL_1_PD;
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else
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ctl1 &= ~TFP410_CTL_1_PD;
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tfp410_writeb(dvo, TFP410_CTL_1, ctl1);
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}
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static bool tfp410_get_hw_state(struct intel_dvo_device *dvo)
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{
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u8 ctl1;
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if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1))
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return false;
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if (ctl1 & TFP410_CTL_1_PD)
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return true;
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else
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return false;
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}
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static void tfp410_dump_regs(struct intel_dvo_device *dvo)
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{
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u8 val, val2;
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tfp410_readb(dvo, TFP410_REV, &val);
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DRM_DEBUG_KMS("TFP410_REV: 0x%02X\n", val);
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tfp410_readb(dvo, TFP410_CTL_1, &val);
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DRM_DEBUG_KMS("TFP410_CTL1: 0x%02X\n", val);
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tfp410_readb(dvo, TFP410_CTL_2, &val);
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DRM_DEBUG_KMS("TFP410_CTL2: 0x%02X\n", val);
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tfp410_readb(dvo, TFP410_CTL_3, &val);
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DRM_DEBUG_KMS("TFP410_CTL3: 0x%02X\n", val);
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tfp410_readb(dvo, TFP410_USERCFG, &val);
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DRM_DEBUG_KMS("TFP410_USERCFG: 0x%02X\n", val);
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tfp410_readb(dvo, TFP410_DE_DLY, &val);
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DRM_DEBUG_KMS("TFP410_DE_DLY: 0x%02X\n", val);
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tfp410_readb(dvo, TFP410_DE_CTL, &val);
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DRM_DEBUG_KMS("TFP410_DE_CTL: 0x%02X\n", val);
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tfp410_readb(dvo, TFP410_DE_TOP, &val);
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DRM_DEBUG_KMS("TFP410_DE_TOP: 0x%02X\n", val);
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tfp410_readb(dvo, TFP410_DE_CNT_LO, &val);
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tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2);
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DRM_DEBUG_KMS("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
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tfp410_readb(dvo, TFP410_DE_LIN_LO, &val);
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tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2);
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DRM_DEBUG_KMS("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
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tfp410_readb(dvo, TFP410_H_RES_LO, &val);
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tfp410_readb(dvo, TFP410_H_RES_HI, &val2);
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DRM_DEBUG_KMS("TFP410_H_RES: 0x%02X%02X\n", val2, val);
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tfp410_readb(dvo, TFP410_V_RES_LO, &val);
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tfp410_readb(dvo, TFP410_V_RES_HI, &val2);
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DRM_DEBUG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val);
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}
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static void tfp410_destroy(struct intel_dvo_device *dvo)
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{
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struct tfp410_priv *tfp = dvo->dev_priv;
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if (tfp) {
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kfree(tfp);
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dvo->dev_priv = NULL;
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}
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}
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const struct intel_dvo_dev_ops tfp410_ops = {
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.init = tfp410_init,
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.detect = tfp410_detect,
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.mode_valid = tfp410_mode_valid,
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.mode_set = tfp410_mode_set,
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.dpms = tfp410_dpms,
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.get_hw_state = tfp410_get_hw_state,
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.dump_regs = tfp410_dump_regs,
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.destroy = tfp410_destroy,
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};
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