282 lines
6.7 KiB
C
282 lines
6.7 KiB
C
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/*
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* CoreNet Coherency Fabric error reporting
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*
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* Copyright 2014 Freescale Semiconductor Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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enum ccf_version {
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CCF1,
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CCF2,
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};
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struct ccf_info {
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enum ccf_version version;
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int err_reg_offs;
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bool has_brr;
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};
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static const struct ccf_info ccf1_info = {
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.version = CCF1,
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.err_reg_offs = 0xa00,
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.has_brr = false,
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};
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static const struct ccf_info ccf2_info = {
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.version = CCF2,
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.err_reg_offs = 0xe40,
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.has_brr = true,
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};
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/*
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* This register is present but not documented, with different values for
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* IP_ID, on other chips with fsl,corenet2-cf such as t4240 and b4860.
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*/
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#define CCF_BRR 0xbf8
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#define CCF_BRR_IPID 0xffff0000
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#define CCF_BRR_IPID_T1040 0x09310000
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static const struct of_device_id ccf_matches[] = {
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{
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.compatible = "fsl,corenet1-cf",
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.data = &ccf1_info,
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},
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{
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.compatible = "fsl,corenet2-cf",
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.data = &ccf2_info,
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},
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{}
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};
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MODULE_DEVICE_TABLE(of, ccf_matches);
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struct ccf_err_regs {
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u32 errdet; /* 0x00 Error Detect Register */
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/* 0x04 Error Enable (ccf1)/Disable (ccf2) Register */
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u32 errdis;
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/* 0x08 Error Interrupt Enable Register (ccf2 only) */
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u32 errinten;
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u32 cecar; /* 0x0c Error Capture Attribute Register */
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u32 cecaddrh; /* 0x10 Error Capture Address High */
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u32 cecaddrl; /* 0x14 Error Capture Address Low */
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u32 cecar2; /* 0x18 Error Capture Attribute Register 2 */
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};
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/* LAE/CV also valid for errdis and errinten */
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#define ERRDET_LAE (1 << 0) /* Local Access Error */
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#define ERRDET_CV (1 << 1) /* Coherency Violation */
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#define ERRDET_UTID (1 << 2) /* Unavailable Target ID (t1040) */
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#define ERRDET_MCST (1 << 3) /* Multicast Stash (t1040) */
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#define ERRDET_CTYPE_SHIFT 26 /* Capture Type (ccf2 only) */
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#define ERRDET_CTYPE_MASK (0x1f << ERRDET_CTYPE_SHIFT)
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#define ERRDET_CAP (1 << 31) /* Capture Valid (ccf2 only) */
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#define CECAR_VAL (1 << 0) /* Valid (ccf1 only) */
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#define CECAR_UVT (1 << 15) /* Unavailable target ID (ccf1) */
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#define CECAR_SRCID_SHIFT_CCF1 24
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#define CECAR_SRCID_MASK_CCF1 (0xff << CECAR_SRCID_SHIFT_CCF1)
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#define CECAR_SRCID_SHIFT_CCF2 18
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#define CECAR_SRCID_MASK_CCF2 (0xff << CECAR_SRCID_SHIFT_CCF2)
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#define CECADDRH_ADDRH 0xff
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struct ccf_private {
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const struct ccf_info *info;
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struct device *dev;
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void __iomem *regs;
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struct ccf_err_regs __iomem *err_regs;
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bool t1040;
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};
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static irqreturn_t ccf_irq(int irq, void *dev_id)
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{
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struct ccf_private *ccf = dev_id;
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static DEFINE_RATELIMIT_STATE(ratelimit, DEFAULT_RATELIMIT_INTERVAL,
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DEFAULT_RATELIMIT_BURST);
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u32 errdet, cecar, cecar2;
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u64 addr;
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u32 src_id;
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bool uvt = false;
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bool cap_valid = false;
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errdet = ioread32be(&ccf->err_regs->errdet);
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cecar = ioread32be(&ccf->err_regs->cecar);
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cecar2 = ioread32be(&ccf->err_regs->cecar2);
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addr = ioread32be(&ccf->err_regs->cecaddrl);
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addr |= ((u64)(ioread32be(&ccf->err_regs->cecaddrh) &
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CECADDRH_ADDRH)) << 32;
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if (!__ratelimit(&ratelimit))
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goto out;
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switch (ccf->info->version) {
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case CCF1:
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if (cecar & CECAR_VAL) {
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if (cecar & CECAR_UVT)
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uvt = true;
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src_id = (cecar & CECAR_SRCID_MASK_CCF1) >>
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CECAR_SRCID_SHIFT_CCF1;
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cap_valid = true;
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}
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break;
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case CCF2:
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if (errdet & ERRDET_CAP) {
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src_id = (cecar & CECAR_SRCID_MASK_CCF2) >>
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CECAR_SRCID_SHIFT_CCF2;
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cap_valid = true;
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}
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break;
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}
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dev_crit(ccf->dev, "errdet 0x%08x cecar 0x%08x cecar2 0x%08x\n",
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errdet, cecar, cecar2);
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if (errdet & ERRDET_LAE) {
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if (uvt)
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dev_crit(ccf->dev, "LAW Unavailable Target ID\n");
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else
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dev_crit(ccf->dev, "Local Access Window Error\n");
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}
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if (errdet & ERRDET_CV)
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dev_crit(ccf->dev, "Coherency Violation\n");
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if (errdet & ERRDET_UTID)
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dev_crit(ccf->dev, "Unavailable Target ID\n");
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if (errdet & ERRDET_MCST)
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dev_crit(ccf->dev, "Multicast Stash\n");
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if (cap_valid) {
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dev_crit(ccf->dev, "address 0x%09llx, src id 0x%x\n",
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addr, src_id);
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}
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out:
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iowrite32be(errdet, &ccf->err_regs->errdet);
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return errdet ? IRQ_HANDLED : IRQ_NONE;
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}
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static int ccf_probe(struct platform_device *pdev)
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{
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struct ccf_private *ccf;
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struct resource *r;
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const struct of_device_id *match;
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u32 errinten;
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int ret, irq;
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match = of_match_device(ccf_matches, &pdev->dev);
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if (WARN_ON(!match))
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return -ENODEV;
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ccf = devm_kzalloc(&pdev->dev, sizeof(*ccf), GFP_KERNEL);
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if (!ccf)
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return -ENOMEM;
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r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!r) {
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dev_err(&pdev->dev, "%s: no mem resource\n", __func__);
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return -ENXIO;
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}
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ccf->regs = devm_ioremap_resource(&pdev->dev, r);
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if (IS_ERR(ccf->regs)) {
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dev_err(&pdev->dev, "%s: can't map mem resource\n", __func__);
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return PTR_ERR(ccf->regs);
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}
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ccf->dev = &pdev->dev;
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ccf->info = match->data;
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ccf->err_regs = ccf->regs + ccf->info->err_reg_offs;
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if (ccf->info->has_brr) {
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u32 brr = ioread32be(ccf->regs + CCF_BRR);
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if ((brr & CCF_BRR_IPID) == CCF_BRR_IPID_T1040)
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ccf->t1040 = true;
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}
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dev_set_drvdata(&pdev->dev, ccf);
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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ret = devm_request_irq(&pdev->dev, irq, ccf_irq, 0, pdev->name, ccf);
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if (ret) {
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dev_err(&pdev->dev, "%s: can't request irq\n", __func__);
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return ret;
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}
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errinten = ERRDET_LAE | ERRDET_CV;
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if (ccf->t1040)
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errinten |= ERRDET_UTID | ERRDET_MCST;
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switch (ccf->info->version) {
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case CCF1:
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/* On CCF1 this register enables rather than disables. */
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iowrite32be(errinten, &ccf->err_regs->errdis);
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break;
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case CCF2:
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iowrite32be(0, &ccf->err_regs->errdis);
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iowrite32be(errinten, &ccf->err_regs->errinten);
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break;
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}
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return 0;
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}
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static int ccf_remove(struct platform_device *pdev)
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{
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struct ccf_private *ccf = dev_get_drvdata(&pdev->dev);
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switch (ccf->info->version) {
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case CCF1:
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iowrite32be(0, &ccf->err_regs->errdis);
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break;
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case CCF2:
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/*
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* We clear errdis on ccf1 because that's the only way to
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* disable interrupts, but on ccf2 there's no need to disable
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* detection.
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*/
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iowrite32be(0, &ccf->err_regs->errinten);
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break;
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}
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return 0;
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}
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static struct platform_driver ccf_driver = {
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = ccf_matches,
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},
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.probe = ccf_probe,
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.remove = ccf_remove,
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};
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module_platform_driver(ccf_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Freescale Semiconductor");
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MODULE_DESCRIPTION("Freescale CoreNet Coherency Fabric error reporting");
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