551 lines
15 KiB
C
551 lines
15 KiB
C
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// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
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/* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
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#include <linux/err.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/mutex.h>
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/slab.h>
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#include "cmd.h"
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#include "core.h"
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#include "i2c.h"
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#define MLXSW_I2C_CIR2_BASE 0x72000
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#define MLXSW_I2C_CIR_STATUS_OFF 0x18
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#define MLXSW_I2C_CIR2_OFF_STATUS (MLXSW_I2C_CIR2_BASE + \
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MLXSW_I2C_CIR_STATUS_OFF)
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#define MLXSW_I2C_OPMOD_SHIFT 12
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#define MLXSW_I2C_GO_BIT_SHIFT 23
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#define MLXSW_I2C_CIR_CTRL_STATUS_SHIFT 24
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#define MLXSW_I2C_GO_BIT BIT(MLXSW_I2C_GO_BIT_SHIFT)
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#define MLXSW_I2C_GO_OPMODE BIT(MLXSW_I2C_OPMOD_SHIFT)
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#define MLXSW_I2C_SET_IMM_CMD (MLXSW_I2C_GO_OPMODE | \
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MLXSW_CMD_OPCODE_QUERY_FW)
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#define MLXSW_I2C_PUSH_IMM_CMD (MLXSW_I2C_GO_BIT | \
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MLXSW_I2C_SET_IMM_CMD)
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#define MLXSW_I2C_SET_CMD (MLXSW_CMD_OPCODE_ACCESS_REG)
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#define MLXSW_I2C_PUSH_CMD (MLXSW_I2C_GO_BIT | MLXSW_I2C_SET_CMD)
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#define MLXSW_I2C_TLV_HDR_SIZE 0x10
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#define MLXSW_I2C_ADDR_WIDTH 4
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#define MLXSW_I2C_PUSH_CMD_SIZE (MLXSW_I2C_ADDR_WIDTH + 4)
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#define MLXSW_I2C_READ_SEMA_SIZE 4
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#define MLXSW_I2C_PREP_SIZE (MLXSW_I2C_ADDR_WIDTH + 28)
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#define MLXSW_I2C_MBOX_SIZE 20
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#define MLXSW_I2C_MBOX_OUT_PARAM_OFF 12
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#define MLXSW_I2C_MAX_BUFF_SIZE 32
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#define MLXSW_I2C_MBOX_OFFSET_BITS 20
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#define MLXSW_I2C_MBOX_SIZE_BITS 12
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#define MLXSW_I2C_ADDR_BUF_SIZE 4
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#define MLXSW_I2C_BLK_MAX 32
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#define MLXSW_I2C_RETRY 5
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#define MLXSW_I2C_TIMEOUT_MSECS 5000
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/**
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* struct mlxsw_i2c - device private data:
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* @cmd.mb_size_in: input mailbox size;
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* @cmd.mb_off_in: input mailbox offset in register space;
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* @cmd.mb_size_out: output mailbox size;
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* @cmd.mb_off_out: output mailbox offset in register space;
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* @cmd.lock: command execution lock;
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* @dev: I2C device;
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* @core: switch core pointer;
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* @bus_info: bus info block;
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*/
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struct mlxsw_i2c {
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struct {
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u32 mb_size_in;
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u32 mb_off_in;
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u32 mb_size_out;
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u32 mb_off_out;
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struct mutex lock;
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} cmd;
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struct device *dev;
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struct mlxsw_core *core;
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struct mlxsw_bus_info bus_info;
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};
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#define MLXSW_I2C_READ_MSG(_client, _addr_buf, _buf, _len) { \
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{ .addr = (_client)->addr, \
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.buf = (_addr_buf), \
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.len = MLXSW_I2C_ADDR_BUF_SIZE, \
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.flags = 0 }, \
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{ .addr = (_client)->addr, \
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.buf = (_buf), \
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.len = (_len), \
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.flags = I2C_M_RD } }
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#define MLXSW_I2C_WRITE_MSG(_client, _buf, _len) \
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{ .addr = (_client)->addr, \
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.buf = (u8 *)(_buf), \
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.len = (_len), \
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.flags = 0 }
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/* Routine converts in and out mail boxes offset and size. */
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static inline void
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mlxsw_i2c_convert_mbox(struct mlxsw_i2c *mlxsw_i2c, u8 *buf)
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{
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u32 tmp;
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/* Local in/out mailboxes: 20 bits for offset, 12 for size */
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tmp = be32_to_cpup((__be32 *) buf);
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mlxsw_i2c->cmd.mb_off_in = tmp &
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GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0);
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mlxsw_i2c->cmd.mb_size_in = (tmp & GENMASK(31,
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MLXSW_I2C_MBOX_OFFSET_BITS)) >>
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MLXSW_I2C_MBOX_OFFSET_BITS;
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tmp = be32_to_cpup((__be32 *) (buf + MLXSW_I2C_ADDR_WIDTH));
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mlxsw_i2c->cmd.mb_off_out = tmp &
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GENMASK(MLXSW_I2C_MBOX_OFFSET_BITS - 1, 0);
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mlxsw_i2c->cmd.mb_size_out = (tmp & GENMASK(31,
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MLXSW_I2C_MBOX_OFFSET_BITS)) >>
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MLXSW_I2C_MBOX_OFFSET_BITS;
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}
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/* Routine obtains register size from mail box buffer. */
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static inline int mlxsw_i2c_get_reg_size(u8 *in_mbox)
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{
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u16 tmp = be16_to_cpup((__be16 *) (in_mbox + MLXSW_I2C_TLV_HDR_SIZE));
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return (tmp & 0x7ff) * 4 + MLXSW_I2C_TLV_HDR_SIZE;
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}
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/* Routine sets I2C device internal offset in the transaction buffer. */
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static inline void mlxsw_i2c_set_slave_addr(u8 *buf, u32 off)
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{
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__be32 *val = (__be32 *) buf;
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*val = htonl(off);
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}
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/* Routine waits until go bit is cleared. */
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static int mlxsw_i2c_wait_go_bit(struct i2c_client *client,
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struct mlxsw_i2c *mlxsw_i2c, u8 *p_status)
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{
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u8 addr_buf[MLXSW_I2C_ADDR_BUF_SIZE];
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u8 buf[MLXSW_I2C_READ_SEMA_SIZE];
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int len = MLXSW_I2C_READ_SEMA_SIZE;
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struct i2c_msg read_sema[] =
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MLXSW_I2C_READ_MSG(client, addr_buf, buf, len);
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bool wait_done = false;
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unsigned long end;
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int i = 0, err;
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mlxsw_i2c_set_slave_addr(addr_buf, MLXSW_I2C_CIR2_OFF_STATUS);
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end = jiffies + msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS);
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do {
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u32 ctrl;
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err = i2c_transfer(client->adapter, read_sema,
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ARRAY_SIZE(read_sema));
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ctrl = be32_to_cpu(*(__be32 *) buf);
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if (err == ARRAY_SIZE(read_sema)) {
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if (!(ctrl & MLXSW_I2C_GO_BIT)) {
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wait_done = true;
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*p_status = ctrl >>
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MLXSW_I2C_CIR_CTRL_STATUS_SHIFT;
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break;
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}
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}
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cond_resched();
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} while ((time_before(jiffies, end)) || (i++ < MLXSW_I2C_RETRY));
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if (wait_done) {
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if (*p_status)
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err = -EIO;
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} else {
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return -ETIMEDOUT;
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}
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return err > 0 ? 0 : err;
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}
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/* Routine posts a command to ASIC though mail box. */
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static int mlxsw_i2c_write_cmd(struct i2c_client *client,
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struct mlxsw_i2c *mlxsw_i2c,
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int immediate)
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{
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__be32 push_cmd_buf[MLXSW_I2C_PUSH_CMD_SIZE / 4] = {
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0, cpu_to_be32(MLXSW_I2C_PUSH_IMM_CMD)
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};
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__be32 prep_cmd_buf[MLXSW_I2C_PREP_SIZE / 4] = {
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0, 0, 0, 0, 0, 0,
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cpu_to_be32(client->adapter->nr & 0xffff),
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cpu_to_be32(MLXSW_I2C_SET_IMM_CMD)
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};
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struct i2c_msg push_cmd =
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MLXSW_I2C_WRITE_MSG(client, push_cmd_buf,
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MLXSW_I2C_PUSH_CMD_SIZE);
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struct i2c_msg prep_cmd =
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MLXSW_I2C_WRITE_MSG(client, prep_cmd_buf, MLXSW_I2C_PREP_SIZE);
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int err;
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if (!immediate) {
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push_cmd_buf[1] = cpu_to_be32(MLXSW_I2C_PUSH_CMD);
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prep_cmd_buf[7] = cpu_to_be32(MLXSW_I2C_SET_CMD);
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}
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mlxsw_i2c_set_slave_addr((u8 *)prep_cmd_buf,
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MLXSW_I2C_CIR2_BASE);
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mlxsw_i2c_set_slave_addr((u8 *)push_cmd_buf,
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MLXSW_I2C_CIR2_OFF_STATUS);
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/* Prepare Command Interface Register for transaction */
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err = i2c_transfer(client->adapter, &prep_cmd, 1);
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if (err < 0)
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return err;
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else if (err != 1)
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return -EIO;
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/* Write out Command Interface Register GO bit to push transaction */
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err = i2c_transfer(client->adapter, &push_cmd, 1);
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if (err < 0)
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return err;
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else if (err != 1)
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return -EIO;
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return 0;
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}
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/* Routine obtains mail box offsets from ASIC register space. */
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static int mlxsw_i2c_get_mbox(struct i2c_client *client,
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struct mlxsw_i2c *mlxsw_i2c)
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{
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u8 addr_buf[MLXSW_I2C_ADDR_BUF_SIZE];
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u8 buf[MLXSW_I2C_MBOX_SIZE];
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struct i2c_msg mbox_cmd[] =
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MLXSW_I2C_READ_MSG(client, addr_buf, buf, MLXSW_I2C_MBOX_SIZE);
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int err;
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/* Read mail boxes offsets. */
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mlxsw_i2c_set_slave_addr(addr_buf, MLXSW_I2C_CIR2_BASE);
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err = i2c_transfer(client->adapter, mbox_cmd, 2);
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if (err != 2) {
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dev_err(&client->dev, "Could not obtain mail boxes\n");
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if (!err)
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return -EIO;
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else
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return err;
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}
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/* Convert mail boxes. */
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mlxsw_i2c_convert_mbox(mlxsw_i2c, &buf[MLXSW_I2C_MBOX_OUT_PARAM_OFF]);
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return err;
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}
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/* Routine sends I2C write transaction to ASIC device. */
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static int
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mlxsw_i2c_write(struct device *dev, size_t in_mbox_size, u8 *in_mbox, int num,
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u8 *p_status)
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{
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struct i2c_client *client = to_i2c_client(dev);
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struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
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unsigned long timeout = msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS);
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u8 tran_buf[MLXSW_I2C_MAX_BUFF_SIZE + MLXSW_I2C_ADDR_BUF_SIZE];
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int off = mlxsw_i2c->cmd.mb_off_in, chunk_size, i, j;
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unsigned long end;
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struct i2c_msg write_tran =
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MLXSW_I2C_WRITE_MSG(client, tran_buf, MLXSW_I2C_PUSH_CMD_SIZE);
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int err;
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for (i = 0; i < num; i++) {
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chunk_size = (in_mbox_size > MLXSW_I2C_BLK_MAX) ?
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MLXSW_I2C_BLK_MAX : in_mbox_size;
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write_tran.len = MLXSW_I2C_ADDR_WIDTH + chunk_size;
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mlxsw_i2c_set_slave_addr(tran_buf, off);
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memcpy(&tran_buf[MLXSW_I2C_ADDR_BUF_SIZE], in_mbox +
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MLXSW_I2C_BLK_MAX * i, chunk_size);
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j = 0;
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end = jiffies + timeout;
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do {
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err = i2c_transfer(client->adapter, &write_tran, 1);
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if (err == 1)
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break;
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cond_resched();
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} while ((time_before(jiffies, end)) ||
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(j++ < MLXSW_I2C_RETRY));
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if (err != 1) {
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if (!err)
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err = -EIO;
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return err;
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}
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off += chunk_size;
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in_mbox_size -= chunk_size;
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}
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/* Prepare and write out Command Interface Register for transaction. */
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err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 0);
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if (err) {
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dev_err(&client->dev, "Could not start transaction");
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return -EIO;
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}
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/* Wait until go bit is cleared. */
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err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, p_status);
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if (err) {
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dev_err(&client->dev, "HW semaphore is not released");
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return err;
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}
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/* Validate transaction completion status. */
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if (*p_status) {
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dev_err(&client->dev, "Bad transaction completion status %x\n",
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*p_status);
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return -EIO;
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}
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return 0;
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}
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/* Routine executes I2C command. */
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static int
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mlxsw_i2c_cmd(struct device *dev, size_t in_mbox_size, u8 *in_mbox,
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size_t out_mbox_size, u8 *out_mbox, u8 *status)
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{
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struct i2c_client *client = to_i2c_client(dev);
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struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
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unsigned long timeout = msecs_to_jiffies(MLXSW_I2C_TIMEOUT_MSECS);
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u8 tran_buf[MLXSW_I2C_ADDR_BUF_SIZE];
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int num, chunk_size, reg_size, i, j;
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int off = mlxsw_i2c->cmd.mb_off_out;
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unsigned long end;
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struct i2c_msg read_tran[] =
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|
|
MLXSW_I2C_READ_MSG(client, tran_buf, NULL, 0);
|
||
|
|
int err;
|
||
|
|
|
||
|
|
WARN_ON(in_mbox_size % sizeof(u32) || out_mbox_size % sizeof(u32));
|
||
|
|
|
||
|
|
reg_size = mlxsw_i2c_get_reg_size(in_mbox);
|
||
|
|
num = reg_size / MLXSW_I2C_BLK_MAX;
|
||
|
|
if (reg_size % MLXSW_I2C_BLK_MAX)
|
||
|
|
num++;
|
||
|
|
|
||
|
|
if (mutex_lock_interruptible(&mlxsw_i2c->cmd.lock) < 0) {
|
||
|
|
dev_err(&client->dev, "Could not acquire lock");
|
||
|
|
return -EINVAL;
|
||
|
|
}
|
||
|
|
|
||
|
|
err = mlxsw_i2c_write(dev, reg_size, in_mbox, num, status);
|
||
|
|
if (err)
|
||
|
|
goto cmd_fail;
|
||
|
|
|
||
|
|
/* No out mailbox is case of write transaction. */
|
||
|
|
if (!out_mbox) {
|
||
|
|
mutex_unlock(&mlxsw_i2c->cmd.lock);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Send read transaction to get output mailbox content. */
|
||
|
|
read_tran[1].buf = out_mbox;
|
||
|
|
for (i = 0; i < num; i++) {
|
||
|
|
chunk_size = (reg_size > MLXSW_I2C_BLK_MAX) ?
|
||
|
|
MLXSW_I2C_BLK_MAX : reg_size;
|
||
|
|
read_tran[1].len = chunk_size;
|
||
|
|
mlxsw_i2c_set_slave_addr(tran_buf, off);
|
||
|
|
|
||
|
|
j = 0;
|
||
|
|
end = jiffies + timeout;
|
||
|
|
do {
|
||
|
|
err = i2c_transfer(client->adapter, read_tran,
|
||
|
|
ARRAY_SIZE(read_tran));
|
||
|
|
if (err == ARRAY_SIZE(read_tran))
|
||
|
|
break;
|
||
|
|
|
||
|
|
cond_resched();
|
||
|
|
} while ((time_before(jiffies, end)) ||
|
||
|
|
(j++ < MLXSW_I2C_RETRY));
|
||
|
|
|
||
|
|
if (err != ARRAY_SIZE(read_tran)) {
|
||
|
|
if (!err)
|
||
|
|
err = -EIO;
|
||
|
|
|
||
|
|
goto cmd_fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
off += chunk_size;
|
||
|
|
reg_size -= chunk_size;
|
||
|
|
read_tran[1].buf += chunk_size;
|
||
|
|
}
|
||
|
|
|
||
|
|
mutex_unlock(&mlxsw_i2c->cmd.lock);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
cmd_fail:
|
||
|
|
mutex_unlock(&mlxsw_i2c->cmd.lock);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mlxsw_i2c_cmd_exec(void *bus_priv, u16 opcode, u8 opcode_mod,
|
||
|
|
u32 in_mod, bool out_mbox_direct,
|
||
|
|
char *in_mbox, size_t in_mbox_size,
|
||
|
|
char *out_mbox, size_t out_mbox_size,
|
||
|
|
u8 *status)
|
||
|
|
{
|
||
|
|
struct mlxsw_i2c *mlxsw_i2c = bus_priv;
|
||
|
|
|
||
|
|
return mlxsw_i2c_cmd(mlxsw_i2c->dev, in_mbox_size, in_mbox,
|
||
|
|
out_mbox_size, out_mbox, status);
|
||
|
|
}
|
||
|
|
|
||
|
|
static bool mlxsw_i2c_skb_transmit_busy(void *bus_priv,
|
||
|
|
const struct mlxsw_tx_info *tx_info)
|
||
|
|
{
|
||
|
|
return false;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mlxsw_i2c_skb_transmit(void *bus_priv, struct sk_buff *skb,
|
||
|
|
const struct mlxsw_tx_info *tx_info)
|
||
|
|
{
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int
|
||
|
|
mlxsw_i2c_init(void *bus_priv, struct mlxsw_core *mlxsw_core,
|
||
|
|
const struct mlxsw_config_profile *profile,
|
||
|
|
struct mlxsw_res *resources)
|
||
|
|
{
|
||
|
|
struct mlxsw_i2c *mlxsw_i2c = bus_priv;
|
||
|
|
|
||
|
|
mlxsw_i2c->core = mlxsw_core;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void mlxsw_i2c_fini(void *bus_priv)
|
||
|
|
{
|
||
|
|
struct mlxsw_i2c *mlxsw_i2c = bus_priv;
|
||
|
|
|
||
|
|
mlxsw_i2c->core = NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct mlxsw_bus mlxsw_i2c_bus = {
|
||
|
|
.kind = "i2c",
|
||
|
|
.init = mlxsw_i2c_init,
|
||
|
|
.fini = mlxsw_i2c_fini,
|
||
|
|
.skb_transmit_busy = mlxsw_i2c_skb_transmit_busy,
|
||
|
|
.skb_transmit = mlxsw_i2c_skb_transmit,
|
||
|
|
.cmd_exec = mlxsw_i2c_cmd_exec,
|
||
|
|
};
|
||
|
|
|
||
|
|
static int mlxsw_i2c_probe(struct i2c_client *client,
|
||
|
|
const struct i2c_device_id *id)
|
||
|
|
{
|
||
|
|
struct mlxsw_i2c *mlxsw_i2c;
|
||
|
|
u8 status;
|
||
|
|
int err;
|
||
|
|
|
||
|
|
mlxsw_i2c = devm_kzalloc(&client->dev, sizeof(*mlxsw_i2c), GFP_KERNEL);
|
||
|
|
if (!mlxsw_i2c)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
i2c_set_clientdata(client, mlxsw_i2c);
|
||
|
|
mutex_init(&mlxsw_i2c->cmd.lock);
|
||
|
|
|
||
|
|
/* In order to use mailboxes through the i2c, special area is reserved
|
||
|
|
* on the i2c address space that can be used for input and output
|
||
|
|
* mailboxes. Such mailboxes are called local mailboxes. When using a
|
||
|
|
* local mailbox, software should specify 0 as the Input/Output
|
||
|
|
* parameters. The location of the Local Mailbox addresses on the i2c
|
||
|
|
* space can be retrieved through the QUERY_FW command.
|
||
|
|
* For this purpose QUERY_FW is to be issued with opcode modifier equal
|
||
|
|
* 0x01. For such command the output parameter is an immediate value.
|
||
|
|
* Here QUERY_FW command is invoked for ASIC probing and for getting
|
||
|
|
* local mailboxes addresses from immedate output parameters.
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* Prepare and write out Command Interface Register for transaction */
|
||
|
|
err = mlxsw_i2c_write_cmd(client, mlxsw_i2c, 1);
|
||
|
|
if (err) {
|
||
|
|
dev_err(&client->dev, "Could not start transaction");
|
||
|
|
goto errout;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Wait until go bit is cleared. */
|
||
|
|
err = mlxsw_i2c_wait_go_bit(client, mlxsw_i2c, &status);
|
||
|
|
if (err) {
|
||
|
|
dev_err(&client->dev, "HW semaphore is not released");
|
||
|
|
goto errout;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Validate transaction completion status. */
|
||
|
|
if (status) {
|
||
|
|
dev_err(&client->dev, "Bad transaction completion status %x\n",
|
||
|
|
status);
|
||
|
|
err = -EIO;
|
||
|
|
goto errout;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Get mailbox offsets. */
|
||
|
|
err = mlxsw_i2c_get_mbox(client, mlxsw_i2c);
|
||
|
|
if (err < 0) {
|
||
|
|
dev_err(&client->dev, "Fail to get mailboxes\n");
|
||
|
|
goto errout;
|
||
|
|
}
|
||
|
|
|
||
|
|
dev_info(&client->dev, "%s mb size=%x off=0x%08x out mb size=%x off=0x%08x\n",
|
||
|
|
id->name, mlxsw_i2c->cmd.mb_size_in,
|
||
|
|
mlxsw_i2c->cmd.mb_off_in, mlxsw_i2c->cmd.mb_size_out,
|
||
|
|
mlxsw_i2c->cmd.mb_off_out);
|
||
|
|
|
||
|
|
/* Register device bus. */
|
||
|
|
mlxsw_i2c->bus_info.device_kind = id->name;
|
||
|
|
mlxsw_i2c->bus_info.device_name = client->name;
|
||
|
|
mlxsw_i2c->bus_info.dev = &client->dev;
|
||
|
|
mlxsw_i2c->dev = &client->dev;
|
||
|
|
|
||
|
|
err = mlxsw_core_bus_device_register(&mlxsw_i2c->bus_info,
|
||
|
|
&mlxsw_i2c_bus, mlxsw_i2c, false,
|
||
|
|
NULL);
|
||
|
|
if (err) {
|
||
|
|
dev_err(&client->dev, "Fail to register core bus\n");
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
errout:
|
||
|
|
i2c_set_clientdata(client, NULL);
|
||
|
|
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
static int mlxsw_i2c_remove(struct i2c_client *client)
|
||
|
|
{
|
||
|
|
struct mlxsw_i2c *mlxsw_i2c = i2c_get_clientdata(client);
|
||
|
|
|
||
|
|
mlxsw_core_bus_device_unregister(mlxsw_i2c->core, false);
|
||
|
|
mutex_destroy(&mlxsw_i2c->cmd.lock);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int mlxsw_i2c_driver_register(struct i2c_driver *i2c_driver)
|
||
|
|
{
|
||
|
|
i2c_driver->probe = mlxsw_i2c_probe;
|
||
|
|
i2c_driver->remove = mlxsw_i2c_remove;
|
||
|
|
return i2c_add_driver(i2c_driver);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(mlxsw_i2c_driver_register);
|
||
|
|
|
||
|
|
void mlxsw_i2c_driver_unregister(struct i2c_driver *i2c_driver)
|
||
|
|
{
|
||
|
|
i2c_del_driver(i2c_driver);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(mlxsw_i2c_driver_unregister);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Vadim Pasternak <vadimp@mellanox.com>");
|
||
|
|
MODULE_DESCRIPTION("Mellanox switch I2C interface driver");
|
||
|
|
MODULE_LICENSE("Dual BSD/GPL");
|