/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2019 MediaTek Inc.
 * Author: Houlong Wei <houlong.wei@mediatek.com>
 */

#ifndef _DT_BINDINGS_GCE_MT2712_H
#define _DT_BINDINGS_GCE_MT2712_H

/* GCE HW thread priority */
#define CMDQ_THR_PRIO_LOWEST	0
#define CMDQ_THR_PRIO_HIGHEST	1

/* GCE SUBSYS */
#define SUBSYS_1400XXXX		1
#define SUBSYS_1401XXXX		2
#define SUBSYS_1402XXXX		3
#define SUBSYS_1403XXXX		23

/* GCE HW EVENT */
#define CMDQ_EVENT_MDP_RDMA0_SOF	0
#define CMDQ_EVENT_MDP_RDMA1_SOF	1
#define CMDQ_EVENT_MDP_TDSHP0_SOF	5
#define CMDQ_EVENT_MDP_TDSHP1_SOF	6
#define CMDQ_EVENT_MDP_WDMA_SOF		7
#define CMDQ_EVENT_MDP_WROT0_SOF	8
#define CMDQ_EVENT_MDP_WROT1_SOF	9
#define CMDQ_EVENT_MDP_CROP_SOF		10
#define CMDQ_EVENT_DISP_OVL0_SOF	11
#define CMDQ_EVENT_DISP_OVL1_SOF	12
#define CMDQ_EVENT_DISP_RDMA0_SOF	13
#define CMDQ_EVENT_DISP_RDMA1_SOF	14
#define CMDQ_EVENT_DISP_RDMA2_SOF	15
#define CMDQ_EVENT_DISP_WDMA0_SOF	16
#define CMDQ_EVENT_DISP_WDMA1_SOF	17
#define CMDQ_EVENT_DISP_COLOR0_SOF	18
#define CMDQ_EVENT_DISP_COLOR1_SOF	19
#define CMDQ_EVENT_DISP_AAL0_SOF	20
#define CMDQ_EVENT_DISP_GAMMA_SOF	21
#define CMDQ_EVENT_DISP_UFOE_SOF	22
#define CMDQ_EVENT_DISP_PWM0_SOF	23
#define CMDQ_EVENT_DISP_PWM1_SOF	24
#define CMDQ_EVENT_DISP_OD0_SOF		25
#define CMDQ_EVENT_MDP_RDMA2_SOF	26
#define CMDQ_EVENT_MDP_RDMA3_SOF	27
#define CMDQ_EVENT_MDP_TDSHP2_SOF	28
#define CMDQ_EVENT_MDP_WROT2_SOF	29
#define CMDQ_EVENT_DISP_OVL2_SOF	30
#define CMDQ_EVENT_DISP_WDMA2_SOF	31
#define CMDQ_EVENT_DISP_COLOR2_SOF	32
#define CMDQ_EVENT_DISP_AAL1_SOF	33
#define CMDQ_EVENT_DISP_OD1_SOF		34
#define CMDQ_EVENT_MDP_RDMA0_EOF	37
#define CMDQ_EVENT_MDP_RDMA1_EOF	38
#define CMDQ_EVENT_MDP_RSZ0_EOF		39
#define CMDQ_EVENT_MDP_RSZ1_EOF		40
#define CMDQ_EVENT_MDP_RSZ2_EOF		41
#define CMDQ_EVENT_MDP_TDSHP0_EOF	42
#define CMDQ_EVENT_MDP_TDSHP1_EOF	43
#define CMDQ_EVENT_MDP_WDMA_EOF		44
#define CMDQ_EVENT_MDP_WROT0_W_EOF	45
#define CMDQ_EVENT_MDP_WROT0_R_EOF	46
#define CMDQ_EVENT_MDP_WROT1_W_EOF	47
#define CMDQ_EVENT_MDP_WROT1_R_EOF	48
#define CMDQ_EVENT_MDP_CROP_EOF		49
#define CMDQ_EVENT_DISP_OVL0_EOF	50
#define CMDQ_EVENT_DISP_OVL1_EOF	51
#define CMDQ_EVENT_DISP_RDMA0_EOF	52
#define CMDQ_EVENT_DISP_RDMA1_EOF	53
#define CMDQ_EVENT_DISP_RDMA2_EOF	54
#define CMDQ_EVENT_DISP_WDMA0_EOF	55
#define CMDQ_EVENT_DISP_WDMA1_EOF	56
#define CMDQ_EVENT_DISP_COLOR0_EOF	57
#define CMDQ_EVENT_DISP_COLOR1_EOF	58
#define CMDQ_EVENT_DISP_AAL0_EOF	59
#define CMDQ_EVENT_DISP_GAMMA_EOF	60
#define CMDQ_EVENT_DISP_UFOE_EOF	61
#define CMDQ_EVENT_DISP_DPI0_EOF	62
#define CMDQ_EVENT_DISP_DPI1_EOF	63
#define CMDQ_EVENT_MDP_RDMA2_EOF	64
#define CMDQ_EVENT_MDP_RDMA3_EOF	65
#define CMDQ_EVENT_MDP_WROT2_W_EOF	66
#define CMDQ_EVENT_MDP_WROT2_R_EOF	67
#define CMDQ_EVENT_MDP_TDSHP2_EOF	68
#define CMDQ_EVENT_DISP_OVL2_EOF	69
#define CMDQ_EVENT_DISP_WDMA2_EOF	70
#define CMDQ_EVENT_DISP_COLOR2_EOF	71
#define CMDQ_EVENT_DISP_AAL1_EOF	72
#define CMDQ_EVENT_DISP_OD0_EOF		73
#define CMDQ_EVENT_DISP_OD1_EOF		74
#define CMDQ_EVENT_DISP_DSI0_EOF	75
#define CMDQ_EVENT_DISP_DSI1_EOF	76
#define CMDQ_EVENT_DISP_DSI2_EOF	77
#define CMDQ_EVENT_DISP_DSI3_EOF	78
#define CMDQ_EVENT_MUTEX0_STREAM_EOF	79
#define CMDQ_EVENT_MUTEX1_STREAM_EOF	80
#define CMDQ_EVENT_MUTEX2_STREAM_EOF	81
#define CMDQ_EVENT_MUTEX3_STREAM_EOF	82
#define CMDQ_EVENT_MUTEX4_STREAM_EOF	83
#define CMDQ_EVENT_DISP_RDMA0_UNDERRUN	89
#define CMDQ_EVENT_DISP_RDMA1_UNDERRUN	90
#define CMDQ_EVENT_DISP_RDMA2_UNDERRUN	91

#endif