/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2019 MediaTek Inc. */ #ifndef _DTS_IOMMU_PORT_MT6885_H_ #define _DTS_IOMMU_PORT_MT6885_H_ #define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) /* Local arbiter ID */ #define MTK_IOMMU_TO_LARB(id) (((id) >> 5) & 0x1f) /* PortID within the local arbiter */ #define MTK_IOMMU_TO_PORT(id) ((id) & 0x1f) #define APU_PSEUDO_LARBID (21) #define CCU_PSEUDO_LARBID_DISP (22) #define CCU_PSEUDO_LARBID_MDP (23) #define CCU_PSEUDO_LARBID_NODE CCU_PSEUDO_LARBID_MDP /* 6, 10, 12, 15 is not applied for IOMMU*/ #define MTK_IOMMU_LARB_NR (24) /* larb0 -- 15*/ #define M4U_PORT_L0_DISP_POSTMASK0 MTK_M4U_ID(0, 0) #define M4U_PORT_L0_MDP_RDMA4 MTK_M4U_ID(0, 1) #define M4U_PORT_L0_OVL_RDMA0_HDR MTK_M4U_ID(0, 2) #define M4U_PORT_L0_OVL_2L_RDMA1_HDR MTK_M4U_ID(0, 3) #define M4U_PORT_L0_OVL_2L_RDMA3_HDR MTK_M4U_ID(0, 4) #define M4U_PORT_L0_OVL_RDMA0 MTK_M4U_ID(0, 5) #define M4U_PORT_L0_OVL_2L_RDMA1 MTK_M4U_ID(0, 6) #define M4U_PORT_L0_OVL_2L_RDMA3 MTK_M4U_ID(0, 7) #define M4U_PORT_L0_OVL_RDMA1_SYSRAM MTK_M4U_ID(0, 8) #define M4U_PORT_L0_OVL_2L_RDMA0_SYSRAM MTK_M4U_ID(0, 9) #define M4U_PORT_L0_OVL_2L_RDMA2_SYSRAM MTK_M4U_ID(0, 10) #define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 11) #define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 12) #define M4U_PORT_L0_DISP_UFBC_WDMA0 MTK_M4U_ID(0, 13) #define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 14) /* larb1 -- 15*/ #define M4U_PORT_L1_DISP_POSTMASK1 MTK_M4U_ID(1, 0) #define M4U_PORT_L1_MDP_RDMA5 MTK_M4U_ID(1, 1) #define M4U_PORT_L1_OVL_RDMA1_HDR MTK_M4U_ID(1, 2) #define M4U_PORT_L1_OVL_2L_RDMA0_HDR MTK_M4U_ID(1, 3) #define M4U_PORT_L1_OVL_2L_RDMA2_HDR MTK_M4U_ID(1, 4) #define M4U_PORT_L1_OVL_RDMA1 MTK_M4U_ID(1, 5) #define M4U_PORT_L1_OVL_2L_RDMA0 MTK_M4U_ID(1, 6) #define M4U_PORT_L1_OVL_2L_RDMA2 MTK_M4U_ID(1, 7) #define M4U_PORT_L1_OVL_RDMA0_SYSRAM MTK_M4U_ID(1, 8) #define M4U_PORT_L1_OVL_2L_RDMA1_SYSRAM MTK_M4U_ID(1, 9) #define M4U_PORT_L1_OVL_2L_RDMA3_SYSRAM MTK_M4U_ID(1, 10) #define M4U_PORT_L1_DISP_WDMA1 MTK_M4U_ID(1, 11) #define M4U_PORT_L1_DISP_RDMA1 MTK_M4U_ID(1, 12) #define M4U_PORT_L1_DISP_UFBC_WDMA1 MTK_M4U_ID(1, 13) #define M4U_PORT_L1_DISP_FAKE1 MTK_M4U_ID(1, 14) /* larb2 -- 6*/ #define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0) #define M4U_PORT_L2_MDP_RDMA2 MTK_M4U_ID(2, 1) #define M4U_PORT_L2_MDP_WROT0 MTK_M4U_ID(2, 2) #define M4U_PORT_L2_MDP_WROT2 MTK_M4U_ID(2, 3) #define M4U_PORT_L2_MDP_FILMGRAIN0 MTK_M4U_ID(2, 4) #define M4U_PORT_L2_MDP_FAKE0 MTK_M4U_ID(2, 5) /* larb3 -- 6*/ #define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(3, 0) #define M4U_PORT_L3_MDP_RDMA3 MTK_M4U_ID(3, 1) #define M4U_PORT_L3_MDP_WROT1 MTK_M4U_ID(3, 2) #define M4U_PORT_L3_MDP_WROT3 MTK_M4U_ID(3, 3) #define M4U_PORT_L3_MDP_FILMGRAIN1 MTK_M4U_ID(3, 4) #define M4U_PORT_L3_MDP_FAKE1 MTK_M4U_ID(3, 5) /* larb4 -- 11*/ #define M4U_PORT_L4_VDEC_MC_EXT_MDP MTK_M4U_ID(4, 0) #define M4U_PORT_L4_VDEC_UFO_EXT_MDP MTK_M4U_ID(4, 1) #define M4U_PORT_L4_VDEC_PP_EXT_MDP MTK_M4U_ID(4, 2) #define M4U_PORT_L4_VDEC_PRED_RD_EXT_MDP MTK_M4U_ID(4, 3) #define M4U_PORT_L4_VDEC_PRED_WR_EXT_MDP MTK_M4U_ID(4, 4) #define M4U_PORT_L4_VDEC_PPWRAP_EXT_MDP MTK_M4U_ID(4, 5) #define M4U_PORT_L4_VDEC_TILE_EXT_MDP MTK_M4U_ID(4, 6) #define M4U_PORT_L4_VDEC_VLD_EXT_MDP MTK_M4U_ID(4, 7) #define M4U_PORT_L4_VDEC_VLD2_EXT_MDP MTK_M4U_ID(4, 8) #define M4U_PORT_L4_VDEC_AVC_MV_EXT_MDP MTK_M4U_ID(4, 9) #define M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT_MDP MTK_M4U_ID(4, 10) /* larb5 -- 8*/ #define M4U_PORT_L5_VDEC_LAT0_VLD_EXT_DISP MTK_M4U_ID(5, 0) #define M4U_PORT_L5_VDEC_LAT0_VLD2_EXT_DISP MTK_M4U_ID(5, 1) #define M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT_DISP MTK_M4U_ID(5, 2) #define M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT_DISP MTK_M4U_ID(5, 3) #define M4U_PORT_L5_VDEC_LAT0_TILE_EXT_DISP MTK_M4U_ID(5, 4) #define M4U_PORT_L5_VDEC_LAT0_WDMA_EXT_DISP MTK_M4U_ID(5, 5) #define M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT_DISP MTK_M4U_ID(5, 6) #define M4U_PORT_L5_VDEC_UFO_ENC_EXT_DISP MTK_M4U_ID(5, 7) /* larb6 -- not existed*/ /* larb7 --/ 27*/ #define M4U_PORT_L7_VENC_RCPU_DISP MTK_M4U_ID(7, 0) #define M4U_PORT_L7_VENC_REC_DISP MTK_M4U_ID(7, 1) #define M4U_PORT_L7_VENC_BSDMA_DISP MTK_M4U_ID(7, 2) #define M4U_PORT_L7_VENC_SV_COMV_DISP MTK_M4U_ID(7, 3) #define M4U_PORT_L7_VENC_RD_COMV_DISP MTK_M4U_ID(7, 4) #define M4U_PORT_L7_VENC_NBM_RDMA_DISP MTK_M4U_ID(7, 5) #define M4U_PORT_L7_VENC_NBM_RDMA_LITE_DISP MTK_M4U_ID(7, 6) #define M4U_PORT_L7_JPGENC_Y_RDMA_DISP MTK_M4U_ID(7, 7) #define M4U_PORT_L7_JPGENC_C_RDMA_DISP MTK_M4U_ID(7, 8) #define M4U_PORT_L7_JPGENC_Q_TABLE_DISP MTK_M4U_ID(7, 9) #define M4U_PORT_L7_JPGENC_BSDMA_DISP MTK_M4U_ID(7, 10) #define M4U_PORT_L7_JPGENC_WDMA0_DISP MTK_M4U_ID(7, 11) #define M4U_PORT_L7_JPGENC_BSDMA0_DISP MTK_M4U_ID(7, 12) #define M4U_PORT_L7_VENC_NBM_WDMA_DISP MTK_M4U_ID(7, 13) #define M4U_PORT_L7_VENC_NBM_WDMA_LITE_DISP MTK_M4U_ID(7, 14) #define M4U_PORT_L7_VENC_CUR_LUMA_DISP MTK_M4U_ID(7, 15) #define M4U_PORT_L7_VENC_CUR_CHROMA_DISP MTK_M4U_ID(7, 16) #define M4U_PORT_L7_VENC_REF_LUMA_DISP MTK_M4U_ID(7, 17) #define M4U_PORT_L7_VENC_REF_CHROMA_DISP MTK_M4U_ID(7, 18) #define M4U_PORT_L7_VENC_SUB_R_LUMA_DISP MTK_M4U_ID(7, 19) #define M4U_PORT_L7_VENC_SUB_W_LUMA_DISP MTK_M4U_ID(7, 20) #define M4U_PORT_L7_VENC_FCS_NBM_RDMA_DISP MTK_M4U_ID(7, 21) #define M4U_PORT_L7_VENC_FCS_NBM_WDMA_DISP MTK_M4U_ID(7, 22) #define M4U_PORT_L7_JPGENC_WDMA1_DISP MTK_M4U_ID(7, 23) #define M4U_PORT_L7_JPGENC_BSDMA1_DISP MTK_M4U_ID(7, 24) #define M4U_PORT_L7_JPGENC_HUFF_OFFSET1_DISP MTK_M4U_ID(7, 25) #define M4U_PORT_L7_JPGENC_HUFF_OFFSET0_DISP MTK_M4U_ID(7, 26) /* larb8 -- 27*/ #define M4U_PORT_L8_VENC_RCPU_MDP MTK_M4U_ID(8, 0) #define M4U_PORT_L8_VENC_REC_MDP MTK_M4U_ID(8, 1) #define M4U_PORT_L8_VENC_BSDMA_MDP MTK_M4U_ID(8, 2) #define M4U_PORT_L8_VENC_SV_COMV_MDP MTK_M4U_ID(8, 3) #define M4U_PORT_L8_VENC_RD_COMV_MDP MTK_M4U_ID(8, 4) #define M4U_PORT_L8_VENC_NBM_RDMA_MDP MTK_M4U_ID(8, 5) #define M4U_PORT_L8_VENC_NBM_RDMA_LITE_MDP MTK_M4U_ID(8, 6) #define M4U_PORT_L8_JPGENC_Y_RDMA_MDP MTK_M4U_ID(8, 7) #define M4U_PORT_L8_JPGENC_C_RDMA_MDP MTK_M4U_ID(8, 8) #define M4U_PORT_L8_JPGENC_Q_TABLE_MDP MTK_M4U_ID(8, 9) #define M4U_PORT_L8_JPGENC_BSDMA_MDP MTK_M4U_ID(8, 10) #define M4U_PORT_L8_JPGENC_WDMA0_MDP MTK_M4U_ID(8, 11) #define M4U_PORT_L8_JPGENC_BSDMA0_MDP MTK_M4U_ID(8, 12) #define M4U_PORT_L8_VENC_NBM_WDMA_MDP MTK_M4U_ID(8, 13) #define M4U_PORT_L8_VENC_NBM_WDMA_LITE_MDP MTK_M4U_ID(8, 14) #define M4U_PORT_L8_VENC_CUR_LUMA_MDP MTK_M4U_ID(8, 15) #define M4U_PORT_L8_VENC_CUR_CHROMA_MDP MTK_M4U_ID(8, 16) #define M4U_PORT_L8_VENC_REF_LUMA_MDP MTK_M4U_ID(8, 17) #define M4U_PORT_L8_VENC_REF_CHROMA_MDP MTK_M4U_ID(8, 18) #define M4U_PORT_L8_VENC_SUB_R_LUMA_MDP MTK_M4U_ID(8, 19) #define M4U_PORT_L8_VENC_SUB_W_LUMA_MDP MTK_M4U_ID(8, 20) #define M4U_PORT_L8_VENC_FCS_NBM_RDMA_MDP MTK_M4U_ID(8, 21) #define M4U_PORT_L8_VENC_FCS_NBM_WDMA_MDP MTK_M4U_ID(8, 22) #define M4U_PORT_L8_JPGENC_WDMA1_MDP MTK_M4U_ID(8, 23) #define M4U_PORT_L8_JPGENC_BSDMA1_MDP MTK_M4U_ID(8, 24) #define M4U_PORT_L8_JPGENC_HUFF_OFFSET1_MDP MTK_M4U_ID(8, 25) #define M4U_PORT_L8_JPGENC_HUFF_OFFSET0_MDP MTK_M4U_ID(8, 26) /* larb9 -- 29*/ #define M4U_PORT_L9_IMG_IMGI_D1_MDP MTK_M4U_ID(9, 0) #define M4U_PORT_L9_IMG_IMGBI_D1_MDP MTK_M4U_ID(9, 1) #define M4U_PORT_L9_IMG_DMGI_D1_MDP MTK_M4U_ID(9, 2) #define M4U_PORT_L9_IMG_DEPI_D1_MDP MTK_M4U_ID(9, 3) #define M4U_PORT_L9_IMG_ICE_D1_MDP MTK_M4U_ID(9, 4) #define M4U_PORT_L9_IMG_SMTI_D1_MDP MTK_M4U_ID(9, 5) #define M4U_PORT_L9_IMG_SMTO_D2_MDP MTK_M4U_ID(9, 6) #define M4U_PORT_L9_IMG_SMTO_D1_MDP MTK_M4U_ID(9, 7) #define M4U_PORT_L9_IMG_CRZO_D1_MDP MTK_M4U_ID(9, 8) #define M4U_PORT_L9_IMG_IMG3O_D1_MDP MTK_M4U_ID(9, 9) #define M4U_PORT_L9_IMG_VIPI_D1_MDP MTK_M4U_ID(9, 10) #define M4U_PORT_L9_IMG_SMTI_D5_MDP MTK_M4U_ID(9, 11) #define M4U_PORT_L9_IMG_TIMGO_D1_MDP MTK_M4U_ID(9, 12) #define M4U_PORT_L9_IMG_UFBC_W0_MDP MTK_M4U_ID(9, 13) #define M4U_PORT_L9_IMG_UFBC_R0_MDP MTK_M4U_ID(9, 14) #define M4U_PORT_L9_IMG_WPE_RDMA1_MDP MTK_M4U_ID(9, 15) #define M4U_PORT_L9_IMG_WPE_RDMA0_MDP MTK_M4U_ID(9, 16) #define M4U_PORT_L9_IMG_WPE_WDMA_MDP MTK_M4U_ID(9, 17) #define M4U_PORT_L9_IMG_MFB_RDMA0_MDP MTK_M4U_ID(9, 18) #define M4U_PORT_L9_IMG_MFB_RDMA1_MDP MTK_M4U_ID(9, 19) #define M4U_PORT_L9_IMG_MFB_RDMA2_MDP MTK_M4U_ID(9, 20) #define M4U_PORT_L9_IMG_MFB_RDMA3_MDP MTK_M4U_ID(9, 21) #define M4U_PORT_L9_IMG_MFB_RDMA4_MDP MTK_M4U_ID(9, 22) #define M4U_PORT_L9_IMG_MFB_RDMA5_MDP MTK_M4U_ID(9, 23) #define M4U_PORT_L9_IMG_MFB_WDMA0_MDP MTK_M4U_ID(9, 24) #define M4U_PORT_L9_IMG_MFB_WDMA1_MDP MTK_M4U_ID(9, 25) #define M4U_PORT_L9_IMG_RESERVE6_MDP MTK_M4U_ID(9, 26) #define M4U_PORT_L9_IMG_RESERVE7_MDP MTK_M4U_ID(9, 27) #define M4U_PORT_L9_IMG_RESERVE8_MDP MTK_M4U_ID(9, 28) /* larb10 -- not existed*/ /* larb11 -- 29*/ #define M4U_PORT_L11_IMG_IMGI_D1_DISP MTK_M4U_ID(11, 0) #define M4U_PORT_L11_IMG_IMGBI_D1_DISP MTK_M4U_ID(11, 1) #define M4U_PORT_L11_IMG_DMGI_D1_DISP MTK_M4U_ID(11, 2) #define M4U_PORT_L11_IMG_DEPI_D1_DISP MTK_M4U_ID(11, 3) #define M4U_PORT_L11_IMG_ICE_D1_DISP MTK_M4U_ID(11, 4) #define M4U_PORT_L11_IMG_SMTI_D1_DISP MTK_M4U_ID(11, 5) #define M4U_PORT_L11_IMG_SMTO_D2_DISP MTK_M4U_ID(11, 6) #define M4U_PORT_L11_IMG_SMTO_D1_DISP MTK_M4U_ID(11, 7) #define M4U_PORT_L11_IMG_CRZO_D1_DISP MTK_M4U_ID(11, 8) #define M4U_PORT_L11_IMG_IMG3O_D1_DISP MTK_M4U_ID(11, 9) #define M4U_PORT_L11_IMG_VIPI_D1_DISP MTK_M4U_ID(11, 10) #define M4U_PORT_L11_IMG_SMTI_D5_DISP MTK_M4U_ID(11, 11) #define M4U_PORT_L11_IMG_TIMGO_D1_DISP MTK_M4U_ID(11, 12) #define M4U_PORT_L11_IMG_UFBC_W0_DISP MTK_M4U_ID(11, 13) #define M4U_PORT_L11_IMG_UFBC_R0_DISP MTK_M4U_ID(11, 14) #define M4U_PORT_L11_IMG_WPE_RDMA1_DISP MTK_M4U_ID(11, 15) #define M4U_PORT_L11_IMG_WPE_RDMA0_DISP MTK_M4U_ID(11, 16) #define M4U_PORT_L11_IMG_WPE_WDMA_DISP MTK_M4U_ID(11, 17) #define M4U_PORT_L11_IMG_MFB_RDMA0_DISP MTK_M4U_ID(11, 18) #define M4U_PORT_L11_IMG_MFB_RDMA1_DISP MTK_M4U_ID(11, 19) #define M4U_PORT_L11_IMG_MFB_RDMA2_DISP MTK_M4U_ID(11, 20) #define M4U_PORT_L11_IMG_MFB_RDMA3_DISP MTK_M4U_ID(11, 21) #define M4U_PORT_L11_IMG_MFB_RDMA4_DISP MTK_M4U_ID(11, 22) #define M4U_PORT_L11_IMG_MFB_RDMA5_DISP MTK_M4U_ID(11, 23) #define M4U_PORT_L11_IMG_MFB_WDMA0_DISP MTK_M4U_ID(11, 24) #define M4U_PORT_L11_IMG_MFB_WDMA1_DISP MTK_M4U_ID(11, 25) #define M4U_PORT_L11_IMG_RESERVE6_DISP MTK_M4U_ID(11, 26) #define M4U_PORT_L11_IMG_RESERVE7_DISP MTK_M4U_ID(11, 27) #define M4U_PORT_L11_IMG_RESERVE8_DISP MTK_M4U_ID(11, 28) /* larb12 -- not existed*/ /* larb13 -- 12*/ #define M4U_PORT_L13_CAM_MRAWI_MDP MTK_M4U_ID(13, 0) #define M4U_PORT_L13_CAM_MRAWO0_MDP MTK_M4U_ID(13, 1) #define M4U_PORT_L13_CAM_MRAWO1_MDP MTK_M4U_ID(13, 2) #define M4U_PORT_L13_CAM_CAMSV1_MDP MTK_M4U_ID(13, 3) #define M4U_PORT_L13_CAM_CAMSV2_MDP MTK_M4U_ID(13, 4) #define M4U_PORT_L13_CAM_CAMSV3_MDP MTK_M4U_ID(13, 5) #define M4U_PORT_L13_CAM_CAMSV4_MDP MTK_M4U_ID(13, 6) #define M4U_PORT_L13_CAM_CAMSV5_MDP MTK_M4U_ID(13, 7) #define M4U_PORT_L13_CAM_CAMSV6_MDP MTK_M4U_ID(13, 8) #define M4U_PORT_L13_CAM_CCUI_MDP MTK_M4U_ID(13, 9) #define M4U_PORT_L13_CAM_CCUO_MDP MTK_M4U_ID(13, 10) #define M4U_PORT_L13_CAM_FAKE_MDP MTK_M4U_ID(13, 11) /* larb14 -- 6*/ #define M4U_PORT_L14_CAM_MRAWI_DISP MTK_M4U_ID(14, 0) #define M4U_PORT_L14_CAM_MRAWO0_DISP MTK_M4U_ID(14, 1) #define M4U_PORT_L14_CAM_MRAWO1_DISP MTK_M4U_ID(14, 2) #define M4U_PORT_L14_CAM_CAMSV0_DISP MTK_M4U_ID(14, 3) #define M4U_PORT_L14_CAM_CCUI_DISP MTK_M4U_ID(14, 4) #define M4U_PORT_L14_CAM_CCUO_DISP MTK_M4U_ID(14, 5) /* larb15 -- no iommu user*/ /* larb16 -- 17*/ #define M4U_PORT_L16_CAM_IMGO_R1_A_MDP MTK_M4U_ID(16, 0) #define M4U_PORT_L16_CAM_RRZO_R1_A_MDP MTK_M4U_ID(16, 1) #define M4U_PORT_L16_CAM_CQI_R1_A_MDP MTK_M4U_ID(16, 2) #define M4U_PORT_L16_CAM_BPCI_R1_A_MDP MTK_M4U_ID(16, 3) #define M4U_PORT_L16_CAM_YUVO_R1_A_MDP MTK_M4U_ID(16, 4) #define M4U_PORT_L16_CAM_UFDI_R2_A_MDP MTK_M4U_ID(16, 5) #define M4U_PORT_L16_CAM_RAWI_R2_A_MDP MTK_M4U_ID(16, 6) #define M4U_PORT_L16_CAM_RAWI_R3_A_MDP MTK_M4U_ID(16, 7) #define M4U_PORT_L16_CAM_AAO_R1_A_MDP MTK_M4U_ID(16, 8) #define M4U_PORT_L16_CAM_AFO_R1_A_MDP MTK_M4U_ID(16, 9) #define M4U_PORT_L16_CAM_FLKO_R1_A_MDP MTK_M4U_ID(16, 10) #define M4U_PORT_L16_CAM_LCESO_R1_A_MDP MTK_M4U_ID(16, 11) #define M4U_PORT_L16_CAM_CRZO_R1_A_MDP MTK_M4U_ID(16, 12) #define M4U_PORT_L16_CAM_LTMSO_R1_A_MDP MTK_M4U_ID(16, 13) #define M4U_PORT_L16_CAM_RSSO_R1_A_MDP MTK_M4U_ID(16, 14) #define M4U_PORT_L16_CAM_AAHO_R1_A_MDP MTK_M4U_ID(16, 15) #define M4U_PORT_L16_CAM_LSCI_R1_A_MDP MTK_M4U_ID(16, 16) /* larb17 -- 17*/ #define M4U_PORT_L17_CAM_IMGO_R1_B_DISP MTK_M4U_ID(17, 0) #define M4U_PORT_L17_CAM_RRZO_R1_B_DISP MTK_M4U_ID(17, 1) #define M4U_PORT_L17_CAM_CQI_R1_B_DISP MTK_M4U_ID(17, 2) #define M4U_PORT_L17_CAM_BPCI_R1_B_DISP MTK_M4U_ID(17, 3) #define M4U_PORT_L17_CAM_YUVO_R1_B_DISP MTK_M4U_ID(17, 4) #define M4U_PORT_L17_CAM_UFDI_R2_B_DISP MTK_M4U_ID(17, 5) #define M4U_PORT_L17_CAM_RAWI_R2_B_DISP MTK_M4U_ID(17, 6) #define M4U_PORT_L17_CAM_RAWI_R3_B_DISP MTK_M4U_ID(17, 7) #define M4U_PORT_L17_CAM_AAO_R1_B_DISP MTK_M4U_ID(17, 8) #define M4U_PORT_L17_CAM_AFO_R1_B_DISP MTK_M4U_ID(17, 9) #define M4U_PORT_L17_CAM_FLKO_R1_B_DISP MTK_M4U_ID(17, 10) #define M4U_PORT_L17_CAM_LCESO_R1_B_DISP MTK_M4U_ID(17, 11) #define M4U_PORT_L17_CAM_CRZO_R1_B_DISP MTK_M4U_ID(17, 12) #define M4U_PORT_L17_CAM_LTMSO_R1_B_DISP MTK_M4U_ID(17, 13) #define M4U_PORT_L17_CAM_RSSO_R1_B_DISP MTK_M4U_ID(17, 14) #define M4U_PORT_L17_CAM_AAHO_R1_B_DISP MTK_M4U_ID(17, 15) #define M4U_PORT_L17_CAM_LSCI_R1_B_DISP MTK_M4U_ID(17, 16) /* larb18 -- 17*/ #define M4U_PORT_L18_CAM_IMGO_R1_C_MDP MTK_M4U_ID(18, 0) #define M4U_PORT_L18_CAM_RRZO_R1_C_MDP MTK_M4U_ID(18, 1) #define M4U_PORT_L18_CAM_CQI_R1_C_MDP MTK_M4U_ID(18, 2) #define M4U_PORT_L18_CAM_BPCI_R1_C_MDP MTK_M4U_ID(18, 3) #define M4U_PORT_L18_CAM_YUVO_R1_C_MDP MTK_M4U_ID(18, 4) #define M4U_PORT_L18_CAM_UFDI_R2_C_MDP MTK_M4U_ID(18, 5) #define M4U_PORT_L18_CAM_RAWI_R2_C_MDP MTK_M4U_ID(18, 6) #define M4U_PORT_L18_CAM_RAWI_R3_C_MDP MTK_M4U_ID(18, 7) #define M4U_PORT_L18_CAM_AAO_R1_C_MDP MTK_M4U_ID(18, 8) #define M4U_PORT_L18_CAM_AFO_R1_C_MDP MTK_M4U_ID(18, 9) #define M4U_PORT_L18_CAM_FLKO_R1_C_MDP MTK_M4U_ID(18, 10) #define M4U_PORT_L18_CAM_LCESO_R1_C_MDP MTK_M4U_ID(18, 11) #define M4U_PORT_L18_CAM_CRZO_R1_C_MDP MTK_M4U_ID(18, 12) #define M4U_PORT_L18_CAM_LTMSO_R1_C_MDP MTK_M4U_ID(18, 13) #define M4U_PORT_L18_CAM_RSSO_R1_C_MDP MTK_M4U_ID(18, 14) #define M4U_PORT_L18_CAM_AAHO_R1_C_MDP MTK_M4U_ID(18, 15) #define M4U_PORT_L18_CAM_LSCI_R1_C_MDP MTK_M4U_ID(18, 16) /* larb19 -- 4*/ #define M4U_PORT_L19_IPE_DVS_RDMA_DISP MTK_M4U_ID(19, 0) #define M4U_PORT_L19_IPE_DVS_WDMA_DISP MTK_M4U_ID(19, 1) #define M4U_PORT_L19_IPE_DVP_RDMA_DISP MTK_M4U_ID(19, 2) #define M4U_PORT_L19_IPE_DVP_WDMA_DISP MTK_M4U_ID(19, 3) /* larb20 -- 6*/ #define M4U_PORT_L20_IPE_FDVT_RDA_DISP MTK_M4U_ID(20, 0) #define M4U_PORT_L20_IPE_FDVT_RDB_DISP MTK_M4U_ID(20, 1) #define M4U_PORT_L20_IPE_FDVT_WRA_DISP MTK_M4U_ID(20, 2) #define M4U_PORT_L20_IPE_FDVT_WRB_DISP MTK_M4U_ID(20, 3) #define M4U_PORT_L20_IPE_RSC_RDMA0_DISP MTK_M4U_ID(20, 4) #define M4U_PORT_L20_IPE_RSC_WDMA_DISP MTK_M4U_ID(20, 5) #define M4U_PORT_L21_APU_FAKE_CODE MTK_M4U_ID(APU_PSEUDO_LARBID, 0) #define M4U_PORT_L21_APU_FAKE_DATA MTK_M4U_ID(APU_PSEUDO_LARBID, 1) #define M4U_PORT_L21_APU_FAKE_VLM MTK_M4U_ID(APU_PSEUDO_LARBID, 2) #define M4U_PORT_L22_CCU_DISP MTK_M4U_ID(CCU_PSEUDO_LARBID_DISP, 0) #define M4U_PORT_L23_CCU_MDP MTK_M4U_ID(CCU_PSEUDO_LARBID_MDP, 0) #define M4U_PORT_UNKNOWN (M4U_PORT_L23_CCU_MDP + 1) #define M4U_PORT_GPU MTK_M4U_ID(31, 31) #define M4U_PORT_NR (257) #define M4U_PORT_APU (M4U_PORT_L21_APU_FAKE_DATA) #define M4U_PORT_APU_CODE (M4U_PORT_L21_APU_FAKE_CODE) #define M4U_PORT_CCU (M4U_PORT_L23_CCU_MDP) #define M4U_PORT_OVL_DEBUG M4U_PORT_L0_DISP_FAKE0 #define M4U_PORT_MDP_DEBUG M4U_PORT_L2_MDP_FAKE0 #define M4U_PORT_BOUNDARY0_DEBUG M4U_PORT_L0_DISP_FAKE0 #define M4U_PORT_BOUNDARY1_DEBUG M4U_PORT_L8_VENC_RCPU_MDP #define M4U_PORT_BOUNDARY2_DEBUG M4U_PORT_L2_MDP_FAKE0 #define M4U_PORT_BOUNDARY3_DEBUG M4U_PORT_L21_APU_FAKE_DATA /* for pusedo ccu device */ #define MISC_PSEUDO_LARBID_DISP (MTK_IOMMU_LARB_NR) #define APU_PSEUDO_LARBID_CODE (MTK_IOMMU_LARB_NR + 1) #define APU_PSEUDO_LARBID_DATA (MTK_IOMMU_LARB_NR + 2) #define APU_PSEUDO_LARBID_VLM (MTK_IOMMU_LARB_NR + 3) #define CCU_PSEUDO_LARBID_LARB (MTK_IOMMU_LARB_NR + 4) #if defined(CONFIG_MTK_IOMMU_PGTABLE_EXT) && \ (CONFIG_MTK_IOMMU_PGTABLE_EXT == 34) #define MTK_IOVA_ADDR_BITS 34 #define MTK_PHYS_ADDR_BITS 35 #else #define MTK_IOVA_ADDR_BITS 32 #define MTK_PHYS_ADDR_BITS 34 #endif #ifdef CONFIG_FPGA_EARLY_PORTING #define MTK_IOMMU_M4U_COUNT (1) #else #define MTK_IOMMU_M4U_COUNT (4) #endif #define MTK_IOMMU_DEBUG_REG_NR (6) #define MTK_IOMMU_WAY_NR (4) #define MTK_IOMMU_RS_COUNT (16) #define MTK_IOMMU_MMU_COUNT (2) #define MTK_IOMMU_TAG_COUNT (64) #define MTK_IOMMU_BANK_COUNT (5) #define MTK_IOMMU_MAU_COUNT (1) #define MTK_MMU_NUM_OF_IOMMU(m4u_id) MTK_IOMMU_MMU_COUNT #define MTK_MAU_NUM_OF_MMU(mmu_id) MTK_IOMMU_MAU_COUNT #define MMU_PAGE_PER_LINE (8) #define MMU_ENTRY_PER_VICTIM (16) #define MTK_IOMMU_LARB_CODEC_MIN (4) #define MTK_IOMMU_LARB_CODEC_MAX (11) #define MTK_IOMMU_IOVA_BOUNDARY_COUNT \ (1 << (CONFIG_MTK_IOMMU_PGTABLE_EXT - 32)) #define APU_IOMMU_INDEX (2) #define MTK_IOMMU_PORT_TRANSFER_DISABLE #endif