/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2020 MediaTek Inc.
 */

#ifndef __SMI_CONF_DBG_H__
#define __SMI_CONF_DBG_H__

#include "smi_reg.h"

void __iomem *smi_mmsys_base;

#define SMI_MMSYS_DEBUG_NUM	((SMI_LARB_NUM_MAX) * 3 + 6)
u32 smi_mmsys_debug_offset[SMI_MMSYS_DEBUG_NUM] = {
	MMSYS_CG_CON0, MMSYS_CG_CON1,
	MMSYS_HW_DCM_1ST_DIS0, MMSYS_HW_DCM_1ST_DIS_SET0,
	MMSYS_HW_DCM_2ND_DIS0, MMSYS_SW0_RST_B,
	DISP_GALS_DBG(0), DISP_GALS_DBG(1), DISP_GALS_DBG(2), DISP_GALS_DBG(3),
	DISP_GALS_DBG(4), DISP_GALS_DBG(5), DISP_GALS_DBG(6),
	DISP_GALS_DBG(7), DISP_GALS_DBG(8), DISP_GALS_DBG(9),
	DISP_GALS_DBG(10), DISP_GALS_DBG(11), DISP_GALS_DBG(12),
	DISP_GALS_DBG(13), DISP_GALS_DBG(14), DISP_GALS_DBG(15),
	MMSYS_GALS_DBG(0), MMSYS_GALS_DBG(1), MMSYS_GALS_DBG(2),
	MMSYS_GALS_DBG(3), MMSYS_GALS_DBG(4), MMSYS_GALS_DBG(5),
	MMSYS_GALS_DBG(6), MMSYS_GALS_DBG(7),
};

#define SMI_COMM_DEBUG_NUM	((SMI_LARB_NUM_MAX) * 4 + 27)
u32 smi_comm_debug_offset[SMI_COMM_DEBUG_NUM] = {
	SMI_L1LEN,
	SMI_L1ARB(0), SMI_L1ARB(1), SMI_L1ARB(2), SMI_L1ARB(3),
	SMI_L1ARB(4), SMI_L1ARB(5), SMI_L1ARB(6), SMI_L1ARB(7),
	SMI_MON_AXI_ENA, SMI_MON_AXI_CLR, SMI_MON_AXI_ACT_CNT,
	SMI_BUS_SEL, SMI_WRR_REG0, SMI_WRR_REG1,
	SMI_READ_FIFO_TH, SMI_M4U_TH, SMI_FIFO_TH1, SMI_FIFO_TH2,
	SMI_PREULTRA_MASK0, SMI_PREULTRA_MASK1, SMI_DCM, SMI_ELA,
	SMI_Mx_RWULTRA_WRRy(1, 0, 0), SMI_Mx_RWULTRA_WRRy(1, 0, 1),
	SMI_Mx_RWULTRA_WRRy(1, 1, 0), SMI_Mx_RWULTRA_WRRy(1, 1, 1),
	SMI_Mx_RWULTRA_WRRy(2, 0, 0), SMI_Mx_RWULTRA_WRRy(2, 0, 1),
	SMI_Mx_RWULTRA_WRRy(2, 1, 0), SMI_Mx_RWULTRA_WRRy(2, 1, 1),
	SMI_COMMON_CLAMP_EN, SMI_COMMON_CLAMP_EN_SET, SMI_COMMON_CLAMP_EN_CLR,
	SMI_DEBUG_S(0), SMI_DEBUG_S(1), SMI_DEBUG_S(2), SMI_DEBUG_S(3),
	SMI_DEBUG_S(4), SMI_DEBUG_S(5), SMI_DEBUG_S(6), SMI_DEBUG_S(7),
	SMI_DEBUG_EXT(0), SMI_DEBUG_EXT(1), SMI_DEBUG_EXT(2), SMI_DEBUG_EXT(3),
	SMI_DEBUG_M0, SMI_DEBUG_M1, SMI_DEBUG_EXT4, SMI_DEBUG_EXT5,
	SMI_DEBUG_MISC, SMI_DUMMY, SMI_DEBUG_EXT6, SMI_DEBUG_EXT7,
	SMI_AST_EN, SMI_AST_COND, SMI_TIMEOUT, SMI_TIMEOUT_CNT, SMI_AST_STA,
};

#define SMI_LARB_DEBUG_NUM	((SMI_PORT_NUM_MAX) * 4 + 31)
u32 smi_larb_debug_offset[SMI_LARB_DEBUG_NUM] = {
	SMI_LARB_STAT, SMI_LARB_IRQ_STATUS, SMI_LARB_SLP_CON,
	SMI_LARB_CON, SMI_LARB_CON_SET,
	SMI_LARB_VC_PRI_MODE, SMI_LARB_CMD_THRT_CON,
	SMI_LARB_SW_FLAG, SMI_LARB_BWL_EN, SMI_LARB_OSTDL_EN,
	SMI_LARB_ULTRA_DIS, SMI_LARB_FORCE_ULTRA,
	SMI_LARB_SPM_ULTRA_MASK, SMI_LARB_SPM_STA,
	SMI_LARB_EXT_GREQ_VIO, SMI_LARB_INT_GREQ_VIO,
	SMI_LARB_OSTD_UDF_VIO, SMI_LARB_OSTD_CRS_VIO,
	SMI_LARB_FIFO_STAT, SMI_LARB_BUS_STAT, SMI_LARB_CMD_THRT_STAT,
	SMI_LARB_MON_REQ, SMI_LARB_REQ_MASK,
	SMI_LARB_EXT_ONGOING, SMI_LARB_INT_ONGOING, SMI_LARB_DBG_CON,
	SMI_LARB_WRR_PORT(0), SMI_LARB_WRR_PORT(1), SMI_LARB_WRR_PORT(2),
	SMI_LARB_WRR_PORT(3), SMI_LARB_WRR_PORT(4), SMI_LARB_WRR_PORT(5),
	SMI_LARB_WRR_PORT(6), SMI_LARB_WRR_PORT(7), SMI_LARB_WRR_PORT(8),
	SMI_LARB_WRR_PORT(9), SMI_LARB_WRR_PORT(10), SMI_LARB_WRR_PORT(11),
	SMI_LARB_WRR_PORT(12), SMI_LARB_WRR_PORT(13), SMI_LARB_WRR_PORT(14),
	SMI_LARB_WRR_PORT(15), SMI_LARB_WRR_PORT(16), SMI_LARB_WRR_PORT(17),
	SMI_LARB_WRR_PORT(18), SMI_LARB_WRR_PORT(19), SMI_LARB_WRR_PORT(20),
	SMI_LARB_WRR_PORT(21), SMI_LARB_WRR_PORT(22), SMI_LARB_WRR_PORT(23),
	SMI_LARB_WRR_PORT(24), SMI_LARB_WRR_PORT(25), SMI_LARB_WRR_PORT(26),
	SMI_LARB_WRR_PORT(27), SMI_LARB_WRR_PORT(28), SMI_LARB_WRR_PORT(29),
	SMI_LARB_WRR_PORT(30), SMI_LARB_WRR_PORT(31),
	SMI_LARB_OSTDL_PORT(0), SMI_LARB_OSTDL_PORT(1), SMI_LARB_OSTDL_PORT(2),
	SMI_LARB_OSTDL_PORT(3), SMI_LARB_OSTDL_PORT(4), SMI_LARB_OSTDL_PORT(5),
	SMI_LARB_OSTDL_PORT(6), SMI_LARB_OSTDL_PORT(7), SMI_LARB_OSTDL_PORT(8),
	SMI_LARB_OSTDL_PORT(9), SMI_LARB_OSTDL_PORT(10),
	SMI_LARB_OSTDL_PORT(11), SMI_LARB_OSTDL_PORT(12),
	SMI_LARB_OSTDL_PORT(13), SMI_LARB_OSTDL_PORT(14),
	SMI_LARB_OSTDL_PORT(15), SMI_LARB_OSTDL_PORT(16),
	SMI_LARB_OSTDL_PORT(17), SMI_LARB_OSTDL_PORT(18),
	SMI_LARB_OSTDL_PORT(19), SMI_LARB_OSTDL_PORT(20),
	SMI_LARB_OSTDL_PORT(21), SMI_LARB_OSTDL_PORT(22),
	SMI_LARB_OSTDL_PORT(23), SMI_LARB_OSTDL_PORT(24),
	SMI_LARB_OSTDL_PORT(25), SMI_LARB_OSTDL_PORT(26),
	SMI_LARB_OSTDL_PORT(27), SMI_LARB_OSTDL_PORT(28),
	SMI_LARB_OSTDL_PORT(29), SMI_LARB_OSTDL_PORT(30),
	SMI_LARB_OSTDL_PORT(31),
	SMI_LARB_OSTD_MON_PORT(0), SMI_LARB_OSTD_MON_PORT(1),
	SMI_LARB_OSTD_MON_PORT(2), SMI_LARB_OSTD_MON_PORT(3),
	SMI_LARB_OSTD_MON_PORT(4), SMI_LARB_OSTD_MON_PORT(5),
	SMI_LARB_OSTD_MON_PORT(6), SMI_LARB_OSTD_MON_PORT(7),
	SMI_LARB_OSTD_MON_PORT(8), SMI_LARB_OSTD_MON_PORT(9),
	SMI_LARB_OSTD_MON_PORT(10), SMI_LARB_OSTD_MON_PORT(11),
	SMI_LARB_OSTD_MON_PORT(12), SMI_LARB_OSTD_MON_PORT(13),
	SMI_LARB_OSTD_MON_PORT(14), SMI_LARB_OSTD_MON_PORT(15),
	SMI_LARB_OSTD_MON_PORT(16), SMI_LARB_OSTD_MON_PORT(17),
	SMI_LARB_OSTD_MON_PORT(18), SMI_LARB_OSTD_MON_PORT(19),
	SMI_LARB_OSTD_MON_PORT(20), SMI_LARB_OSTD_MON_PORT(21),
	SMI_LARB_OSTD_MON_PORT(22), SMI_LARB_OSTD_MON_PORT(23),
	SMI_LARB_OSTD_MON_PORT(24), SMI_LARB_OSTD_MON_PORT(25),
	SMI_LARB_OSTD_MON_PORT(26), SMI_LARB_OSTD_MON_PORT(27),
	SMI_LARB_OSTD_MON_PORT(28), SMI_LARB_OSTD_MON_PORT(29),
	SMI_LARB_OSTD_MON_PORT(30), SMI_LARB_OSTD_MON_PORT(31),
	SMI_LARB_NON_SEC_CON(0), SMI_LARB_NON_SEC_CON(1),
	SMI_LARB_NON_SEC_CON(2), SMI_LARB_NON_SEC_CON(3),
	SMI_LARB_NON_SEC_CON(4), SMI_LARB_NON_SEC_CON(5),
	SMI_LARB_NON_SEC_CON(6), SMI_LARB_NON_SEC_CON(7),
	SMI_LARB_NON_SEC_CON(8), SMI_LARB_NON_SEC_CON(9),
	SMI_LARB_NON_SEC_CON(10), SMI_LARB_NON_SEC_CON(11),
	SMI_LARB_NON_SEC_CON(12), SMI_LARB_NON_SEC_CON(13),
	SMI_LARB_NON_SEC_CON(14), SMI_LARB_NON_SEC_CON(15),
	SMI_LARB_NON_SEC_CON(16), SMI_LARB_NON_SEC_CON(17),
	SMI_LARB_NON_SEC_CON(18), SMI_LARB_NON_SEC_CON(19),
	SMI_LARB_NON_SEC_CON(20), SMI_LARB_NON_SEC_CON(21),
	SMI_LARB_NON_SEC_CON(22), SMI_LARB_NON_SEC_CON(23),
	SMI_LARB_NON_SEC_CON(24), SMI_LARB_NON_SEC_CON(25),
	SMI_LARB_NON_SEC_CON(26), SMI_LARB_NON_SEC_CON(27),
	SMI_LARB_NON_SEC_CON(28), SMI_LARB_NON_SEC_CON(29),
	SMI_LARB_NON_SEC_CON(30), SMI_LARB_NON_SEC_CON(31),
	SMI_LARB_MON_EN, SMI_LARB_MON_CLR, SMI_LARB_MON_ACT_CNT,
	INT_SMI_LARB_CMD_THRT_CON, INT_SMI_LARB_DBG_CON,
};
#endif