// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (c) 2019 MediaTek Inc.
 *
 */

/**********************************************
 *MSDC DTSI File
 *******************************************/
&msdc0 {
	index = /bits/ 8 <0>;
	clk_src = /bits/ 8 <MSDC0_CLKSRC_400MHZ>;
	bus-width = <8>;
	max-frequency = <200000000>;
	cap-mmc-highspeed;
	mmc-ddr-1_8v;
	mmc-hs200-1_8v;
	mmc-hs400-1_8v;
	no-sd;
	no-sdio;
	non-removable;
	pinctl = <&msdc0_pins_default>;
	pinctl_hs400 = <&msdc0_pins_hs400>;
	pinctl_hs200 = <&msdc0_pins_hs200>;
	register_setting = <&msdc0_register_setting_default>;
	host_function = /bits/ 8 <MSDC_EMMC>;
	bootable;
	status = "okay";
	infracfg = <&infracfg_ao>;
	topckgen = <&topckgen>;

#ifndef CONFIG_FPGA_EARLY_PORTING
	vmmc-supply = <&mt_pmic_vemc_ldo_reg>;
	clocks = <&infracfg_ao CLK_IFR_MSDC0_SRC>,
		<&infracfg_ao CLK_IFR_MSDC0>,
		<&infracfg_ao CLK_IFR_FAES_FDE>;
	clock-names = "msdc0-clock", "msdc0-hclock", "msdc0-aes-clock";
#endif
};


&msdc1 {
	index = /bits/ 8 <1>;
	clk_src = /bits/ 8 <MSDC1_CLKSRC_200MHZ>;
	bus-width = <4>;
	max-frequency = <200000000>;
	cap-sd-highspeed;
	sd-uhs-sdr12;
	sd-uhs-sdr25;
	sd-uhs-sdr50;
	sd-uhs-sdr104;
	sd-uhs-ddr50;
	no-mmc;
	no-sdio;

	pinctl = <&msdc1_pins_default>;
	pinctl_sdr104 = <&msdc1_pins_sdr104>;
	pinctl_sdr50 = <&msdc1_pins_sdr50>;
	pinctl_ddr50 = <&msdc1_pins_ddr50>;
	register_setting = <&msdc1_register_setting_default>;

	host_function = /bits/ 8 <MSDC_SD>;

	cd_level = /bits/ 8 <MSDC_CD_LOW>;
	cd-gpios = <&pio 1 0>;

	status = "okay";

#ifndef CONFIG_FPGA_EARLY_PORTING
	vmmc-supply = <&mt_pmic_vmch_ldo_reg>;
	vqmmc-supply = <&mt_pmic_vmc_ldo_reg>;
	mediatek,pwrap-regmap = <&pwrap>;
	clocks = <&infracfg_ao CLK_IFR_MSDC1_SRC>, <&infracfg_ao CLK_IFR_MSDC1>;
	clock-names = "msdc1-clock", "msdc1-hclock";
#endif
};

&msdc2 {
	status = "disable";
};

&msdc3 {
	status = "disable";
};

&pio {
	msdc0_pins_default: msdc0@default {
		pins_cmd {
			drive-strength = /bits/ 8 <3>;
		};
		pins_dat {
			drive-strength = /bits/ 8 <3>;
		};
		pins_clk {
			drive-strength = /bits/ 8 <3>;
		};
		pins_rst {
			drive-strength = /bits/ 8 <3>;
		};
		pins_ds {
			drive-strength = /bits/ 8 <3>;
		};
	};

	msdc0_pins_hs400: msdc0@hs400 {
		pins_cmd {
			drive-strength = /bits/ 8 <3>;
		};
		pins_dat {
			drive-strength = /bits/ 8 <4>;
		};
		pins_clk {
			drive-strength = /bits/ 8 <4>;
		};
		pins_rst {
			drive-strength = /bits/ 8 <3>;
		};
		pins_ds {
			drive-strength = /bits/ 8 <4>;
		};
	};

	msdc0_pins_hs200: msdc0@hs200 {
		pins_cmd {
			drive-strength = /bits/ 8 <3>;
		};
		pins_dat {
			drive-strength = /bits/ 8 <4>;
		};
		pins_clk {
			drive-strength = /bits/ 8 <4>;
		};
		pins_rst {
			drive-strength = /bits/ 8 <3>;
		};
		pins_ds {
			drive-strength = /bits/ 8 <4>;
		};
	};

	msdc0_register_setting_default: msdc0@register_default {
		cmd_edge = /bits/ 8 <MSDC_SMPL_RISING>;
		rdata_edge = /bits/ 8 <MSDC_SMPL_RISING>;
		wdata_edge = /bits/ 8 <MSDC_SMPL_RISING>;
	};

	msdc1_pins_default: msdc1@default {
		pins_cmd {
			drive-strength = /bits/ 8 <3>;
		};
		pins_dat {
			drive-strength = /bits/ 8 <3>;
		};
		pins_clk {
			drive-strength = /bits/ 8 <3>;
		};
	};

	msdc1_pins_sdr104: msdc1@sdr104 {
		pins_cmd {
			drive-strength = /bits/ 8 <3>;
		};
		pins_dat {
			drive-strength = /bits/ 8 <3>;
		};
		pins_clk {
			drive-strength = /bits/ 8 <3>;
		};
	};

	msdc1_pins_sdr50: msdc1@sdr50 {
		pins_cmd {
			drive-strength = /bits/ 8 <3>;
		};
		pins_dat {
			drive-strength = /bits/ 8 <3>;
		};
		pins_clk {
			drive-strength = /bits/ 8 <3>;
		};
	};

	msdc1_pins_ddr50: msdc1@ddr50 {
		pins_cmd {
			drive-strength = /bits/ 8 <3>;
		};
		pins_dat {
			drive-strength = /bits/ 8 <3>;
		};
		pins_clk {
			drive-strength = /bits/ 8 <3>;
		};
	};

	msdc1_register_setting_default: msdc1@register_default {
		cmd_edge = /bits/ 8 <MSDC_SMPL_RISING>;
		rdata_edge = /bits/ 8 <MSDC_SMPL_RISING>;
		wdata_edge = /bits/ 8 <MSDC_SMPL_RISING>;
	};

	msdc3_pins_default: msdc3@default {
		pins_cmd {
			drive-strength = /bits/ 8 <4>;
		};
		pins_dat {
			drive-strength = /bits/ 8 <4>;
		};
		pins_clk {
			drive-strength = /bits/ 8 <4>;
		};
	};

	msdc3_register_setting_default: msdc3@register_default {
		cmd_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
		rdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
		wdata_edge = /bits/ 8 <MSDC_SMPL_FALLING>;
	};
};