/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (c) 2019 MediaTek Inc.
*/

/dts-v1/;
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt6885-larb-port.h>
#include <dt-bindings/gce/mt6885-gce.h>
#include <dt-bindings/iio/mt635x-auxadc.h>
#include <dt-bindings/mfd/mt6315-irq.h>
#include <dt-bindings/mfd/mt6359-irq.h>
#include <dt-bindings/pinctrl/mt6885-pinfunc.h>
#include <dt-bindings/clock/mt6885-clk.h>
#include <dt-bindings/mmc/mt6885-msdc.h>
#include <dt-bindings/spmi/spmi.h>
#include <generated/autoconf.h>
#include "mediatek/mt6360.dtsi"

/ {
	model = "MT6885";
	compatible = "mediatek,MT6885";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	/* chosen */
	chosen: chosen {
		bootargs = "console=tty0 console=ttyS0,921600n1 root=/dev/ram \
vmalloc=400M slub_debug=OFZPU swiotlb=noforce \
firmware_class.path=/vendor/firmware \
page_owner=on loop.max_part=7";
		kaslr-seed = <0 0>;
	};

	aliases {
		ovl0 = &disp_ovl0;
		ovl1 = &disp_ovl1;
		ovl3 = &disp_ovl0_2l;
		ovl4 = &disp_ovl1_2l;
		ovl5 = &disp_ovl2_2l;
		ovl6 = &disp_ovl3_2l;
		rdma0 = &disp_rdma0;
		rdma4 = &disp_rdma4;
		rdma5 = &disp_rdma5;
		wdma0 = &disp_wdma0;
		wdma1 = &disp_wdma1;
		dsi0 = &dsi0;
		merge1=&disp_merge1;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@000 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0000>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
		};

		cpu1: cpu@001 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0100>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
		};

		cpu2: cpu@002 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0200>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
		};

		cpu3: cpu@003 {
			device_type = "cpu";
			compatible = "arm,cortex-a55";
			reg = <0x0300>;
			enable-method = "psci";
			clock-frequency = <1701000000>;
			cpu-idle-states = <&cpuoff_l &clusteroff_l &mcusysoff>;
		};

		cpu4: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a75";
			reg = <0x0400>;
			enable-method = "psci";
			clock-frequency = <2171000000>;
			cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
		};

		cpu5: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a75";
			reg = <0x0500>;
			enable-method = "psci";
			clock-frequency = <2171000000>;
			cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
		};

		cpu6: cpu@102 {
			device_type = "cpu";
			compatible = "arm,cortex-a75";
			reg = <0x0600>;
			enable-method = "psci";
			clock-frequency = <2171000000>;
			cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
		};

		cpu7: cpu@200 {
			device_type = "cpu";
			compatible = "arm,cortex-a75";
			reg = <0x0700>;
			enable-method = "psci";
			clock-frequency = <2171000000>;
			cpu-idle-states = <&cpuoff_b &clusteroff_b &mcusysoff>;
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&cpu0>;
				};
				core1 {
					cpu = <&cpu1>;
				};
				core2 {
					cpu = <&cpu2>;
				};
				core3 {
					cpu = <&cpu3>;
				};
				doe_dvfs_cl0: doe {
				};

			};

			cluster1 {
				core0 {
					cpu = <&cpu4>;
				};
				core1 {
					cpu = <&cpu5>;
				};
				core2 {
					cpu = <&cpu6>;
				};
				doe_dvfs_cl1: doe {
				};
			};

			cluster2 {
				core0 {
					cpu = <&cpu7>;
				};
				doe_dvfs_cl2: doe {
				};
			};

		};
		idle-states {
			entry-method = "arm,psci";
			cpuoff_l: cpuoff_l {
				compatible = "mediatek,idle-state";
				arm,psci-suspend-param = <0x00010001>;
				local-timer-stop;
				entry-latency-us = <50>;
				exit-latency-us = <100>;
				min-residency-us = <1600>;
			};
			cpuoff_b: cpuoff_b {
				compatible = "mediatek,idle-state";
				arm,psci-suspend-param = <0x00010001>;
				local-timer-stop;
				entry-latency-us = <50>;
				exit-latency-us = <100>;
				min-residency-us = <1400>;
			};
			clusteroff_l: clusteroff_l {
				compatible = "mediatek,idle-state";
				arm,psci-suspend-param = <0x01010001>;
				local-timer-stop;
				entry-latency-us = <100>;
				exit-latency-us = <250>;
				min-residency-us = <2100>;
			};
			clusteroff_b: clusteroff_b {
				compatible = "mediatek,idle-state";
				arm,psci-suspend-param = <0x01010001>;
				local-timer-stop;
				entry-latency-us = <100>;
				exit-latency-us = <250>;
				min-residency-us = <1900>;
			};
			mcusysoff: mcusysoff {
				compatible = "mediatek,idle-state";
				arm,psci-suspend-param = <0x01010002>;
				local-timer-stop;
				entry-latency-us = <300>;
				exit-latency-us = <1200>;
				min-residency-us = <2600>;
			};
		};
	};
	disp_leds {
		compatible = "mediatek,disp-leds";

		backlight {
			label = "lcd-backlight";
			max-brightness = <255>;
			led-bits = <8>;
			default-state = "on";
		};
	};

	mtk_lpm: mtk_lpm {
		compatible = "mediatek,mtk-lpm";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		suspend-method = "system";

		irq-remain = <&edge_keypad &edge_mdwdt>,
			     <&level_vpu_core0 &level_vpu_core1>,
			     <&level_vpu_core2>,
			     <&level_mtk_mdla0 &level_mtk_mdla1>,
			     <&level_edma0 &level_edma1>,
			     <&level_mali0 &level_mali1 &level_mali2>,
			     <&level_mali3 &level_mali4>,
			     <&level_i2c0>;

		resource-ctrl = <&bus26m &infra &syspll>,
				<&dram_s0 &dram_s1>;
		constraints = <&rc_bus26m &rc_syspll &rc_dram>;

		lpm_sysram: lpm_sysram@0011b500 {
			compatible = "mediatek,lpm-sysram";
			reg = <0 0x0011b500 0 0x300>;
		};

		irq-remain-list {
			edge_keypad: edge_keypad {
				target = <&keypad>;
				value = <1 0 0 0x04>;
			};
			edge_mdwdt: edge_mdwdt {
				target = <&mddriver>;
				value = <1 0 0x80000000 0x02000000>;
			};
			level_vpu_core0: level_vpu_core0 {
				target = <&vpu_core0>;
				value = <0 0 0 0>;
			};
			level_vpu_core1: level_vpu_core1 {
				target = <&vpu_core1>;
				value = <0 0 0 0>;
			};
			level_vpu_core2: level_vpu_core2 {
				target = <&vpu_core2>;
				value = <0 0 0 0>;
			};
			level_mtk_mdla0: level_mtk_mdla0 {
				target = <&mtk_mdla>;
				value = <0 0 0 0>;
			};
			level_mtk_mdla1: level_mtk_mdla1 {
				target = <&mtk_mdla>;
				value = <0 1 0 0>;
			};
			level_edma0: level_edma0 {
				target = <&edma0>;
				value = <0 0 0 0>;
			};
			level_edma1: level_edma1 {
				target = <&edma1>;
				value = <0 0 0 0>;
			};
			level_mali0: level_mali0 {
				target = <&mali>;
				value = <0 0 0 0>;
			};
			level_mali1: level_mali1 {
				target = <&mali>;
				value = <0 1 0 0>;
			};
			level_mali2: level_mali2 {
				target = <&mali>;
				value = <0 2 0 0>;
			};
			level_mali3: level_mali3 {
				target = <&mali>;
				value = <0 3 0 0>;
			};
			level_mali4: level_mali4 {
				target = <&mali>;
				value = <0 4 0 0>;
			};
			level_i2c0: level_i2c0 {
				target = <&i2c0>;
				value = <0 0 0 0>;
			};
		};
		resource-ctrl-list {
			bus26m: bus26m {
				id = <0x00000000>;
				value = <0>;
			};
			infra: infra {
				id = <0x00000001>;
				value = <0>;
			};
			syspll: syspll {
				id = <0x00000002>;
				value = <0>;
			};
			dram_s0: dram_s0 {
				id = <0x00000003>;
				value = <0>;
			};
			dram_s1: dram_s1 {
				id = <0x00000004>;
				value = <0>;
			};
		};
		constraint-list {
			rc_bus26m: rc_bus26m {
				id = <0x00000000>;
				value = <1>;
			};
			rc_syspll: rc_syspll {
				id = <0x00000001>;
				value = <1>;
			};
			rc_dram: rc_dram {
				id = <0x00000002>;
				value = <1>;
			};
		};
	};
	cpupm_sysram: cpupm-sysram@0011b000 {
			compatible = "mediatek,cpupm-sysram";
			reg = <0 0x0011b000 0 0x500>;
	};

	mcucfg_mp0_counter {
		compatible = "mediatek,mcucfg_mp0_counter";
		reg_mp0_counter_base = <&mcucfg>;
	};

	mcusys_ctrl: mcusys-ctrl@0c53a000 {
			compatible = "mediatek,mcusys-ctrl";
			reg = <0 0x0c53a000 0 0x1000>;
	};
	pmu {
		compatible = "arm,armv8-pmuv3";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	dsu-pmu-0 {
		compatible = "arm,dsu-pmu";
		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
		cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
			<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
	};

	memory {
		device_type = "memory";
		reg = <0 0x40000000 0 0x3e605000>;
	};

	psci {
		compatible      = "arm,psci-1.0";
		method          = "smc";
	};

	reserved_memory: reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		zmc-default {
			compatible = "mediatek,zone_movable_cma";
			size = <0 0x2d000000>;
			alignment = <0 0x1000000>;
			alloc-ranges = <0 0xc0000000 4 0x00000000>;
		};

		ion-carveout-heap {
			compatible = "mediatek,ion-carveout-heap";
			no-map;
#ifdef CONFIG_FPGA_EARLY_PORTING
			size = <0 0x10000000>;
#else
			size = <0 0xc000>;
#endif
			alignment = <0 0x1000>;
			alloc-ranges = <0 0x40000000 0 0x80000000>;
		};

		consys-reserve-memory {
			compatible = "mediatek,consys-reserve-memory";
			no-map;
			size = <0 0x450000>;
			alignment = <0 0x100000>;
			alloc-ranges = <0 0x40000000 0 0x80000000>;
		};

		wifi_mem: wifi-reserve-memory {
			compatible = "shared-dma-pool";
			no-map;
			size = <0 0xF20000>;
			alignment = <0 0x1000000>;
			alloc-ranges = <0 0x40000000 0 0x80000000>;
		};

		gps-reserve-memory {
			compatible = "mediatek,gps-reserve-memory";
			no-map;
			size = <0 0x100000>;
			alignment = <0 0x100000>;
			alloc-ranges = <0 0x40000000 0 0x80000000>;
		};

		reserve-memory-sspm_share {
			compatible = "mediatek,reserve-memory-sspm_share";
			no-map;
			status = "okay";
#if defined(CONFIG_MTK_GMO_RAM_OPTIMIZE) || defined(CONFIG_MTK_MET_MEM_ALLOC)
			size = <0 0x110000>; /* 1M + 64K */
#else
			size = <0 0x910000>; /* 9M + 64K */
#endif
			alignment = <0 0x10000>;
			alloc-ranges = <0 0x40000000 0 0x60000000>;
		};

		reserve-memory-adsp_share {
			compatible = "mediatek,reserve-memory-adsp_share";
			no-map;
			size = <0 0x1000000>;
			alloc-ranges = <0 0x40000000 0 0x40000000>;
			alignment = <0 0x10000>; //EMI 64KB Align
		};
		reserve-memory-scp_share {
			compatible = "mediatek,reserve-memory-scp_share";
			no-map;
			size = <0 0x00300000>; /*3 MB share mem size */
			alignment = <0 0x1000000>;
			alloc-ranges = <0 0x50000000 0 0x40000000>;
		};
		reserve-memory-mcupm_share {
			compatible = "mediatek,reserve-memory-mcupm_share";
			no-map;
			status = "okay";
			size = <0 0x200000>; /* 2M  */
			alignment = <0 0x10000>;
			alloc-ranges = <0 0x40000000 0 0x60000000>;
		};
	};

	cache_parity {
		compatible = "mediatek,cache_parity";
		version = <2>;
		err_level = <0>;
		interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	};

	qos@0011bb00 {
		compatible = "mediatek,qos-2.0";
		reg = <0 0x0011bb00 0 0x100>;
	};

	gic: interrupt-controller {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		#address-cells = <2>;
		#size-cells = <2>;
		#redistributor-regions = <1>;
		interrupt-parent = <&gic>;
		interrupt-controller;
		reg = <0 0x0c000000 0 0x40000>, // distributor
		      <0 0x0c040000 0 0x200000>; // redistributor
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
	};

	clocks {
		clk_null: clk_null {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <0>;
		};

		clk26m: clk26m {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <26000000>;
		};

		clk12m: clk12m {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <12000000>;
		};

		clk32k: clk32k {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32000>;
		};
	};

	chipid@08000000 {
		compatible = "mediatek,chipid";
		reg = <0 0x08000000 0 0x0004>,
		      <0 0x08000004 0 0x0004>,
		      <0 0x08000008 0 0x0004>,
		      <0 0x0800000c 0 0x0004>;
	};

	topckgen: topckgen@10000000 {
		compatible = "mediatek,topckgen", "syscon";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
	};

	infracfg_ao: infracfg_ao@10001000 {
		compatible = "mediatek,infracfg_ao", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		#clock-cells = <1>;
	};

	dcm: dcm@10001000 {
		compatible = "mediatek,mt6885-dcm";
		reg = <0 0x10001000 0 0x1000>,
			<0 0x10002000 0 0x1000>,
			<0 0x10022000 0 0x1000>,
			<0 0x10219000 0 0x1000>,
			<0 0x1021d000 0 0x1000>,
			<0 0x10235000 0 0x1000>,
			<0 0x10238000 0 0x1000>,
			<0 0x10245000 0 0x1000>,
			<0 0x10248000 0 0x1000>,
			<0 0x10255000 0 0x1000>,
			<0 0x10258000 0 0x1000>,
			<0 0x10265000 0 0x1000>,
			<0 0x10268000 0 0x1000>,
			<0 0x1030e000 0 0x1000>,
			<0 0x10400000 0 0x50000>,
			<0 0x11210000 0 0x1000>,
			<0 0x0c538000 0 0x5000>,
			<0 0x0c53a800 0 0x1000>;
		reg-names = "infracfg_ao",
			"infracfg_ao_mem",
			"infra_ao_bcrm",
			"emi",
			"sub_emi",
			"chn0_emi",
			"dramc_ch0_top5",
			"chn1_emi",
			"dramc_ch1_top5",
			"chn2_emi",
			"dramc_ch2_top5",
			"chn3_emi",
			"dramc_ch3_top5",
			"sub_infracfg_ao_mem",
			"sspm",
			"audio",
			"mp_cpusys_top",
			"cpccfg_reg";
	};

	scpsys: scpsys@10001000 {
		compatible = "mediatek,scpsys";
		reg = <0 0x10001000 0 0x1000>,		/* infracfg_ao */
			<0 0x10006000 0 0x1000>,	/* spm */
			<0 0x10000000 0 0x1000>;	/* topckgen */
		#clock-cells = <1>;
	};

	scp_dvfs {
		compatible = "mediatek,scp_dvfs";
		clocks =
			<&topckgen TOP_MUX_SCP>,
			<&clk26m>,
			<&topckgen TOP_UNIVPLL_D5>,
			<&topckgen TOP_MAINPLL_D6_D2>,
			<&topckgen TOP_MAINPLL_D6>,
			<&topckgen TOP_UNIVPLL_D6>,
			<&topckgen TOP_MAINPLL_D4_D2>,
			<&topckgen TOP_MAINPLL_D5_D2>,
			<&topckgen TOP_UNIVPLL_D4_D2>;

		clock-names =
			"clk_mux",
			"clk_pll_0",
			"clk_pll_1",
			"clk_pll_2",
			"clk_pll_3",
			"clk_pll_4",
			"clk_pll_5",
			"clk_pll_6",
			"clk_pll_7";
	};

	infracfg_ao_mem@10002000 {
		compatible = "mediatek,infracfg_ao_mem";
		reg = <0 0x10002000 0 0x1000>;
	};

	pericfg@10003000 {
		compatible = "mediatek,pericfg", "syscon";
		reg = <0 0x10003000 0 0x1000>;
		#clock-cells = <1>;
	};

	dbgtop@1000d000 {
		compatible = "mediatek,dbgtop";
		reg = <0 0x1000d000 0 0x1000>;
	};

	btif@1100c000 {
		compatible = "mediatek,btif";
		/*btif base*/
		reg = <0 0x1100c000 0 0x1000>,
			/*btif tx dma base*/
			<0 0x11000d80 0 0x80>,
			/*btif rx dma base*/
			<0 0x11000e00 0 0x80>;
		/*btif irq, IRQS_Sync ID, btif_irq_b*/
		interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
				   /*btif tx dma irq*/
				   <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
				   /*btif rx dma irq*/
				   <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg_ao INFRACFG_AO_BTIF_CG>,
			   /*btif clock*/
			   <&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
		/*ap dma clock*/
		clock-names = "btifc","apdmac";
	};

	iocfg_rm: iocfg_rm@11c20000 {
		compatible = "mediatek,iocfg_rm";
		reg = <0 0x11c20000 0 0x1000>;
	};

	iocfg_bm: iocfg_bm@11d10000 {
		compatible = "mediatek,iocfg_bm";
		reg = <0 0x11d10000 0 0x1000>;
	};

	iocfg_lm: iocfg_lm@11e20000 {
		compatible = "mediatek,iocfg_lm";
		reg = <0 0x11e20000 0 0x1000>;
	};

	iocfg_lb: iocfg_lb@11e70000 {
		compatible = "mediatek,iocfg_lb";
		reg = <0 0x11e70000 0 0x1000>;
	};

	iocfg_rt: iocfg_rt@11ea0000 {
		compatible = "mediatek,iocfg_rt";
		reg = <0 0x11ea0000 0 0x1000>;
	};

	iocfg_lt: iocfg_lt@11f20000 {
		compatible = "mediatek,iocfg_lt";
		reg = <0 0x11f20000 0 0x1000>;
	};

	iocfg_tm: iocfg_tm@11f30000 {
		compatible = "mediatek,iocfg_tm";
		reg = <0 0x11f30000 0 0x1000>;
	};

	eint: apirq@1000b000 {
		compatible = "mediatek,apirq";
		reg = <0 0x1000b000 0 0x1000>;
		interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
	};

	gpio: gpio@10005000 {
		compatible = "mediatek,gpio";
		reg = <0 0x10005000 0 0x1000>;
	};

	pio: pinctrl {
		compatible = "mediatek,mt6885-pinctrl";
		reg_bases = <&gpio>,
			    <&iocfg_rm>,
			    <&iocfg_bm>,
			    <&iocfg_lm>,
			    <&iocfg_lb>,
			    <&iocfg_rt>,
			    <&iocfg_lt>,
			    <&iocfg_tm>;
		reg_base_eint = <&eint>;
		pins-are-numbered;
		gpio-controller;
		gpio-ranges = <&pio 0 0 220>;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <4>;
		interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-parent = <&gic>;
	};

	msdc0: msdc@11230000 {
		compatible = "mediatek,msdc", "syscon";
		reg = <0 0x11230000 0 0x10000>;
		interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
		#clock-cells = <1>;
	};

	msdc1: msdc@11240000{
		compatible = "mediatek,msdc";
		reg = <0 0x11240000 0 0x1000>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
	};

	msdc0_top@11f50000 {
		compatible = "mediatek,msdc0_top";
		reg = <0 0x11f50000 0 0x1000>;
	};

	msdc1_top@11e10000 {
		compatible = "mediatek,msdc1_top";
		reg = <0 0x11e10000 0 0x1000>;
	};

	sleep@10006000 {
		compatible = "mediatek,sleep";
		reg = <0 0x10006000 0 0x1000>;
	};

	spmtwam: spmtwam@10006000 {
		compatible = "mediatek,spmtwam";
		reg = <0 0x10006000 0 0x1000>;
		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
		spm_twam_con = <0xa0>;
		spm_twam_window_len = <0xa4>;
		spm_twam_idle_sel = <0xa8>;
		spm_irq_mask = <0xb4>;
		spm_irq_sta = <0x128>;
		spm_twam_last_sta0 = <0x1d0>;
		spm_twam_last_sta1 = <0x1d4>;
		spm_twam_last_sta2 = <0x1d8>;
		spm_twam_last_sta3 = <0x1dc>;
	};

	srclken@10006500 {
		compatible = "mediatek,srclken";
		reg = <0 0x10006500 0 0x1000>;
	};

	toprgu: toprgu@10007000 {
		compatible = "mediatek,toprgu";
		reg = <0 0x10007000 0 0x1000>;
		interrupts = <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>;
	};

	apxgpt@10008000 {
		compatible = "mediatek,apxgpt";
		reg = <0 0x10008000 0 0x1000>;
		interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
	};

	hacc@1000a000 {
		compatible = "mediatek,hacc";
		reg = <0 0x1000a000 0 0x1000>;
		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
	};

	apirq@1000b000 {
		compatible = "mediatek,apirq";
		reg = <0 0x1000b000 0 0x1000>;
		interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
	};

	apmixed: apmixed@1000c000 {
		compatible = "mediatek,apmixed", "syscon";
		reg = <0 0x1000c000 0 0xe00>;
		#clock-cells = <1>;
	};

	fhctl@1000ce00 {
		compatible = "mediatek,fhctl";
		reg = <0 0x1000ce00 0 0x200>;
	};

	pwrap: pwrap@10026000 {
		compatible = "mediatek,mt6885-pwrap";
		reg = <0 0x10026000 0 0x1000>;
		reg-names = "pwrap";
		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg_ao INFRACFG_AO_PMIC_CG_AP>,
			 <&infracfg_ao INFRACFG_AO_PMIC_CG_TMR>,
			 <&topckgen TOP_MUX_PWRAP_ULPOSC>,
			 <&topckgen TOP_OSC_D10>;
		clock-names = "spi", "wrap", "ulposc", "ulposc_osc";

		main_pmic: mt6359-pmic {
			compatible = "mediatek,mt6359-pmic";
			interrupt-parent = <&pio>;
			interrupts = <222 IRQ_TYPE_LEVEL_HIGH 222 0>;
			status = "okay";

			pmic_oc_debug: pmic-oc-debug {
				compatible = "mediatek,pmic-oc-debug";
			};
		};
	};

	pwraph: pwraphal@10026000 {
		compatible = "mediatek,pwraph";
		mediatek,pwrap-regmap = <&pwrap>;
	};

	pwmleds {
		compatible = "mediatek,pwm-leds";

		backlight {
			label = "lcd-backlight";
			pwms = <&disp_pwm 0 39385>;
			max-brightness = <255>;
			pwm-names = "lcd-backlight";
		};
	};

	pwrap_mpu@10026000 {
		compatible = "mediatek,pwrap_mpu";
		reg = <0 0x10026000 0 0x1000>;
	};

	devapc_ao_infra_peri@1000e000 {
		compatible = "mediatek,devapc_ao_infra_peri";
		reg = <0 0x1000e000 0 0x1000>;
	};

	sleep_reg_md@1000f000 {
		compatible = "mediatek,sleep_reg_md";
		reg = <0 0x1000f000 0 0x1000>;
	};

	keypad: kp@10010000 {
		compatible = "mediatek,kp";
		reg = <0 0x10010000 0 0x1000>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>;
	};

	topmisc@10011000 {
		compatible = "mediatek,topmisc";
		reg = <0 0x10011000 0 0x1000>;
	};

	dvfsrc: dvfsrc@10012000 {
		compatible = "mediatek,dvfsrc";
		reg = <0 0x10012000 0 0x1000>,
			<0 0x10006000 0 0x1000>;
		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
	};

	boot_dramboost: boot_dramboost {
		compatible = "mediatek,dvfsrc-boost";
		boost_opp = <0>;
	};

	mbist_ao@10013000 {
		compatible = "mediatek,mbist_ao";
		reg = <0 0x10013000 0 0x1000>;
	};

	apcldmain_ao@10014000 {
		compatible = "mediatek,apcldmain_ao";
		reg = <0 0x10014000 0 0x400>;
	};

	dpmaif:dpmaif@10014000 {
		compatible = "mediatek,dpmaif";
		reg = <0 0x10014000 0 0x1000>, /*AO_UL*/
			<0 0x1022D000 0 0x1000>, /*PD_UL*/
			<0 0x1022C000 0 0x1000>, /*PD_MD_MISC*/
			<0 0x1022E000 0 0x1000>; /*SRAM*/
		interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; /*209+32=241*/
		mediatek,dpmaif_capability = <6>;
		/*clocks = ; clock-names = ; set in mddriver node */
	};

	mddriver:mddriver {
		compatible = "mediatek,mddriver";
		mediatek,mdhif_type = <6>; /* bit0~3: CLDMA|CCIF|DPMAIF */
		mediatek,md_id = <0>;
		mediatek,cldma_capability = <6>;
		reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
			<0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
		interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
				/*MDWDT*/
			     <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
				/*CCIF0 194/226*/
			     <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
				/*CCIF0 195/227*/
		clocks = <&scpsys SCP_SYS_MD1>,
			<&infracfg_ao INFRACFG_AO_DPMAIF_MAIN_CG>,
			<&infracfg_ao INFRACFG_AO_CLDMA_BCLK_CK>,
			<&infracfg_ao INFRACFG_AO_CCIF_AP_CG>,
			<&infracfg_ao INFRACFG_AO_CCIF_MD_CG>,
			<&infracfg_ao INFRACFG_AO_CCIF1_AP_CG>,
			<&infracfg_ao INFRACFG_AO_CCIF1_MD_CG>,
			<&infracfg_ao INFRACFG_AO_CCIF2_AP_CG>,
			<&infracfg_ao INFRACFG_AO_CCIF2_MD_CG>,
			<&infracfg_ao INFRACFG_AO_CCIF4_MD_CG>,
			<&infracfg_ao INFRACFG_AO_CCIF5_MD_CG>;
		clock-names = "scp-sys-md1-main",
			"infra-dpmaif-clk",
			"infra-dpmaif-blk-clk",
			"infra-ccif-ap",
			"infra-ccif-md",
			"infra-ccif1-ap",
			"infra-ccif1-md",
			"infra-ccif2-ap",
			"infra-ccif2-md",
			"infra-ccif4-md",
			"infra-ccif5-md";
	};

	radio_md_cfg:radio_md_cfg {
		compatible = "mediatek,radio_md_cfg";
	};

	md_auxadc:md_auxadc {
		compatible = "mediatek,md_auxadc";
		io-channels = <&auxadc 2>;
		io-channel-names = "md-channel";
	};

	gpio_usage_mapping: gpio_usage_mapping {
		compatible = "mediatek,gpio_usage_mapping";
	};

	apcldmaout_ao@10014400 {
		compatible = "mediatek,apcldmaout_ao";
		reg = <0 0x10014400 0 0x400>;
	};

	apcldmamisc_ao@10014800 {
		compatible = "mediatek,apcldmamisc_ao";
		reg = <0 0x10014800 0 0x400>;
	};

	apcldmamisc_ao@10014c00 {
		compatible = "mediatek,apcldmamisc_ao";
		reg = <0 0x10014c00 0 0x400>;
	};

	devapc_mpu_ao@10015000 {
		compatible = "mediatek,devapc_mpu_ao";
		reg = <0 0x10015000 0 0x1000>;
	};

	aes_top0@10016000 {
		compatible = "mediatek,aes_top0";
		reg = <0 0x10016000 0 0x1000>;
	};

	sys_timer@10017000 {
		compatible = "mediatek,sys_timer";
		reg = <0 0x10017000 0 0x1000>;
		reg-names = "sys_timer_base";
		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen TOP_CLK13M>;
	};

	modem_temp_share@10018000 {
		compatible = "mediatek,modem_temp_share";
		reg = <0 0x10018000 0 0x1000>;
	};

	devapc_ao_md@10019000 {
		compatible = "mediatek,devapc_ao_md";
		reg = <0 0x10019000 0 0x1000>;
	};

	security_ao@1001a000 {
		compatible = "mediatek,security_ao";
		reg = <0 0x1001a000 0 0x1000>;
	};

	topckgen_ao@1001b000 {
		compatible = "mediatek,topckgen_ao";
		reg = <0 0x1001b000 0 0x1000>;
	};

	devapc_ao_mm@1001c000 {
		compatible = "mediatek,devapc_ao_mm";
		reg = <0 0x1001c000 0 0x1000>;
	};

	sleep_sram@1001e000 {
		compatible = "mediatek,sleep_sram";
		reg = <0 0x1001e000 0 0x4000>;
	};

	sleep_sram@1001f000 {
		compatible = "mediatek,sleep_sram";
		reg = <0 0x1001f000 0 0x1000>;
	};

	sleep_sram@10020000 {
		compatible = "mediatek,sleep_sram";
		reg = <0 0x10020000 0 0x1000>;
	};

	sleep_sram@10021000 {
		compatible = "mediatek,sleep_sram";
		reg = <0 0x10021000 0 0x1000>;
	};

	devapc_ao_infra_peri@10022000 {
		compatible = "mediatek,devapc_ao_infra_peri";
		reg = <0 0x10022000 0 0x1000>;
	};

	devapc_ao_infra_peri@10023000 {
		compatible = "mediatek,devapc_ao_infra_peri";
		reg = <0 0x10023000 0 0x1000>;
	};

	devapc_ao_infra_peri@10024000 {
		compatible = "mediatek,devapc_ao_infra_peri";
		reg = <0 0x10024000 0 0x1000>;
	};

	devapc_ao_infra_peri@10025000 {
		compatible = "mediatek,devapc_ao_infra_peri";
		reg = <0 0x10025000 0 0x1000>;
	};

	device_mpu_low@1021a000 {
		compatible = "mediatek,device_mpu_low";
		reg = <0 0x1021a000 0 0x1000>;
		prot-base = <0x0 0x40000000>;
		prot-size = <0x4 0x00000000>;
		page-size = <0x200000>;
		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
	};

	device_mpu_sub@1021b000 {
		compatible = "mediatek,device_mpu_sub";
		reg = <0 0x1021b000 0 0x1000>;
		prot-base = <0x0 0x40000000>;
		prot-size = <0x4 0x00000000>;
		page-size = <0x200000>;
		interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
	};

	bus_dbg@10208000 {
		compatible = "mediatek,bus_dbg-v2";
		reg = <0 0x10208000 0 0x1000>,
			  <0 0x10001000 0 0x1000>;
		mediatek,bus_dbg_con_offset = <0x2fc>;
		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
	};

	device_mpu_acp@1030d000 {
		compatible = "mediatek,device_mpu_acp";
		reg = <0 0x1030d000 0 0x1000>;
		prot-base = <0x0 0x40000000>;
		prot-size = <0x4 0x00000000>;
		page-size = <0x200000>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
	};

	sspm@10400000 {
		compatible = "mediatek,sspm";
		reg = <0 0x10400000 0 0x28000>,
			<0 0x10440000 0 0x10000>,
			<0 0x10450000 0 0x100>,
			<0 0x10451000 0 0x4>,
			<0 0x10451004 0 0x4>,
			<0 0x10460000 0 0x100>,
			<0 0x10461000 0 0x4>,
			<0 0x10461004 0 0x4>,
			<0 0x10470000 0 0x100>,
			<0 0x10471000 0 0x4>,
			<0 0x10471004 0 0x4>,
			<0 0x10480000 0 0x100>,
			<0 0x10481000 0 0x4>,
			<0 0x10481004 0 0x4>,
			<0 0x10490000 0 0x100>,
			<0 0x10491000 0 0x4>,
			<0 0x10491004 0 0x4>;

		reg-names = "sspm_base",
			"cfgreg",
			"mbox0_base",
			"mbox0_set",
			"mbox0_clr",
			"mbox1_base",
			"mbox1_set",
			"mbox1_clr",
			"mbox2_base",
			"mbox2_set",
			"mbox2_clr",
			"mbox3_base",
			"mbox3_set",
			"mbox3_clr",
			"mbox4_base",
			"mbox4_set",
			"mbox4_clr";

		interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "ipc",
			"mbox0",
			"mbox1",
			"mbox2",
			"mbox3",
			"mbox4";
	};

	/* ATF logger SW IRQ number 535 = 32 + 503 */
	atf_logger {
		compatible = "mediatek,atf_logger";
		interrupts = <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>;
	};

	/* Trustonic Mobicore SW IRQ number 536 = 32 + 504 */
	mobicore {
		compatible = "trustonic,mobicore";
		interrupts = <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>;
	};

	tee_sanity {
		compatible = "mediatek,tee_sanity";
		interrupts = <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>;
	};

	/* Microtrust SW IRQ number 506(538) ~ 511(543) */
	utos {
		compatible = "microtrust,utos";
		interrupts = <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 507 IRQ_TYPE_EDGE_RISING>;
	};

	utos_tester {
		compatible = "microtrust,tester-v1";
	};

	infraao_scp_0@10500000 {
		compatible = "mediatek,infraao_scp_0";
		reg = <0 0x10500000 0 0x2fb000>;
	};

	infraao_scp_1@107fb000 {
		compatible = "mediatek,infraao_scp_1";
		reg = <0 0x107fb000 0 0x1000>;
	};

	infraao_scp_2@107fc000 {
		compatible = "mediatek,infraao_scp_2";
		reg = <0 0x107fc000 0 0x1000>;
	};

	infraao_scp_3@107fd000 {
		compatible = "mediatek,infraao_scp_3";
		reg = <0 0x107fd000 0 0x1000>;
	};

	infraao_scp_4@107fe000 {
		compatible = "mediatek,infraao_scp_4";
		reg = <0 0x107fe000 0 0x1000>;
	};

	infraao_scp_5@107ff000 {
		compatible = "mediatek,infraao_scp_5";
		reg = <0 0x107ff000 0 0x1000>;
	};

	adsp_common: adsp_common@10800000 {
		compatible = "mediatek,adsp_common";
		reg = <0 0x1080b000 0 0x50>, /* CFG SECURE */
			<0 0x10806000 0 0x100>, /* MBOX0 base */
			<0 0x10806100 0 0x4>, /* MBOX0 set */
			<0 0x1080610c 0 0x4>, /* MBOX0 clr */
			<0 0x10806104 0 0x4>, /* MBOX0 send */
			<0 0x10806108 0 0x4>, /* MBOX0 recv */
			<0 0x1080b050 0 0x4>, /* MBOX0 init */
			<0 0x10807000 0 0x100>, /* MBOX1 base */
			<0 0x10807100 0 0x4>, /* MBOX1 set */
			<0 0x1080710c 0 0x4>, /* MBOX1 clr */
			<0 0x10807104 0 0x4>, /* MBOX1 send */
			<0 0x10807108 0 0x4>, /* MBOX1 recv */
			<0 0x1080b054 0 0x4>, /* MBOX1 init */
			<0 0x10808000 0 0x100>, /* MBOX2 base */
			<0 0x10808100 0 0x4>, /* MBOX2 set */
			<0 0x1080810c 0 0x4>, /* MBOX2 clr */
			<0 0x10808104 0 0x4>, /* MBOX2 send */
			<0 0x10808108 0 0x4>, /* MBOX2 recv */
			<0 0x1080b058 0 0x4>, /* MBOX2 init */
			<0 0x10809000 0 0x100>, /* MBOX3 base */
			<0 0x10809100 0 0x4>, /* MBOX3 set */
			<0 0x1080910c 0 0x4>, /* MBOX3 clr */
			<0 0x10809104 0 0x4>, /* MBOX3 send */
			<0 0x10809108 0 0x4>, /* MBOX3 recv */
			<0 0x1080b05c 0 0x4>, /* MBOX3 init */
			<0 0x10720180 0 0x4>; /* CLK cg */
		reg-names = "cfg_secure",
			"mbox0_base",
			"mbox0_set",
			"mbox0_clr",
			"mbox0_send",
			"mbox0_recv",
			"mbox0_init",
			"mbox1_base",
			"mbox1_set",
			"mbox1_clr",
			"mbox1_send",
			"mbox1_recv",
			"mbox1_init",
			"mbox2_base",
			"mbox2_set",
			"mbox2_clr",
			"mbox2_send",
			"mbox2_recv",
			"mbox2_init",
			"mbox3_base",
			"mbox3_set",
			"mbox3_clr",
			"mbox3_send",
			"mbox3_recv",
			"mbox3_init",
			"clock_cg";
		interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* MBOX0 */
			<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* MBOX1 */
			<GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, /* MBOX2 */
			<GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>; /* MBOX3 */
		interrupt-names = "mbox0",
			"mbox1",
			"mbox2",
			"mbox3";
		#mbox-cells = <1>;
		clocks = <&scpsys SCP_SYS_ADSP>, /* add ck cg later */
			<&topckgen TOP_MUX_ADSP>,
			<&clk26m>,
			<&topckgen TOP_ADSPPLL_CK>,
			<&topckgen TOP_MUX_SCP>;
		clock-names = "scp_sys_adsp", /* add ck cg later */
			"clk_top_adsp_sel",
			"clk_top_clk26m",
			"clk_top_adsppll",
			"clk_top_scp_sel";
		adsp-rsv-ipidma-a = <0x100000>;
		adsp-rsv-ipidma-b = <0x100000>;
		adsp-rsv-logger-a = <0x80000>;
		adsp-rsv-logger-b = <0x80000>;
		adsp-rsv-c2c = <0x40000>;
		adsp-rsv-dbg-dump-a = <0x80000>;
		adsp-rsv-dbg-dump-b = <0x80000>;
		adsp-rsv-core-dump-a = <0x400>;
		adsp-rsv-core-dump-b = <0x400>;
		adsp-rsv-audio = <0x5c0000>;
	};

	adsp_core0: adsp_core0@10820000 {
		compatible = "mediatek,adsp_core_0";
		reg = <0 0x10800000 0 0x6000>, /* CFG */
			<0 0x10840000 0 0x9000>, /* ITCM */
			<0 0x10820000 0 0x8000>; /* DTCM */
		system = <0 0x56000000 0 0x700000>;
		interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>;
		mboxes = <&adsp_common 0>, /*channel 0*/
			<&adsp_common 1>; /*channel 1*/
		feature_control_bits = <0x703FF>;
	};

	adsp_core1: adsp_core1@10850000 {
		compatible = "mediatek,adsp_core_1";
		reg = <0 0x10800000 0 0x6000>, /* CFG */
			<0 0x10870000 0 0x9000>, /* ITCM */
			<0 0x10850000 0 0x8000>; /* DTCM */
		system = <0 0x56700000 0 0x700000>;
		interrupts = <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>;
		mboxes = <&adsp_common 2>, /*channel 2*/
			<&adsp_common 3>; /*channel 3*/
		feature_control_bits = <0x8F00F>;
	};

	mcucfg: mcucfg@0c530000 {
		compatible = "mediatek,mcucfg";
		reg = <0 0x0c530000 0 0x10000>;
	};

#ifdef CONFIG_MTK_CONFIG_M4U
	m4u@10205000 {
		compatible = "mediatek,m4u";
		reg = <0 0x10205000 0 0x1000>;
	};
#endif
#ifdef CONFIG_MTK_IOMMU_V2
	iommu0: m4u@1411a000  {
		cell-index = <0>;
		compatible = "mediatek,iommu_v0";
		reg = <0 0x1411a000 0 0x1000>;
		mediatek,larbs = <&smi_larb0 &smi_larb1 &smi_larb5>,
				<&smi_larb7 &smi_larb11 &smi_larb14>,
				<&smi_larb17 &smi_larb19 &smi_larb20>;
		interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_SMI_INFRA>,
		       <&dispsys_config MM_SMI_IOMMU>,
		       <&scpsys SCP_SYS_DIS>;
		clock-names = "disp-infra-ck", "disp-iommu-ck", "power";
		#iommu-cells = <1>;
	};

	iommu1: m4u@1f027000{
		cell-index = <1>;
		compatible = "mediatek,iommu_v0";
		reg = <0 0x1f027000 0 0x1000>;
		mediatek,larbs = <&smi_larb2 &smi_larb3 &smi_larb4>,
				<&smi_larb8 &smi_larb9 &smi_larb13>,
				<&smi_larb16 &smi_larb18>;
		interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_SMI2>,
		       <&scpsys SCP_SYS_MDP>;
		clock-names = "mdp-smi2-ck", "power";
		#iommu-cells = <1>;
	};

	iommu2: m4u@19010000  {
		cell-index = <2>;
		compatible = "mediatek,iommu_v0";
		reg = <0 0x19010000 0 0x1000>;
		interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&apu_conn APU_CONN_IOMMU_0_CG>,
		       <&scpsys SCP_SYS_VPU>;
		clock-names = "clock", "power";
		#iommu-cells = <1>;
	};

	iommu3: m4u@19015000  {
		cell-index = <3>;
		compatible = "mediatek,iommu_v0";
		reg = <0 0x19015000 0 0x1000>;
		interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&apu_conn APU_CONN_IOMMU_1_CG>,
		       <&scpsys SCP_SYS_VPU>;
		clock-names = "clock", "power";
		#iommu-cells = <1>;
	};

	iommu0_bank1: m4u@1411b000 {
		cell-index = <0>;
		compatible = "mediatek,bank1_m4u0";
		reg = <0 0x1411b000 0 0x1000>;
		interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu0_bank2: m4u@1411c000 {
		cell-index = <0>;
		compatible = "mediatek,bank2_m4u0";
		reg = <0 0x1411c000 0 0x1000>;
		interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu0_bank3: m4u@1411d000 {
		cell-index = <0>;
		compatible = "mediatek,bank3_m4u0";
		reg = <0 0x1411d000 0 0x1000>;
		interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu1_bank1: m4u@1f028000 {
		cell-index = <1>;
		compatible = "mediatek,bank1_m4u1";
		reg = <0 0x1f028000 0 0x1000>;
		interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu1_bank2: m4u@1f029000 {
		cell-index = <1>;
		compatible = "mediatek,bank2_m4u1";
		reg = <0 0x1f029000 0 0x1000>;
		interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu1_bank3: m4u@1f02a000 {
		cell-index = <1>;
		compatible = "mediatek,bank3_m4u1";
		reg = <0 0x1f02a000 0 0x1000>;
		interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu2_bank1: m4u@19011000 {
		cell-index = <2>;
		compatible = "mediatek,bank1_m4u2";
		reg = <0 0x19011000 0 0x1000>;
		interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu2_bank2: m4u@19012000 {
		cell-index = <2>;
		compatible = "mediatek,bank2_m4u2";
		reg = <0 0x19012000 0 0x1000>;
		interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu2_bank3: m4u@19013000 {
		cell-index = <2>;
		compatible = "mediatek,bank3_m4u2";
		reg = <0 0x19013000 0 0x1000>;
		interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu3_bank1: m4u@19016000 {
		cell-index = <3>;
		compatible = "mediatek,bank1_m4u3";
		reg = <0 0x19016000 0 0x1000>;
		interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu3_bank2: m4u@19017000 {
		cell-index = <3>;
		compatible = "mediatek,bank2_m4u3";
		reg = <0 0x19017000 0 0x1000>;
		interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu3_bank3: m4u@19018000 {
		cell-index = <3>;
		compatible = "mediatek,bank3_m4u3";
		reg = <0 0x19018000 0 0x1000>;
		interrupts = <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu0_sec: m4u@1411e000 {
		cell-index = <0>;
		compatible = "mediatek,sec_m4u0";
		reg = <0 0x1411e000 0 0x1000>;
		interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu1_sec: m4u@1f02b000 {
		cell-index = <0>;
		compatible = "mediatek,sec_m4u1";
		reg = <0 0x1f02b000 0 0x1000>;
		interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu2_sec: m4u@19014000 {
		cell-index = <0>;
		compatible = "mediatek,sec_m4u2";
		reg = <0 0x19014000 0 0x1000>;
		interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu3_sec: m4u@19019000 {
		cell-index = <0>;
		compatible = "mediatek,sec_m4u3";
		reg = <0 0x19019000 0 0x1000>;
		interrupts = <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>;
	};

#endif
	devapc@10207000 {
		compatible = "mediatek,mt6885-devapc";
		reg = <0 0x10207000 0 0x1000>,
			<0 0x11021000 0 0x1000>,
			<0 0x11022000 0 0x1000>,
			<0 0x10030000 0 0x1000>,
			<0 0x1020e000 0 0x1000>,
			<0 0x10033000 0 0x1000>,
			<0 0x0010c000 0 0x1000>;
		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg_ao INFRACFG_AO_DEVICE_APC_CG>;
		clock-names = "devapc-infra-clock";
	};

	hwrng: hwrng {
		compatible = "mediatek,mt67xx-rng";
	};

	ap_ccif0@10209000 {
		compatible = "mediatek,ap_ccif0";
		reg = <0 0x10209000 0 0x1000>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
	};

	md_ccif0@1020a000 {
		compatible = "mediatek,md_ccif0";
		reg = <0 0x1020a000 0 0x1000>;
	};

	ap_ccif1@1020b000 {
		compatible = "mediatek,ap_ccif1";
		reg = <0 0x1020b000 0 0x1000>;
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
	};

	md_ccif1@1020c000 {
		compatible = "mediatek,md_ccif1";
		reg = <0 0x1020c000 0 0x1000>;
	};

	infra_mbist@1020d000 {
		compatible = "mediatek,infra_mbist";
		reg = <0 0x1020d000 0 0x1000>;
	};

	timer: timer {
		compatible = "arm,armv8-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
		clock-frequency = <13000000>;
	};

	infracfg@1020e000 {
		compatible = "mediatek,infracfg";
		reg = <0 0x1020e000 0 0x1000>;
	};

	trng@1020f000 {
		compatible = "mediatek,trng";
		reg = <0 0x1020f000 0 0x1000>;
		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
	};

	dxcc_sec@10210000 {
		compatible = "mediatek,dxcc_sec";
		reg = <0 0x10210000 0 0x1000>;
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
	};

	md2md_md1_ccif0@10211000 {
		compatible = "mediatek,md2md_md1_ccif0";
		reg = <0 0x10211000 0 0x1000>;
	};

	cq_dma@10212000 {
		compatible = "mediatek,mt-cqdma-v1";
		reg = <0 0x10212000 0 0x80>,
			<0 0x10212100 0 0x80>,
			<0 0x10212200 0 0x80>,
			<0 0x10212300 0 0x80>;
		interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
		nr_channel = <4>;
		clocks = <&infracfg_ao INFRACFG_AO_CQ_DMA_CG>;
		clock-names = "cqdma";
	};

	md2md_md2_ccif0@10213000 {
		compatible = "mediatek,md2md_md2_ccif0";
		reg = <0 0x10213000 0 0x1000>;
	};

	sramrom@10214000 {
		compatible = "mediatek,sramrom";
		reg = <0 0x10214000 0 0x1000>;
	};

	infra_bcrm@10215000 {
		compatible = "mediatek,infra_bcrm";
		reg = <0 0x10215000 0 0x1000>;
	};

	sub_infra_bcrm@10216000 {
		compatible = "mediatek,sub_infra_bcrm";
		reg = <0 0x10216000 0 0x1000>;
	};

	mipi_rx_ana_csi0@10217000 {
		compatible = "mediatek,mipi_rx_ana_csi0";
		reg = <0 0x10217000 0 0x1000>;
	};

	mipi_rx_ana_csi1@10218000 {
		compatible = "mediatek,mipi_rx_ana_csi1";
		reg = <0 0x10218000 0 0x1000>;
	};

	emicen: emicen@10219000 {
		compatible = "mediatek,mt6885-emicen",
			     "mediatek,common-emicen";
		reg = <0 0x10219000 0 0x1000>,
		      <0 0x1021d000 0 0x1000>;
		mediatek,emi-reg = <&emichn>;
	};

	emiisu {
		compatible = "mediatek,mt6885-emiisu",
			     "mediatek,common-emiisu";
		ctrl_intf = <0>;
	};

#ifdef CONFIG_MTK_CONFIG_M4U
	m4u@10220000 {
		compatible = "mediatek,m4u";
		reg = <0 0x10220000 0 0x1000>;
	};

	m4u@10221000 {
		compatible = "mediatek,m4u";
		reg = <0 0x10221000 0 0x1000>;
	};

	m4u@10222000 {
		compatible = "mediatek,m4u";
		reg = <0 0x10222000 0 0x1000>;
	};

	m4u@10223000 {
		compatible = "mediatek,m4u";
		reg = <0 0x10223000 0 0x1000>;
	};

	m4u@10224000 {
		compatible = "mediatek,m4u";
		reg = <0 0x10224000 0 0x1000>;
	};
#endif

	infra_device_mpu@1021a000 {
		compatible = "mediatek,infra_device_mpu";
		reg = <0 0x1021a000 0 0x1000>;
	};

	infra_device_mpu@1021b000 {
		compatible = "mediatek,infra_device_mpu";
		reg = <0 0x1021b000 0 0x1000>;
	};

	infracfg_mem@1021c000 {
		compatible = "mediatek,infracfg_mem";
		reg = <0 0x1021c000 0 0x1000>;
	};

	infra_device_mpu@1021d000 {
		compatible = "mediatek,infra_device_mpu";
		reg = <0 0x1021d000 0 0x1000>;
	};

	infra_device_mpu@1021e000 {
		compatible = "mediatek,infra_device_mpu";
		reg = <0 0x1021e000 0 0x1000>;
	};

	apcldmain@1021f000 {
		compatible = "mediatek,apcldmain";
		reg = <0 0x1021f000 0 0x1000>;
	};

	apcldmaout@1021b400 {
		compatible = "mediatek,apcldmaout";
		reg = <0 0x1021b400 0 0x400>;
	};

	apcldmamisc@1021b800 {
		compatible = "mediatek,apcldmamisc";
		reg = <0 0x1021b800 0 0x400>;
	};

	apcldmamisc@1021bc00 {
		compatible = "mediatek,apcldmamisc";
		reg = <0 0x1021bc00 0 0x400>;
	};

	mdcldmain@1021c000 {
		compatible = "mediatek,mdcldmain";
		reg = <0 0x1021c000 0 0x400>;
	};

	infra_md@1021d000 {
		compatible = "mediatek,infra_md";
		reg = <0 0x1021d000 0 0x1000>;
	};

	bpi_bsi_slv0@1021e000 {
		compatible = "mediatek,bpi_bsi_slv0";
		reg = <0 0x1021e000 0 0x1000>;
	};

	bpi_bsi_slv1@1021f000 {
		compatible = "mediatek,bpi_bsi_slv1";
		reg = <0 0x1021f000 0 0x1000>;
	};

	bpi_bsi_slv2@10225000 {
		compatible = "mediatek,bpi_bsi_slv2";
		reg = <0 0x10225000 0 0x1000>;
	};

	infra_device_mpu@10225000 {
		compatible = "mediatek,infra_device_mpu";
		reg = <0 0x10225000 0 0x1000>;
	};

	emimpu@10226000 {
		compatible = "mediatek,mt6885-emimpu",
			     "mediatek,common-emimpu";
		reg = <0 0x10226000 0 0x1000>,
		      <0 0x10225000 0 0x1000>;
		mediatek,emi-reg = <&emicen>;
		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
		region_cnt = <32>;
		domain_cnt = <16>;
		addr_align = <16>;
		ap_region = <31>;
		ap_apc = <0 5 5 5 0 0 6 5>,
			 <0 0 5 0 1 1 5 5>;
		dump = <0x1f0 0x1f8 0x1fc>;
		clear = <0x160 0xffffffff 16>,
			<0x200 0x00000003 16>,
			<0x1f0 0x80000000 1>;
		clear_md = <0x1fc 0x80000000 1>;
		ctrl_intf = <1>;
		slverr = <0>;
	};

	upower: upower {
		compatible = "mediatek,mt6893-upower";
	};

	dvfsp@10227000 {
		compatible = "mediatek,dvfsp";
		reg = <0 0x10227000 0 0x1000>;
	};

	dvfsp: dvfsp@0011bc00 {
		compatible = "mediatek,mt6885-dvfsp";
		reg = <0 0x0011bc00 0 0x1400>,
		      <0 0x0011bc00 0 0x1400>;
		state = <1>;
		imax_state = <2>;
		change_flag = <0>;
		proc1-supply = <&mt6315_6_vbuck1>;
		proc2-supply = <&mt6315_6_vbuck3>;
		little-rise-time = <1000>;
		little-down-time = <750>;
		big-rise-time = <1000>;
		big-down-time = <750>;
	};

	mt_cpufreq: mt_cpufreq {
		compatible = "mediatek,mt-cpufreq";
	};

	cpumssv: cpumssv {
		compatible = "mediatek,cpumssv";
		state = <0>;
	};

	gce_clock: gce_clock@10228000 {
		compatible = "mediatek,gce_clock", "syscon";
		reg = <0 0x10228000 0 0x1000>;
		#clock-cells = <1>;
	};

	gce_mbox: gce_mbox@10228000 {
		compatible = "mediatek,mt6885-gce";
		reg = <0 0x10228000 0 0x4000>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <3>;
		#gce-event-cells = <1>;
		#gce-subsys-cells = <2>;
		default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
			/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
			/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
		clock-names = "gce", "gce-timer";
		clocks = <&infracfg_ao INFRACFG_AO_GCE_CG>,
			<&infracfg_ao INFRACFG_AO_GCE_26M>;
	};

	gce_mbox_sec: gce_mbox_sec@10228000 {
		compatible = "mediatek,mailbox-gce-sec";
		reg = <0 0x10228000 0 0x4000>;
		#mbox-cells = <3>;
		mboxes = <&gce_mbox 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>;
		clock-names = "gce";
		clocks = <&infracfg_ao INFRACFG_AO_GCE_CG>;
	};

	infra_dpmaif@1022c000 {
		compatible = "mediatek,infra_dpmaif";
		reg = <0 0x1022c000 0 0x1000>;
	};

	infra_dpmaif@1022d000 {
		compatible = "mediatek,infra_dpmaif";
		reg = <0 0x1022d000 0 0x1000>;
	};

	infra_dpmaif@1022e000 {
		compatible = "mediatek,infra_dpmaif";
		reg = <0 0x1022e000 0 0x1000>;
	};

	infra_dpmaif@1022f000 {
		compatible = "mediatek,infra_dpmaif";
		reg = <0 0x1022f000 0 0x1000>;
	};

	dramc@10230000 {
		compatible = "mediatek,mt6885-dramc",
			     "mediatek,common-dramc";
		reg = <0 0x10230000 0 0x2000>, /* DRAMC AO CHA */
			<0 0x10240000 0 0x2000>, /* DRAMC AO CHB */
			<0 0x10250000 0 0x2000>, /* DRAMC AO CHC */
			<0 0x10260000 0 0x2000>, /* DRAMC AO CHD */
			<0 0x10234000 0 0x1000>, /* DRAMC NAO CHA */
			<0 0x10244000 0 0x1000>, /* DRAMC NAO CHB */
			<0 0x10254000 0 0x1000>, /* DRAMC NAO CHC */
			<0 0x10264000 0 0x1000>, /* DRAMC NAO CHD */
			<0 0x10238000 0 0x2000>, /* DDRPHY AO CHA */
			<0 0x10248000 0 0x2000>, /* DDRPHY AO CHB */
			<0 0x10258000 0 0x2000>, /* DDRPHY AO CHC */
			<0 0x10268000 0 0x2000>, /* DDRPHY AO CHD */
			<0 0x10236000 0 0x1000>, /* DDRPHY NAO CHA */
			<0 0x10246000 0 0x1000>, /* DDRPHY NAO CHB */
			<0 0x10256000 0 0x1000>, /* DDRPHY NAO CHC */
			<0 0x10266000 0 0x1000>, /* DDRPHY NAO CHD */
			<0 0x10006000 0 0x1000>; /* SLEEP BASE */
		mr4_version = <1>;
		mr4_rg = <0x0090 0x0000ffff 0>;
		fmeter_version = <1>;
		crystal_freq = <52>;
		pll_id = <0x050c 0x00000100 8>;
		shu_lv = <0x050c 0x00030000 16>;
		shu_of = <0x700>;
		sdmpcw = <0x0704 0xffff0000 16>,
			 <0x0724 0xffff0000 16>;
		prediv = <0x0708 0x000c0000 18>,
			 <0x0728 0x000c0000 18>;
		posdiv = <0x0708 0x00000007 0>,
			 <0x0728 0x00000007 0>;
		ckdiv4 = <0x0874 0x00000004 2>,
			 <0x0874 0x00000004 2>;
		pll_md = <0x0744 0x00000100 8>,
			 <0x0744 0x00000100 8>;
		cldiv2 = <0x08b4 0x00000002 1>,
			 <0x08b4 0x00000002 1>;
		fbksel = <0x070c 0x00000040 6>,
			 <0x070c 0x00000040 6>;
		dqsopen = <0x0870 0x00100000 20>,
			 <0x0870 0x00100000 20>;
		dqopen = <0x0870 0x00200000 21>,
			 <0x0870 0x00200000 21>;
	};

	dramc_ch0_top0@10230000 {
		compatible = "mediatek,dramc_ch0_top0";
		reg = <0 0x10230000 0 0x2000>;
	};

	dramc_ch0_top1@10232000 {
		compatible = "mediatek,dramc_ch0_top1";
		reg = <0 0x10232000 0 0x2000>;
	};

	dramc_ch0_top2@10234000 {
		compatible = "mediatek,dramc_ch0_top2";
		reg = <0 0x10234000 0 0x1000>;
	};

	emichn: emichn@10235000 {
		compatible = "mediatek,mt6885-emichn",
			     "mediatek,common-emichn";
		reg = <0 0x10235000 0 0x1000>,
		      <0 0x10245000 0 0x1000>,
		      <0 0x10255000 0 0x1000>,
		      <0 0x10265000 0 0x1000>;
	};

	dramc_ch0_rsv@10236000 {
		compatible = "mediatek,dramc_ch0_rsv";
		reg = <0 0x10236000 0 0x2000>;
	};

	dramc_ch0_rsv@10238000 {
		compatible = "mediatek,dramc_ch0_rsv";
		reg = <0 0x10238000 0 0x2000>;
	};

	dramc_ch0_rsv@1023a000 {
		compatible = "mediatek,dramc_ch0_rsv";
		reg = <0 0x1023a000 0 0x2000>;
	};

	ap_ccif2@1023c000 {
		compatible = "mediatek,ap_ccif2";
		reg = <0 0x1023c000 0 0x1000>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
	};

	apdma: dma-controller@11000a80 {
		compatible = "mediatek,mt6577-uart-dma";
		reg = <0 0x11000a80 0 0x80>,
		      <0 0x11000b00 0 0x80>,
		      <0 0x11000b80 0 0x80>,
		      <0 0x11000c00 0 0x80>;
		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
		clock-names = "apdma";
		#dma-cells = <1>;
		dma-bits = <34>;
	};

	apuart0: serial@11002000 {
		compatible = "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x1000>;
		interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk26m>, <&infracfg_ao INFRACFG_AO_UART0_CG>;
		clock-names = "baud", "bus";
		dmas = <&apdma 0
				&apdma 1>;
		dma-names = "tx", "rx";
	};

	apuart1: serial@11003000 {
		compatible = "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x1000>;
		interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clk26m>, <&infracfg_ao INFRACFG_AO_UART1_CG>;
		clock-names = "baud", "bus";
		dmas = <&apdma 2
				&apdma 3>;
		dma-names = "tx", "rx";
	};

	usb0:usb3@11200000 {
		compatible = "mediatek,usb3";
		reg = <0 0x11200000 0 0x10000>,
			<0 0x11203e00 0 0x100>,
			<0 0x11e40000 0 0x10000>;
		reg-names = "ssusb_base",
				"ssusb_ippc",
				"ssusb_sif2";
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "musb-hdrc";
		debug_level = <6>;
		fpga_i2c_physical_base = <0x11d01100>;
	};

	usbphy0:usbphy {
		compatible = "usb-nop-xceiv";
	};

	usb3_phy {
		compatible = "mediatek,usb3_phy";
		reg = <0 0x11e40000 0 0x10000>;
		reg-names = "sif_base";
		clocks = <&infracfg_ao INFRACFG_AO_SSUSB_CG>,
			 <&infracfg_ao INFRACFG_AO_SSUSB_XHCI_CG>;
		clock-names = "ssusb_clk", "sys_ck";
		#phy-cells = <1>;
	};

	mtu3_0:mtu3_0@11200000 {
		compatible = "mediatek,mt6885-mtu3";
		reg = <0 0x11201000 0 0x3000>,
		      <0 0x11203e00 0 0x100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "ssusb_mac";
		clocks = <&infracfg_ao INFRACFG_AO_SSUSB_CG>,
			   <&infracfg_ao INFRACFG_AO_SSUSB_XHCI_CG>;
		clock-names = "sys_ck", "rel_clk";
		phy-cells = <1>;
		phys = <&usb0phy 0>;
		phy-names = "port0_phy";
		extcon = <&extcon_usb>;
		dr_mode = "otg";
	};

	xhci0:usb_xhci@11200000 {
		compatible = "mediatek,mt67xx-xhci";
		reg = <0 0x11200000 0 0x1000>;
		reg-names = "mac";
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "xhci";
		clocks = <&infracfg_ao INFRACFG_AO_SSUSB_XHCI_CG>;
		clock-names = "sys_ck";
		phys = <&usb0phy 0>;
		phy-names = "port0_phy";
	};

	usb0phy:usb0phy@11e40000 {
		compatible = "mediatek,mt6885-phy";
		reg = <0 0x11e40000 0 0x10000>,
			  <0 0x11203e00 0 0x100>;
		reg-names = "sif_base", "ippc";
		#phy-cells = <1>;
	};

	extcon_usb: extcon_usb {
		compatible = "mediatek,extcon-usb";
	};

	usb_boost_manager {
		compatible = "mediatek,usb_boost";
		boost_period = <30>;
	};

	mmc0: mmc@11230000 {
	      compatible = "mediatek,mt6885-mmc";
	      reg = <0 0x11230000 0 0x1000>;
	      interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
	      clocks = <&clk12m>,
		       <&clk12m>,
		       <&clk12m>;
	      clock-names = "source", "hclk", "source_cg";
	      status = "disabled";
	};

	mmc_fixed_3v3: fixedregulator@0 {
		compatible = "regulator-fixed";
		status = "disabled";
	};

	mmc_fixed_1v8_io: fixedregulator@1 {
		compatible = "regulator-fixed";
		status = "disabled";
	};

	ufshci:ufshci@11270000 {
		compatible = "mediatek,ufshci";
		reg = <0 0x11270000 0 0x2300>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;

		#ifndef CONFIG_FPGA_EARLY_PORTING
		clocks =
			<&infracfg_ao INFRACFG_AO_UFS_CG>,
			<&infracfg_ao INFRACFG_AO_UNIPRO_SYSCLK_CG>,
			<&infracfg_ao INFRACFG_AO_UFS_MP_SAP_BCLK_CG>,
			<&infracfg_ao INFRACFG_AO_AES_UFSFDE_CG>,
			<&topckgen TOP_MUX_AES_UFSFDE>,
			<&topckgen TOP_UNIVPLL_D6>,
			<&topckgen TOP_MAINPLL_D4>;
		clock-names =
			"ufs-clk",
			"ufs-unipro-clk",
			"ufs-mp-clk",
			"ufs-crypto-clk",
			"ufs-vendor-crypto-clk-mux",
			"ufs-vendor-crypto-normal-parent-clk",
			"ufs-vendor-crypto-perf-parent-clk";
		freq-table-hz =
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>;
		#endif

		/* Regulators */
		/* In MT67xx, only VCC is available to be controlled by UFS */
		/* driver */
		/* VCCQ2:  Provided by external LDO. SW control is not */
		/* necessary */
		/* VCCQ: Not supported by current UFS devices */
		#ifndef CONFIG_FPGA_EARLY_PORTING
		vcc-supply = <&mt_pmic_vemc_ldo_reg>;
		vcc-fixed-regulator;
		#endif

		/* Number of lanes available per direction - either 1 or 2 */
		lanes-per-direction = <2>;

		/* Auto-Hibern8 Timer. Unit: ms	(0 means disabled) */
		mediatek,auto-hibern8-timer = <10>;

		/* System Suspend Level */
		mediatek,spm-level = <3>;

		/* Runtime Suspend Configuration */
		/* 1. Runtime PM on/off (on: 1, off: 0) */
		mediatek,rpm-enable = <1>;

		/* 2. Auto Suspend Delay. Unit: ms */
		mediatek,rpm-autosuspend-delay = <2000>;

		/* 3. Runtime Suspend Level */
		mediatek,rpm-level = <3>;

		/* Performance Mode */
		mediatek,perf-crypto-vcore = <2>;
	};

	ufs_mphy@11fa0000 {
		compatible = "mediatek,ufs_mphy";
		reg = <0 0x11fa0000 0 0xc000>;
	};

	md_ccif2@1023d000 {
		compatible = "mediatek,md_ccif2";
		reg = <0 0x1023d000 0 0x1000>;
	};

	ap_ccif3@1023e000 {
		compatible = "mediatek,ap_ccif3";
		reg = <0 0x1023e000 0 0x1000>;
		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
	};

	md_ccif3@1023f000 {
		compatible = "mediatek,md_ccif3";
		reg = <0 0x1023f000 0 0x1000>;
	};

	dramc_ch1_top0@10240000 {
		compatible = "mediatek,dramc_ch1_top0";
		reg = <0 0x10240000 0 0x2000>;
	};

	dramc_ch1_top1@10242000 {
		compatible = "mediatek,dramc_ch1_top1";
		reg = <0 0x10242000 0 0x2000>;
	};

	dramc_ch1_top2@10244000 {
		compatible = "mediatek,dramc_ch1_top2";
		reg = <0 0x10244000 0 0x1000>;
	};

	dramc_ch1_rsv@10246000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x10246000 0 0x2000>;
	};

	dramc_ch1_rsv@10248000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x10248000 0 0x2000>;
	};

	dramc_ch1_rsv@1024a000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x1024a000 0 0x2000>;
	};

	ap_ccif4@1024c000 {
		compatible = "mediatek,ap_ccif4";
		reg = <0 0x1024c000 0 0x1000>;
	};

	md_ccif4@1024d000 {
		compatible = "mediatek,md_ccif4";
		reg = <0 0x1024d000 0 0x1000>;
	};

	md_ccif4@1024e000 {
		compatible = "mediatek,md_ccif4";
		reg = <0 0x1024e000 0 0x1000>;
	};

#ifdef CONFIG_MTK_CONFIG_M4U
	m4u@1024f000 {
		compatible = "mediatek,m4u";
		reg = <0 0x1024f000 0 0x1000>;
	};

	m4u@10250000 {
		compatible = "mediatek,m4u";
		reg = <0 0x10250000 0 0x1000>;
	};

	m4u@10251000 {
		compatible = "mediatek,m4u";
		reg = <0 0x10251000 0 0x1000>;
	};

	m4u@10252000 {
		compatible = "mediatek,m4u";
		reg = <0 0x10252000 0 0x1000>;
	};

	m4u@10253000 {
		compatible = "mediatek,m4u";
		reg = <0 0x10253000 0 0x1000>;
	};
#endif
	mm_vpu_m0_sub_common@10254000 {
		compatible = "mediatek,mm_vpu_m0_sub_common";
		reg = <0 0x10254000 0 0x1000>;
	};

	mm_vpu_m1_sub_common@10255000 {
		compatible = "mediatek,mm_vpu_m1_sub_common";
		reg = <0 0x10255000 0 0x1000>;
	};

	axi2acp_sub_common@10256000 {
		compatible = "mediatek,axi2acp_sub_common";
		reg = <0 0x10256000 0 0x1000>;
	};

	dramc_ch1_top0@10250000 {
		compatible = "mediatek,dramc_ch1_top0";
		reg = <0 0x10250000 0 0x2000>;
	};

	dramc_ch1_top1@10252000 {
		compatible = "mediatek,dramc_ch1_top1";
		reg = <0 0x10252000 0 0x2000>;
	};

	dramc_ch1_top2@10254000 {
		compatible = "mediatek,dramc_ch1_top2";
		reg = <0 0x10254000 0 0x1000>;
	};

	dramc_ch1_rsv@10256000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x10256000 0 0x2000>;
	};

	dramc_ch1_rsv@10258000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x10258000 0 0x2000>;
	};

	dramc_ch1_rsv@1025a000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x1025a000 0 0x2000>;
	};

	ap_ccif5@1025c000 {
		compatible = "mediatek,ap_ccif5";
		reg = <0 0x1025c000 0 0x1000>;
	};

	md_ccif5@1025d000 {
		compatible = "mediatek,md_ccif5";
		reg = <0 0x1025d000 0 0x1000>;
	};

	mm_vpu_m0_sub_common@1025e000 {
		compatible = "mediatek,mm_vpu_m0_sub_common";
		reg = <0 0x1025e000 0 0x1000>;
	};

	mm_vpu_m1_sub_common@1025f000 {
		compatible = "mediatek,mm_vpu_m1_sub_common";
		reg = <0 0x1025f000 0 0x1000>;
	};

	dramc_ch1_top0@10260000 {
		compatible = "mediatek,dramc_ch1_top0";
		reg = <0 0x10260000 0 0x2000>;
	};

	dramc_ch1_top1@10262000 {
		compatible = "mediatek,dramc_ch1_top1";
		reg = <0 0x10262000 0 0x2000>;
	};

	dramc_ch1_top2@10264000 {
		compatible = "mediatek,dramc_ch1_top2";
		reg = <0 0x10264000 0 0x1000>;
	};

	dramc_ch1_rsv@10266000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x10266000 0 0x2000>;
	};

	dramc_ch1_rsv@10268000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x10268000 0 0x2000>;
	};

	dramc_ch1_rsv@1026a000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x1026a000 0 0x2000>;
	};

	mm_vpu_m0_sub_common@10309000 {
		compatible = "mediatek,mm_vpu_m0_sub_common";
		reg = <0 0x10309000 0 0x1000>;
	};

	mm_vpu_m1_sub_common@1030a000 {
		compatible = "mediatek,mm_vpu_m1_sub_common";
		reg = <0 0x1030a000 0 0x1000>;
	};

	mm_vpu_m1_sub_common@1030b000 {
		compatible = "mediatek,mm_vpu_m1_sub_common";
		reg = <0 0x1030b000 0 0x1000>;
	};

	mm_vpu_m1_sub_common@1030c000 {
		compatible = "mediatek,mm_vpu_m1_sub_common";
		reg = <0 0x1030c000 0 0x1000>;
	};

	mm_vpu_m1_sub_common@1030d000 {
		compatible = "mediatek,mm_vpu_m1_sub_common";
		reg = <0 0x1030d000 0 0x1000>;
	};

	mdp_gce_clock: mdp_gce_clock@10318000 {
		compatible = "mediatek,mdp_gce_clock", "syscon";
		reg = <0 0x10318000 0 0x1000>;
		#clock-cells = <1>;
	};

	gce_mbox_m: gce_mbox_m@10318000 {
		compatible = "mediatek,mailbox-gce", "mediatek,mt6885-gce";
		reg = <0 0x10318000 0 0x4000>;
		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
		#mbox-cells = <3>;
		#gce-event-cells = <1>;
		#gce-subsys-cells = <2>;
		default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
			/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
			/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
			/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
		clock-names = "gce", "gce-timer";
		clocks = <&infracfg_ao INFRACFG_AO_GCE2_CG>,
			<&infracfg_ao INFRACFG_AO_GCE_26M>;
	};

	gce_mbox_m_sec: gce_mbox_m_sec@10318000 {
		compatible = "mediatek,mailbox-gce-sec";
		reg = <0 0x10318000 0 0x4000>;
		#mbox-cells = <3>;
		mboxes = <&gce_mbox_m 15 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>;
		clock-names = "gce";
		clocks = <&infracfg_ao INFRACFG_AO_GCE2_CG>;
	};

	cmdq-test {
		compatible = "mediatek,cmdq-test";
		mediatek,gce = <&gce_mbox>;
		mmsys_config = <&mdpsys_config>;
		mediatek,gce-subsys = <99>, <SUBSYS_1400XXXX>;
		mboxes = <&gce_mbox 23 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox_m 23 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>,
			<&gce_mbox_sec 11 0 CMDQ_THR_PRIO_1>;
		token_user0 = /bits/ 16 <CMDQ_SYNC_TOKEN_USER_0>;
		token_gpr_set4 = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>;
	};

	cmdq-bw-mon {
		compatible = "mediatek,cmdq-bw-mon";
		mboxes = <&gce_mbox 22 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_1>;
		smi_mon = <&smi_common>, <&mdp_smi_common>;
		bw_mon_gpr = /bits/ 8 <GCE_GPR_R13>;
	};

	gce@10318000 {
		compatible = "mediatek,gce";
		reg = <0 0x10318000 0 0x4000>;
		mmsys_config = <&mdpsys_config>;
		thread_count = <24>;
		mediatek,mailbox-gce = <&gce_mbox>;
		mboxes = <&gce_mbox 7 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
			<&gce_mbox_m 12 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox_m 13 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox_m 14 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox_m 21 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox_m 22 0 CMDQ_THR_PRIO_1>;
		disp_mutex_reg = <0x14120000 0x1000>;
		g3d_config_base = <0x13000000 0 0xffff0000>;
		mmsys_config_base = <0x14000000 1 0xffff0000>;
		disp_dither_base = <0x14010000 2 0xffff0000>;
		mm_na_base = <0x14020000 3 0xffff0000>;
		imgsys_base = <0x15020000 4 0xffff0000>;
		vdec_gcon_base = <0x18800000 5 0xffff0000>;
		venc_gcon_base = <0x18810000 6 0xffff0000>;
		conn_peri_base = <0x18820000 7 0xffff0000>;
		topckgen_base = <0x18830000 8 0xffff0000>;
		kp_base = <0x18840000 9 0xffff0000>;
		scp_sram_base = <0x10000000 10 0xffff0000>;
		infra_na3_base = <0x10010000 11 0xffff0000>;
		infra_na4_base = <0x10020000 12 0xffff0000>;
		scp_base = <0x10030000 13 0xffff0000>;
		mcucfg_base = <0x10040000 14 0xffff0000>;
		gcpu_base = <0x10050000 15 0xffff0000>;
		usb0_base = <0x10200000 16 0xffff0000>;
		usb_sif_base = <0x10280000 17 0xffff0000>;
		audio_base = <0x17000000 18 0xffff0000>;
		vdec_base = <0x17010000 19 0xffff0000>;
		msdc2_base = <0x17020000 20 0xffff0000>;
		vdec1_base = <0x17030000 21 0xffff0000>;
		msdc3_base = <0x18000000 22 0xffff0000>;
		ap_dma_base = <0x18010000 23 0xffff0000>;
		gce_base = <0x18020000 24 0xffff0000>;
		vdec2_base = <0x18040000 25 0xffff0000>;
		vdec3_base = <0x18050000 26 0xffff0000>;
		camsys_base = <0x18080000 27 0xffff0000>;
		camsys1_base = <0x180a0000 28 0xffff0000>;
		camsys2_base = <0x180b0000 29 0xffff0000>;
		dip2_cq_thread0_frame_done = <1>;
		dip2_cq_thread1_frame_done = <2>;
		dip2_cq_thread2_frame_done = <3>;
		dip2_cq_thread3_frame_done = <4>;
		dip2_cq_thread4_frame_done = <5>;
		dip2_cq_thread5_frame_done = <6>;
		dip2_cq_thread6_frame_done = <7>;
		dip2_cq_thread7_frame_done = <8>;
		dip2_cq_thread8_frame_done = <9>;
		dip2_cq_thread9_frame_done = <10>;
		dip2_cq_thread10_frame_done = <11>;
		dip2_cq_thread11_frame_done = <12>;
		dip2_cq_thread12_frame_done = <13>;
		dip2_cq_thread13_frame_done = <14>;
		dip2_cq_thread14_frame_done = <15>;
		dip2_cq_thread15_frame_done = <16>;
		dip2_cq_thread16_frame_done = <17>;
		dip2_cq_thread17_frame_done = <18>;
		dip2_cq_thread18_frame_done = <19>;
		dip2_cq_thread19_frame_done = <20>;
		dip2_cq_thread20_frame_done = <21>;
		dip2_cq_thread21_frame_done = <22>;
		dip2_cq_thread22_frame_done = <23>;
		dip2_cq_thread23_frame_done = <24>;
		dip_cq_thread0_frame_done = <33>;
		dip_cq_thread1_frame_done = <34>;
		dip_cq_thread2_frame_done = <35>;
		dip_cq_thread3_frame_done = <36>;
		dip_cq_thread4_frame_done = <37>;
		dip_cq_thread5_frame_done = <38>;
		dip_cq_thread6_frame_done = <39>;
		dip_cq_thread7_frame_done = <40>;
		dip_cq_thread8_frame_done = <41>;
		dip_cq_thread9_frame_done = <42>;
		dip_cq_thread10_frame_done = <43>;
		dip_cq_thread11_frame_done = <44>;
		dip_cq_thread12_frame_done = <45>;
		dip_cq_thread13_frame_done = <46>;
		dip_cq_thread14_frame_done = <47>;
		dip_cq_thread15_frame_done = <48>;
		dip_cq_thread16_frame_done = <49>;
		dip_cq_thread17_frame_done = <50>;
		dip_cq_thread18_frame_done = <51>;
		dip_cq_thread19_frame_done = <52>;
		dip_cq_thread20_frame_done = <53>;
		dip_cq_thread21_frame_done = <54>;
		dip_cq_thread22_frame_done = <55>;
		dip_cq_thread23_frame_done = <56>;
		ipe_event_tx_frame_done_0 = <129>;
		ipe_event_tx_frame_done_1 = <130>;
		ipe_event_tx_frame_done_2 = <131>;
		ipe_event_tx_frame_done_3 = <132>;
		ipe_event_tx_frame_done_4 = <133>;
		isp_frame_done_a = <193>;
		isp_frame_done_b = <194>;
		isp_frame_done_c = <195>;
		camsv_0_pass1_done = <196>;
		camsv_0_2_pass1_done = <197>;
		camsv_1_pass1_done = <198>;
		camsv_2_pass1_done = <199>;
		camsv_3_pass1_done = <200>;
		mraw_0_pass1_done = <201>;
		mraw_1_pass1_done = <202>;
		seninf_0_fifo_full = <203>;
		seninf_1_fifo_full = <204>;
		seninf_2_fifo_full = <205>;
		seninf_3_fifo_full = <206>;
		seninf_4_fifo_full = <207>;
		seninf_5_fifo_full = <208>;
		seninf_6_fifo_full = <209>;
		seninf_7_fifo_full = <210>;
		seninf_cam8_fifo_full = <211>;
		seninf_cam9_fifo_full = <212>;
		seninf_cam10_fifo_full = <213>;
		seninf_cam11_fifo_full = <214>;
		seninf_cam12_fifo_full = <215>;
		tg_ovrun_a_int_dly = <216>;
		tg_graberr_a_int_dly = <217>;
		tg_ovrun_b_int_dly = <218>;
		tg_graberr_b_int_dly = <219>;
		tg_ovrun_c_int = <220>;
		tg_graberr_c_int = <221>;
		tg_ovrun_m0_int = <222>;
		dma_r1_error_m0_int = <223>;
		mdp_rdma0_sof = <256>;
		mdp_rdma1_sof = <257>;
		mdp_rdma2_sof = <258>;
		mdp_rdma3_sof = <259>;
		mdp_fg0_sof = <260>;
		mdp_fg1_sof = <261>;
		mdp_aal_sof = <262>;
		mdp_aal1_sof = <263>;
		mdp_aal2_sof = <264>;
		mdp_aal3_sof = <265>;
		mdp_hdr0_sof = <266>;
		mdp_hdr1_sof = <267>;
		mdp_rsz0_sof = <268>;
		mdp_rsz1_sof = <269>;
		mdp_rsz2_sof = <270>;
		mdp_rsz3_sof = <271>;
		mdp_wrot0_sof = <272>;
		mdp_wrot1_sof = <273>;
		mdp_wrot2_sof = <274>;
		mdp_wrot3_sof = <275>;
		mdp_tdshp_sof = <276>;
		mdp_tdshp1_sof = <277>;
		mdp_tdshp2_sof = <278>;
		mdp_tdshp3_sof = <279>;
		mdp_tcc0_sof = <280>;
		mdp_tcc1_sof = <281>;
		mdp_tcc2_sof = <282>;
		mdp_tcc3_sof = <283>;
		img_dl_relay_sof = <284>;
		img_dl_relay1_sof = <285>;
		img_dl_relay2_sof = <286>;
		img_dl_relay3_sof = <287>;
		mdp_wrot3_write_frame_done = <288>;
		mdp_wrot2_write_frame_done = <289>;
		mdp_wrot1_write_frame_done = <290>;
		mdp_wrot0_write_frame_done = <291>;
		mdp_tdshp3_frame_done = <292>;
		mdp_tdshp2_frame_done = <293>;
		mdp_tdshp1_frame_done = <294>;
		mdp_tdshp0_frame_done = <295>;
		mdp_tcc3_frame_done = <296>;
		mdp_tcc2_frame_done = <297>;
		mdp_tcc1_frame_done = <298>;
		mdp_tcc0_frame_done = <299>;
		mdp_rsz3_frame_done = <300>;
		mdp_rsz2_frame_done = <301>;
		mdp_rsz1_frame_done = <302>;
		mdp_rsz0_frame_done = <303>;
		mdp_rdma3_frame_done = <304>;
		mdp_rdma2_frame_done = <305>;
		mdp_rdma1_frame_done = <306>;
		mdp_rdma0_frame_done = <307>;
		mdp_hdr1_frame_done = <308>;
		mdp_hdr0_frame_done = <309>;
		mdp_fg1_frame_done = <310>;
		mdp_fg0_frame_done = <311>;
		mdp_color1_frame_done = <312>;
		mdp_color_frame_done = <313>;
		mdp_aal3_frame_done = <314>;
		mdp_aal2_frame_done = <315>;
		mdp_aal1_frame_done = <316>;
		mdp_aal_frame_done = <317>;
		stream_done_0 = <320>;
		stream_done_1 = <321>;
		stream_done_2 = <322>;
		stream_done_3 = <323>;
		stream_done_4 = <324>;
		stream_done_5 = <325>;
		stream_done_6 = <326>;
		stream_done_7 = <327>;
		stream_done_8 = <328>;
		stream_done_9 = <329>;
		stream_done_10 = <330>;
		stream_done_11 = <331>;
		stream_done_12 = <332>;
		stream_done_13 = <333>;
		stream_done_14 = <334>;
		stream_done_15 = <335>;
		mdp_wrot3_sw_rst_done = <336>;
		mdp_wrot2_sw_rst_done = <337>;
		mdp_wrot1_rst_done = <338>;
		mdp_wrot0_rst_done = <339>;
		mdp_rdma3_sw_rst_done = <340>;
		mdp_rdma2_sw_rst_done = <341>;
		mdp_rdma1_rst_done = <342>;
		mdp_rdma0_rst_done = <343>;
		mm_mutex   = <&mdp_mutex>;
		mdp_rdma0  = <&mdp_rdma0>;
		mdp_rdma1  = <&mdp_rdma1>;
		mdp_rdma2  = <&mdp_rdma2>;
		mdp_rdma3  = <&mdp_rdma3>;
		mdp_rsz0   = <&mdp_rsz0>;
		mdp_rsz1   = <&mdp_rsz1>;
		mdp_rsz2   = <&mdp_rsz2>;
		mdp_rsz3   = <&mdp_rsz3>;
		mdp_wrot0  = <&mdp_wrot0>;
		mdp_wrot1  = <&mdp_wrot1>;
		mdp_wrot2  = <&mdp_wrot2>;
		mdp_wrot3  = <&mdp_wrot3>;
		mdp_tdshp0 = <&mdp_tdshp0>;
		mdp_tdshp1 = <&mdp_tdshp1>;
		mdp_tdshp2 = <&mdp_tdshp2>;
		mdp_tdshp3 = <&mdp_tdshp3>;
		mdp_aal0   = <&mdp_aal0>;
		mdp_aal1   = <&mdp_aal1>;
		mdp_aal2   = <&mdp_aal2>;
		mdp_aal3   = <&mdp_aal3>;
		mdp_color0 = <&mdp_color0>;
		mdp_color1 = <&mdp_color1>;
		mdp_hdr0   = <&mdp_hdr0>;
		mdp_hdr1   = <&mdp_hdr1>;
		mdp_fg0    = <&mdp_fg0>;
		mdp_fg1    = <&mdp_fg1>;
		mdp_tcc0   = <&mdp_tcc0>;
		mdp_tcc1   = <&mdp_tcc1>;
		mdp_tcc2   = <&mdp_tcc2>;
		mdp_tcc3   = <&mdp_tcc3>;
		clock-names = "GCE", "GCE_TIMER", "GCE2";
		clocks = <&infracfg_ao INFRACFG_AO_GCE_CG>,
			<&infracfg_ao INFRACFG_AO_GCE_26M>,
			<&infracfg_ao INFRACFG_AO_GCE2_CG>;
	};

	scp: scp@10700000 {
		compatible = "mediatek,scp";
		status = "okay";
		reg = <0 0x10500000 0 0x180000>, /* tcm */
		<0 0x10724000 0 0x1000>,	 /* cfg */
		<0 0x10721000 0 0x1000>,	 /* clk*/
		<0 0x10730000 0 0x1000>,	 /* cfg core0 */
		<0 0x10740000 0 0x1000>,	 /* cfg core1 */
		<0 0x10752000 0 0x1000>,	 /* bus tracker */
		<0 0x10760000 0 0x40000>,	 /* llc */
		<0 0x107a5000 0 0x4>,		 /* cfg_sec */
		<0 0x107fb000 0 0x100>,		 /* mbox0 base */
		<0 0x107fb100 0 0x4>,		 /* mbox0 set */
		<0 0x107fb10c 0 0x4>,		 /* mbox0 clr */
		<0 0x107a5020 0 0x4>,		 /* mbox0 init */
		<0 0x107fc000 0 0x100>,		 /* mbox1 base */
		<0 0x107fc100 0 0x4>,		 /* mbox1 set */
		<0 0x107fc10c 0 0x4>,		 /* mbox1 clr */
		<0 0x107a5024 0 0x4>,		 /* mbox1 init */
		<0 0x107fd000 0 0x100>,		 /* mbox2 base */
		<0 0x107fd100 0 0x4>,		 /* mbox2 set */
		<0 0x107fd10c 0 0x4>,		 /* mbox2 clr */
		<0 0x107a5028 0 0x4>,		 /* mbox2 init */
		<0 0x107fe000 0 0x100>,		 /* mbox3 base */
		<0 0x107fe100 0 0x4>,		 /* mbox3 set */
		<0 0x107fe10c 0 0x4>,		 /* mbox3 clr */
		<0 0x107a502c 0 0x4>,		 /* mbox3 init */
		<0 0x107ff000 0 0x100>,		 /* mbox4 base */
		<0 0x107ff100 0 0x4>,		 /* mbox4 set */
		<0 0x107ff10c 0 0x4>,		 /* mbox4 clr */
		<0 0x107a5030 0 0x4>;		 /* mbox4 init */

		reg-names = "scp_sram_base",
			"scp_cfgreg",
			"scp_clkreg",
			"scp_cfgreg_core0",
			"scp_cfgreg_core1",
			"scp_bus_tracker",
			"scp_l1creg",
			"scp_cfgreg_sec",
			"mbox0_base",
			"mbox0_set",
			"mbox0_clr",
			"mbox0_init",
			"mbox1_base",
			"mbox1_set",
			"mbox1_clr",
			"mbox1_init",
			"mbox2_base",
			"mbox2_set",
			"mbox2_clr",
			"mbox2_init",
			"mbox3_base",
			"mbox3_set",
			"mbox3_clr",
			"mbox3_init",
			"mbox4_base",
			"mbox4_set",
			"mbox4_clr",
			"mbox4_init";

		interrupts = <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;

		 interrupt-names = "ipc0",
			"ipc1",
			"mbox0",
			"mbox1",
			"mbox2",
			"mbox3",
			"mbox4";

		core_0 = "enable";
		scp_sramSize = <0x00180000>;
	};

	dramc_ch1_rsv@10900000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x10900000 0 0x40000>;
	};

	dramc_ch1_rsv@10940000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x10940000 0 0xc0000>;
	};

	dramc_ch1_rsv@10a00000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x10a00000 0 0x40000>;
	};

	dramc_ch1_rsv@10a40000 {
		compatible = "mediatek,dramc_ch1_rsv";
		reg = <0 0x10a40000 0 0xc0000>;
	};

	gic500@0c000000 {
		compatible = "mediatek,gic500";
		reg = <0 0x0c000000 0 0x400000>;
	};

	gic_cpu@0c400000 {
		compatible = "mediatek,gic_cpu";
		reg = <0 0x0c400000 0 0x40000>;
	};

	dfd@10200b00 {
		compatible = "mediatek,dfd";
		reg = <0 0x10200b00 0 0x10000>;

		mediatek,enabled = <1>;
		mediatek,chain_length = <0x1940>;
		mediatek,rg_dfd_timeout = <0xa0>;
	};

	dfd_cache: dfd_cache {
		compatible = "mediatek,dfd_cache";
		mediatek,enabled = <0>;
		mediatek,l2c_trigger = <0>;
		mediatek,rg_dfd_timeout = <0x5dc0>;
	};

	dbg_ao@0d000000 {
		compatible = "mediatek,dbg_ao";
		reg = <0 0x0d000000 0 0x10000>;
	};

	dbg_cti@0d020000 {
		compatible = "mediatek,dbg_cti";
		reg = <0 0x0d020000 0 0x10000>;
	};

	dbg_etr@0d030000 {
		compatible = "mediatek,dbg_etr";
		reg = <0 0x0d030000 0 0x10000>;
	};

	bus_tracer@0d040000 {
		compatible = "mediatek,bus_tracer-v1";
		reg = <0 0x0d040000 0 0x100>, /* dem base */
		      <0 0x0d01a000 0 0x1000>, /* dbgao base */
		      <0 0x0d041000 0 0x3000>, /* funnel/rep/etr base */
		      <0 0x0d010000 0 0x1000>, /* bus tracer etb base */
		      <0 0x0d040800 0 0x100>, /* infra bus tracer base */
		      <0 0x0d040900 0 0x100>, /* peri1 bus tracer base */
		      <0 0x0d040a00 0 0x100>; /* peri2 bus tracer base */

		mediatek,err_flag = <0xfbf8ffff>;

		/*
		 * index 0 for infra bus tracer
		 * index 1 for peri1 bus tracer
		 * index 2 for peri2 bus tracer
		 */
		mediatek,num_tracer = <3>;
		mediatek,enabled_tracer = <0 1 1>;
		mediatek,at_id = <0x10 0x30 0x70>;

		/* filters: disabled by default */
		/*
		 * mediatek,watchpoint_filter = <0x0 0x10010000 0xfffff000>;
		 * mediatek,bypass_filter = <0x14000000 0xffff0000>;
		 * mediatek,id_filter = <0x10 0x40>;
		 * mediatek,rw_filter = <0x0 0x1>;
		 */
	};

	dbg_dem@0d0a0000 {
		compatible = "mediatek,dbg_dem";
		reg = <0 0x0d0a0000 0 0x10000>;
		interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
	};

	dbg_mdsys1@0d100000 {
		compatible = "mediatek,dbg_mdsys1";
		reg = <0 0x0d100000 0 0x80000>;
	};

	pwm@11006000 {
		compatible = "mediatek,pwm";
		reg = <0 0x11006000 0 0x1000>;
		interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg_ao INFRACFG_AO_PWM1_CG>,
			<&infracfg_ao INFRACFG_AO_PWM2_CG>,
			<&infracfg_ao INFRACFG_AO_PWM3_CG>,
			<&infracfg_ao INFRACFG_AO_PWM4_CG>,
			<&infracfg_ao INFRACFG_AO_PWM_HCLK_CG>,
			<&infracfg_ao INFRACFG_AO_PWM_CG>;

		clock-names = "PWM1-main",
			"PWM2-main",
			"PWM3-main",
			"PWM4-main",
			"PWM-HCLK-main",
			"PWM-main";
	};

	ses: ses {
		compatible = "mediatek,ses";
		state = <256>;
		ses0_reg3 = <0>;
		ses1_reg3 = <0>;
		ses2_reg3 = <0>;
		ses3_reg3 = <0>;
		ses4_reg3 = <0>;
		ses5_reg3 = <0>;
		ses6_reg3 = <0>;
		ses7_reg3 = <0>;
		ses8_reg3 = <0>;
		ses0_reg2 = <0>;
		ses1_reg2 = <0>;
		ses2_reg2 = <0>;
		ses3_reg2 = <0>;
		ses4_reg2 = <0>;
		ses5_reg2 = <0>;
		ses6_reg2 = <0>;
		ses7_reg2 = <0>;
		ses8_reg2 = <0>;
		ses0_drphipct = <0>;
		ses1_drphipct = <0>;
		ses2_drphipct = <0>;
		ses3_drphipct = <0>;
		ses4_drphipct = <0>;
		ses5_drphipct = <0>;
		ses6_drphipct = <0>;
		ses7_drphipct = <0>;
		ses8_drphipct = <0>;
		ses0_drplopct = <0>;
		ses1_drplopct = <0>;
		ses2_drplopct = <0>;
		ses3_drplopct = <0>;
		ses4_drplopct = <0>;
		ses5_drplopct = <0>;
		ses6_drplopct = <0>;
		ses7_drplopct = <0>;
		ses8_drplopct = <0>;
	};

	brisket: brisket {
		compatible = "mediatek,brisket";
		brisket_doe_ptp = <255>;
		brisket_doe_pllclken = <240>;
		brisket_doe_bren = <240>;
		brisket_doe_brisket05 = <1116226>;
		brisket_doe_brisket06 = <64497>;
		brisket_doe_brisket07 = <4095>;
		brisket_doe_brisket08 = <3210>;
		brisket_doe_brisket09 = <15872>;
	};

	credit_didt: credit_didt {
		compatible = "mediatek,credit_didt";
		credit_didt_doe_ptp = <255>;
		credit_didt_doe_enable = <61440>;
		credit_didt4_doe_ls_period = <6>;
		credit_didt5_doe_ls_period = <6>;
		credit_didt6_doe_ls_period = <6>;
		credit_didt7_doe_ls_period = <6>;
		credit_didt4_doe_ls_credit = <6>;
		credit_didt5_doe_ls_credit = <6>;
		credit_didt6_doe_ls_credit = <6>;
		credit_didt7_doe_ls_credit = <6>;
		credit_didt4_doe_ls_low_freq_period = <7>;
		credit_didt5_doe_ls_low_freq_period = <7>;
		credit_didt6_doe_ls_low_freq_period = <7>;
		credit_didt7_doe_ls_low_freq_period = <7>;
		credit_didt4_doe_ls_low_freq_enable = <0>;
		credit_didt5_doe_ls_low_freq_enable = <0>;
		credit_didt6_doe_ls_low_freq_enable = <0>;
		credit_didt7_doe_ls_low_freq_enable = <0>;
		credit_didt4_doe_vx_period = <6>;
		credit_didt5_doe_vx_period = <6>;
		credit_didt6_doe_vx_period = <6>;
		credit_didt7_doe_vx_period = <6>;
		credit_didt4_doe_vx_credit = <6>;
		credit_didt5_doe_vx_credit = <6>;
		credit_didt6_doe_vx_credit = <6>;
		credit_didt7_doe_vx_credit = <6>;
		credit_didt4_doe_vx_low_freq_period = <7>;
		credit_didt5_doe_vx_low_freq_period = <7>;
		credit_didt6_doe_vx_low_freq_period = <7>;
		credit_didt7_doe_vx_low_freq_period = <7>;
		credit_didt4_doe_vx_low_freq_enable = <0>;
		credit_didt5_doe_vx_low_freq_enable = <0>;
		credit_didt6_doe_vx_low_freq_enable = <0>;
		credit_didt7_doe_vx_low_freq_enable = <0>;
	};

	eem_fsm: eem_fsm@11278000 {
		compatible = "mediatek,eem_fsm";
		reg = <0 0x11278000 0 0x1000>;
		interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg_ao INFRACFG_AO_THERM_CG>;
		clock-names = "therm-main";
		eem-status = <1>;
		eem-initmon-little = <0xf>;
		eem-initmon-big = <0xf>;
		eem-initmon-cci = <0xf>;
		eem-initmon-gpu = <0xf>;
		eem-clamp-little = <0>;
		eem-clamp-big = <0>;
		eem-clamp-cci = <0>;
		eem-clamp-gpu = <0>;
		eem-offset-little = <0xff>;
		eem-offset-big = <0xff>;
		eem-offset-cci = <0xff>;
		eem-offset-gpu = <0xff>;
	};

	eemgpu_fsm: eemgpu_fsm@1100b000 {
		compatible = "mediatek,eemgpu_fsm";
		reg = <0 0x1100b000 0 0x1000>;
		interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
		eemg-status = <1>;
		eemg-initmon-gpu = <0xf>;
		eemg-clamp-gpu = <0>;
		eemg-offset-gpu = <0xff>;
	};

	therm_ctrl@1100b000 {
		compatible = "mediatek,therm_ctrl";
		reg = <0 0x1100b000 0 0x26E200>;
		interrupts =
			<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&infracfg_ao INFRACFG_AO_THERM_CG>;
		clock-names = "therm-main";
	};


	tboard_thermistor1: thermal-sensor1 {
		compatible = "mediatek,mtboard-thermistor1";
		io-channels = <&auxadc 0>;
		io-channel-names = "thermistor-ch0";
	};

	tboard_thermistor2: thermal-sensor2 {
		compatible = "mediatek,mtboard-thermistor2";
		io-channels = <&auxadc 1>;
		io-channel-names = "thermistor-ch1";
	};

	tboard_thermistor3: thermal-sensor3 {
		compatible = "mediatek,mtboard-thermistor3";
		io-channels = <&auxadc 2>;
		io-channel-names = "thermistor-ch2";
	};

	mt6315_them_intr {
		compatible = "mediatek,mt6315_therm_intr";
		interrupts-extended =
			<&mt6315_6_regulator INT_TEMP_L IRQ_TYPE_EDGE_RISING>,
			<&mt6315_6_regulator INT_TEMP_H IRQ_TYPE_EDGE_RISING>,
			<&mt6315_6_regulator INT_RCS0 IRQ_TYPE_LEVEL_HIGH>,
			<&mt6315_7_regulator INT_TEMP_L IRQ_TYPE_EDGE_RISING>,
			<&mt6315_7_regulator INT_TEMP_H IRQ_TYPE_EDGE_RISING>,
			<&mt6315_7_regulator INT_RCS0 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names =
			"6315_6_temp_l",
			"6315_6_temp_h",
			"6315_6_rcs0",
			"6315_7_temp_l",
			"6315_7_temp_h",
			"6315_7_rcs0";
	};

	auxadc: auxadc@11001000 {
		compatible = "mediatek,mt6768-auxadc";
		reg = <0 0x11001000 0 0x1000>;
		interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>;
		clocks = <&infracfg_ao INFRACFG_AO_AUXADC_CG>;
		clock-names = "main";
		#io-channel-cells = <1>;
		/* Auxadc efuse calibration */
		/* 1. Auxadc cali on/off bit shift */
		mediatek,cali-en-bit = <20>;
		/* 2. Auxadc cali ge bits shift */
		mediatek,cali-ge-bit = <10>;
		/* 3. Auxadc cali oe bits shift */
		mediatek,cali-oe-bit = <0>;
		/* 4. Auxadc cali efuse index */
		mediatek,cali-efuse-index = <113>;
	};

	mali: mali@13000000 {
		compatible = "mediatek,mali", "arm,mali-valhall";
		reg = <0 0x13000000 0 0x4000>;
		interrupts =
			<GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names =
			"GPU",
			"MMU",
			"JOB",
			"EVENT",
			"PWR";
	};

	gpufreq {
		compatible = "mediatek,gpufreq";
		clocks =
			<&topckgen TOP_MUX_MFG>,
			/* mfgpll_ck(1150MHz) */
			<&topckgen TOP_MFGPLL_CK>,
			/* mainpll_d5_d2(218.4MHz) */
			<&topckgen TOP_MAINPLL_D5_D2>,
			<&g3d_config MFGCFG_BG3D>,
			/* MFG0: MFG_ASYNC */
			<&scpsys SCP_SYS_MFG0>,
			/* MFG1: MFG_TOP */
			<&scpsys SCP_SYS_MFG1>,
			/* MFG2: SHADER_STACK_0: core0 */
			<&scpsys SCP_SYS_MFG2>,
			/* MFG3: SHADER_STACK_1: core1, core2 */
			<&scpsys SCP_SYS_MFG3>,
			/* MFG4: SHADER_STACK_2: core3, core4 */
			<&scpsys SCP_SYS_MFG4>,
			/* MFG5: SHADER_STACK_5: core5, core6 */
			<&scpsys SCP_SYS_MFG5>,
			/* MFG6: SHADER_STACK_6: core7, core8 */
			<&scpsys SCP_SYS_MFG6>;
		clock-names =
			"clk_mux",
			"clk_main_parent",
			"clk_sub_parent",
			"subsys_mfg_cg",
			"mtcmos_mfg_async",
			"mtcmos_mfg",
			"mtcmos_mfg_core0",
			"mtcmos_mfg_core1_2",
			"mtcmos_mfg_core3_4",
			"mtcmos_mfg_core5_6",
			"mtcmos_mfg_core7_8";
			_vgpu-supply = <&mt6315_7_vbuck1>;
			_vsram_gpu-supply = <&mt_pmic_vsram_others_ldo_reg>;
	};

	mali_dvfs_hint@13fbb000 {
		compatible = "mediatek,mali_dvfs_hint", "syscon";
		reg = <0 0x13fbb000 0 0x1000>;
		#clock-cells = <1>;
	};

	g3d_secure_reg@13fbc000 {
		compatible = "mediatek,g3d_secure_reg";
		reg = <0 0x13fbc000 0 0x1000>;
	};

	g3d_testbench@13fbd000 {
		compatible = "mediatek,g3d_testbench", "syscon";
		reg = <0 0x13fbd000 0 0x1000>;
		#clock-cells = <1>;
	};

	g3d_config: g3d_config@13fbf000 {
		compatible = "mediatek,g3d_config", "syscon";
		reg = <0 0x13fbf000 0 0x1000>;
		#clock-cells = <1>;
	};

	devapc_ao_infra_peri_debug1@10023000  {
		compatible = "mediatek,devapc_ao_infra_peri_debug1";
		reg = <0 0x10023000 0 0x1000>;
	};

	devapc_ao_infra_peri_debug2@10025000  {
		compatible = "mediatek,devapc_ao_infra_peri_debug2";
		reg = <0 0x10025000 0 0x1000>;
	};

	devapc_ao_infra_peri_debug3@1002b000  {
		compatible = "mediatek,devapc_ao_infra_peri_debug3";
		reg = <0 0x1002b000 0 0x1000>;
	};

	devapc_ao_infra_peri_debug4@1002e000  {
		compatible = "mediatek,devapc_ao_infra_peri_debug4";
		reg = <0 0x1002e000 0 0x1000>;
	};

	mdpsys_config: mdpsys_config@1f000000 {
		compatible = "mediatek,mdpsys_config", "syscon";
		reg = <0 0x1f000000 0 0x1000>;
		#clock-cells = <1>;
		interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_IMG_DL_ASYNC0>,
			<&mdpsys_config MDP_IMG_DL_ASYNC1>,
			<&mdpsys_config MDP_IMG_DL_ASYNC2>,
			<&mdpsys_config MDP_IMG_DL_ASYNC3>,
			<&mdpsys_config MDP_IMG0_IMG_DL_ASYNC0>,
			<&mdpsys_config MDP_IMG0_IMG_DL_ASYNC1>,
			<&mdpsys_config MDP_IMG1_IMG_DL_ASYNC2>,
			<&mdpsys_config MDP_IMG1_IMG_DL_ASYNC3>,
			<&mdpsys_config MDP_APB_BUS>,
			<&mdpsys_config MDP_APMCU_GALS>;
		clock-names = "MDP_IMG_DL_ASYNC0",
				"MDP_IMG_DL_ASYNC1",
				"MDP_IMG_DL_ASYNC2",
				"MDP_IMG_DL_ASYNC3",
				"MDP_IMG0_IMG_DL_ASYNC0",
				"MDP_IMG0_IMG_DL_ASYNC1",
				"MDP_IMG1_IMG_DL_ASYNC2",
				"MDP_IMG1_IMG_DL_ASYNC3",
				"MDP_APB_BUS",
				"MDP_APMCU_GALS";
	};

	irq_nfc: irq_nfc {
		compatible = "mediatek,irq_nfc-eint";
	};

	mdp_mutex: mdp_mutex@1f001000 {
		compatible = "mediatek,mdp_mutex";
		reg = <0 0x1f001000 0 0x1000>;
		interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_MUTEX0>;
		clock-names = "MDP_MUTEX0";
	};

	mdp_rdma0: mdp_rdma0@1f006000 {
		compatible = "mediatek,mdp_rdma0", "mediatek,mdp";
		reg = <0 0x1f006000 0 0x1000>;
		interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_RDMA0>,
			<&infracfg_ao INFRACFG_AO_GCE2_CG>,
			<&infracfg_ao INFRACFG_AO_GCE_26M>;
		clock-names = "MDP_RDMA0", "GCE", "GCE_TIMER";
		mmsys_config = <&mdpsys_config>;
		mm_mutex   = <&mdp_mutex>;
		mboxes = <&gce_mbox_m_sec 10 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox_m 12 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox_m 13 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox_m 14 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox_m 21 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox_m 22 0 CMDQ_THR_PRIO_1>;
		/* <-- To be removed after DRM enabled */
		/* To be removed after DRM enabled --> */
		/* To Do: refine after mdp3 */
		mdp_rdma0  = <&mdp_rdma0>;
		mdp_rdma1  = <&mdp_rdma1>;
		mdp_rdma2  = <&mdp_rdma2>;
		mdp_rdma3  = <&mdp_rdma3>;
		mdp_rsz0   = <&mdp_rsz0>;
		mdp_rsz1   = <&mdp_rsz1>;
		mdp_rsz2   = <&mdp_rsz2>;
		mdp_rsz3   = <&mdp_rsz3>;
		mdp_wrot0  = <&mdp_wrot0>;
		mdp_wrot1  = <&mdp_wrot1>;
		mdp_wrot2  = <&mdp_wrot2>;
		mdp_wrot3  = <&mdp_wrot3>;
		mdp_tdshp0 = <&mdp_tdshp0>;
		mdp_tdshp1 = <&mdp_tdshp1>;
		mdp_tdshp2 = <&mdp_tdshp2>;
		mdp_tdshp3 = <&mdp_tdshp3>;
		mdp_aal0   = <&mdp_aal0>;
		mdp_aal1   = <&mdp_aal1>;
		mdp_aal2   = <&mdp_aal2>;
		mdp_aal3   = <&mdp_aal3>;
		mdp_color0 = <&mdp_color0>;
		mdp_color1 = <&mdp_color1>;
		mdp_hdr0   = <&mdp_hdr0>;
		mdp_hdr1   = <&mdp_hdr1>;
		mdp_fg0    = <&mdp_fg0>;
		mdp_fg1    = <&mdp_fg1>;
		mdp_tcc0   = <&mdp_tcc0>;
		mdp_tcc1   = <&mdp_tcc1>;
		mdp_tcc2   = <&mdp_tcc2>;
		mdp_tcc3   = <&mdp_tcc3>;
		/* To Do: refine after DRM enabled */
		thread_count = <24>;
		mediatek,mailbox-gce = <&gce_mbox>;
		mediatek,mailbox-gce-m = <&gce_mbox_m>;
		disp_mutex_reg = <0x14120000 0x1000>;
		g3d_config_base = <0x13000000 0 0xffff0000>;
		mmsys_config_base = <0x14000000 1 0xffff0000>;
		disp_dither_base = <0x14010000 2 0xffff0000>;
		mm_na_base = <0x14020000 3 0xffff0000>;
		imgsys_base = <0x15020000 4 0xffff0000>;
		vdec_gcon_base = <0x18800000 5 0xffff0000>;
		venc_gcon_base = <0x18810000 6 0xffff0000>;
		conn_peri_base = <0x18820000 7 0xffff0000>;
		topckgen_base = <0x18830000 8 0xffff0000>;
		kp_base = <0x18840000 9 0xffff0000>;
		scp_sram_base = <0x10000000 10 0xffff0000>;
		infra_na3_base = <0x10010000 11 0xffff0000>;
		infra_na4_base = <0x10020000 12 0xffff0000>;
		scp_base = <0x10030000 13 0xffff0000>;
		mcucfg_base = <0x10040000 14 0xffff0000>;
		gcpu_base = <0x10050000 15 0xffff0000>;
		usb0_base = <0x10200000 16 0xffff0000>;
		usb_sif_base = <0x10280000 17 0xffff0000>;
		audio_base = <0x17000000 18 0xffff0000>;
		vdec_base = <0x17010000 19 0xffff0000>;
		msdc2_base = <0x17020000 20 0xffff0000>;
		vdec1_base = <0x17030000 21 0xffff0000>;
		msdc3_base = <0x18000000 22 0xffff0000>;
		ap_dma_base = <0x18010000 23 0xffff0000>;
		gce_base = <0x18020000 24 0xffff0000>;
		vdec2_base = <0x18040000 25 0xffff0000>;
		vdec3_base = <0x18050000 26 0xffff0000>;
		camsys_base = <0x18080000 27 0xffff0000>;
		camsys1_base = <0x180a0000 28 0xffff0000>;
		camsys2_base = <0x180b0000 29 0xffff0000>;
		dip2_cq_thread0_frame_done = <1>;
		dip2_cq_thread1_frame_done = <2>;
		dip2_cq_thread2_frame_done = <3>;
		dip2_cq_thread3_frame_done = <4>;
		dip2_cq_thread4_frame_done = <5>;
		dip2_cq_thread5_frame_done = <6>;
		dip2_cq_thread6_frame_done = <7>;
		dip2_cq_thread7_frame_done = <8>;
		dip2_cq_thread8_frame_done = <9>;
		dip2_cq_thread9_frame_done = <10>;
		dip2_cq_thread10_frame_done = <11>;
		dip2_cq_thread11_frame_done = <12>;
		dip2_cq_thread12_frame_done = <13>;
		dip2_cq_thread13_frame_done = <14>;
		dip2_cq_thread14_frame_done = <15>;
		dip2_cq_thread15_frame_done = <16>;
		dip2_cq_thread16_frame_done = <17>;
		dip2_cq_thread17_frame_done = <18>;
		dip2_cq_thread18_frame_done = <19>;
		dip2_cq_thread19_frame_done = <20>;
		dip2_cq_thread20_frame_done = <21>;
		dip2_cq_thread21_frame_done = <22>;
		wpe_b_frame_done = <23>;
		dip2_cq_thread23_frame_done = <24>;
		dip_cq_thread0_frame_done = <33>;
		dip_cq_thread1_frame_done = <34>;
		dip_cq_thread2_frame_done = <35>;
		dip_cq_thread3_frame_done = <36>;
		dip_cq_thread4_frame_done = <37>;
		dip_cq_thread5_frame_done = <38>;
		dip_cq_thread6_frame_done = <39>;
		dip_cq_thread7_frame_done = <40>;
		dip_cq_thread8_frame_done = <41>;
		dip_cq_thread9_frame_done = <42>;
		dip_cq_thread10_frame_done = <43>;
		dip_cq_thread11_frame_done = <44>;
		dip_cq_thread12_frame_done = <45>;
		dip_cq_thread13_frame_done = <46>;
		dip_cq_thread14_frame_done = <47>;
		dip_cq_thread15_frame_done = <48>;
		dip_cq_thread16_frame_done = <49>;
		dip_cq_thread17_frame_done = <50>;
		dip_cq_thread18_frame_done = <51>;
		dip_cq_thread19_frame_done = <52>;
		dip_cq_thread20_frame_done = <53>;
		dip_cq_thread21_frame_done = <54>;
		wpe_a_frame_done = <55>;
		dip_cq_thread23_frame_done = <56>;
		ipe_event_tx_frame_done_0 = <129>;
		ipe_event_tx_frame_done_1 = <130>;
		rsc_frame_done = <131>;
		ipe_event_tx_frame_done_3 = <132>;
		ipe_event_tx_frame_done_4 = <133>;
		isp_frame_done_a = <193>;
		isp_frame_done_b = <194>;
		isp_frame_done_c = <195>;
		camsv_0_pass1_done = <196>;
		camsv_0_2_pass1_done = <197>;
		camsv_1_pass1_done = <198>;
		camsv_2_pass1_done = <199>;
		camsv_3_pass1_done = <200>;
		mraw_0_pass1_done = <201>;
		mraw_1_pass1_done = <202>;
		seninf_0_fifo_full = <203>;
		seninf_1_fifo_full = <204>;
		seninf_2_fifo_full = <205>;
		seninf_3_fifo_full = <206>;
		seninf_4_fifo_full = <207>;
		seninf_5_fifo_full = <208>;
		seninf_6_fifo_full = <209>;
		seninf_7_fifo_full = <210>;
		seninf_cam8_fifo_full = <211>;
		seninf_cam9_fifo_full = <212>;
		seninf_cam10_fifo_full = <213>;
		seninf_cam11_fifo_full = <214>;
		seninf_cam12_fifo_full = <215>;
		tg_ovrun_a_int_dly = <216>;
		tg_graberr_a_int_dly = <217>;
		tg_ovrun_b_int_dly = <218>;
		tg_graberr_b_int_dly = <219>;
		tg_ovrun_c_int = <220>;
		tg_graberr_c_int = <221>;
		tg_ovrun_m0_int = <222>;
		dma_r1_error_m0_int = <223>;
		mdp_rdma0_sof = <256>;
		mdp_rdma1_sof = <257>;
		mdp_rdma2_sof = <258>;
		mdp_rdma3_sof = <259>;
		mdp_fg0_sof = <260>;
		mdp_fg1_sof = <261>;
		mdp_aal_sof = <262>;
		mdp_aal1_sof = <263>;
		mdp_aal2_sof = <264>;
		mdp_aal3_sof = <265>;
		mdp_hdr0_sof = <266>;
		mdp_hdr1_sof = <267>;
		mdp_rsz0_sof = <268>;
		mdp_rsz1_sof = <269>;
		mdp_rsz2_sof = <270>;
		mdp_rsz3_sof = <271>;
		mdp_wrot0_sof = <272>;
		mdp_wrot1_sof = <273>;
		mdp_wrot2_sof = <274>;
		mdp_wrot3_sof = <275>;
		mdp_tdshp_sof = <276>;
		mdp_tdshp1_sof = <277>;
		mdp_tdshp2_sof = <278>;
		mdp_tdshp3_sof = <279>;
		mdp_tcc0_sof = <280>;
		mdp_tcc1_sof = <281>;
		mdp_tcc2_sof = <282>;
		mdp_tcc3_sof = <283>;
		img_dl_relay_sof = <284>;
		img_dl_relay1_sof = <285>;
		img_dl_relay2_sof = <286>;
		img_dl_relay3_sof = <287>;
		mdp_wrot3_write_frame_done = <288>;
		mdp_wrot2_write_frame_done = <289>;
		mdp_wrot1_write_frame_done = <290>;
		mdp_wrot0_write_frame_done = <291>;
		mdp_tdshp3_frame_done = <292>;
		mdp_tdshp2_frame_done = <293>;
		mdp_tdshp1_frame_done = <294>;
		mdp_tdshp_frame_done = <295>;
		mdp_tcc3_frame_done = <296>;
		mdp_tcc2_frame_done = <297>;
		mdp_tcc1_frame_done = <298>;
		mdp_tcc0_frame_done = <299>;
		mdp_rsz3_frame_done = <300>;
		mdp_rsz2_frame_done = <301>;
		mdp_rsz1_frame_done = <302>;
		mdp_rsz0_frame_done = <303>;
		mdp_rdma3_frame_done = <304>;
		mdp_rdma2_frame_done = <305>;
		mdp_rdma1_frame_done = <306>;
		mdp_rdma0_frame_done = <307>;
		mdp_hdr1_frame_done = <308>;
		mdp_hdr0_frame_done = <309>;
		mdp_fg1_frame_done = <310>;
		mdp_fg0_frame_done = <311>;
		mdp_color1_frame_done = <312>;
		mdp_color_frame_done = <313>;
		mdp_aal3_frame_done = <314>;
		mdp_aal2_frame_done = <315>;
		mdp_aal1_frame_done = <316>;
		mdp_aal_frame_done = <317>;
		stream_done_0 = <320>;
		stream_done_1 = <321>;
		stream_done_2 = <322>;
		stream_done_3 = <323>;
		stream_done_4 = <324>;
		stream_done_5 = <325>;
		stream_done_6 = <326>;
		stream_done_7 = <327>;
		stream_done_8 = <328>;
		stream_done_9 = <329>;
		stream_done_10 = <330>;
		stream_done_11 = <331>;
		stream_done_12 = <332>;
		stream_done_13 = <333>;
		stream_done_14 = <334>;
		stream_done_15 = <335>;
		mdp_wrot3_sw_rst_done = <336>;
		mdp_wrot2_sw_rst_done = <337>;
		mdp_wrot1_rst_done = <338>;
		mdp_wrot0_rst_done = <339>;
		mdp_rdma3_sw_rst_done = <340>;
		mdp_rdma2_sw_rst_done = <341>;
		mdp_rdma1_rst_done = <342>;
		mdp_rdma0_rst_done = <343>;
	};

	mdp_rdma1: mdp_rdma1@1f007000 {
		compatible = "mediatek,mdp_rdma1";
		reg = <0 0x1f007000 0 0x1000>;
		interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_RDMA1>;
		clock-names = "MDP_RDMA1";
	};

	mdp_rdma2: mdp_rdma2@1f008000 {
		compatible = "mediatek,mdp_rdma2";
		reg = <0 0x1f008000 0 0x1000>;
		interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_RDMA2>;
		clock-names = "MDP_RDMA2";
	};

	mdp_rdma3: mdp_rdma3@1f009000 {
		compatible = "mediatek,mdp_rdma3";
		reg = <0 0x1f009000 0 0x1000>;
		interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_RDMA3>;
		clock-names = "MDP_RDMA3";
	};

	mdp_fg0: mdp_fg0@1f00a000 {
		compatible = "mediatek,mdp_fg0";
		reg = <0 0x1f00a000 0 0x1000>;
		interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_FG0>;
		clock-names = "MDP_FG0";
	};

	mdp_fg1: mdp_fg1@1f00b000 {
		compatible = "mediatek,mdp_fb1";
		reg = <0 0x1f00b000 0 0x1000>;
		interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_FG1>;
		clock-names = "MDP_FG1";
	};

	mdp_aal0: mdp_aal0@1f00c000 {
		compatible = "mediatek,mdp_aal0";
		reg = <0 0x1f00c000 0 0x1000>;
		interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_AAL0>;
		clock-names = "MDP_AAL0";
	};

	mdp_aal1: mdp_aal1@1f00d000 {
		compatible = "mediatek,mdp_aal1";
		reg = <0 0x1f00d000 0 0x1000>;
		interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_AAL1>;
		clock-names = "MDP_AAL1";
	};

	mdp_aal2: mdp_aal2@1f00e000 {
		compatible = "mediatek,mdp_aal2";
		reg = <0 0x1f00e000 0 0x1000>;
		interrupts = <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_AAL2>;
		clock-names = "MDP_AAL2";
	};

	mdp_aal3: mdp_aal3@1f00f000 {
		compatible = "mediatek,mdp_aal3";
		reg = <0 0x1f00f000 0 0x1000>;
		interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_AAL3>;
		clock-names = "MDP_AAL3";
	};

	mdp_hdr0: mdp_hdr0@1f010000 {
		compatible = "mediatek,mdp_hdr0";
		reg = <0 0x1f010000 0 0x1000>;
		interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_HDR0>;
		clock-names = "MDP_HDR0";
	};

	mdp_hdr1: mdp_hdr1@1f011000 {
		compatible = "mediatek,mdp_hdr1";
		reg = <0 0x1f011000 0 0x1000>;
		interrupts = <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_HDR1>;
		clock-names = "MDP_HDR1";
	};

	mdp_rsz0: mdp_rsz0@1f012000 {
		compatible = "mediatek,mdp_rsz0";
		reg = <0 0x1f012000 0 0x1000>;
		interrupts = <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_RSZ0>;
		clock-names = "MDP_RSZ0";
	};

	mdp_rsz1: mdp_rsz1@1f013000 {
		compatible = "mediatek,mdp_rsz1";
		reg = <0 0x1f013000 0 0x1000>;
		interrupts = <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_RSZ1>;
		clock-names = "MDP_RSZ1";
	};

	mdp_rsz2: mdp_rsz2@1f014000 {
		compatible = "mediatek,mdp_rsz2";
		reg = <0 0x1f014000 0 0x1000>;
		interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_RSZ2>;
		clock-names = "MDP_RSZ2";
	};

	mdp_rsz3: mdp_rsz3@1f015000 {
		compatible = "mediatek,mdp_rsz3";
		reg = <0 0x1f015000 0 0x1000>;
		interrupts = <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_RSZ3>;
		clock-names = "MDP_RSZ3";
	};

	mdp_wrot0: mdp_wrot0@1f016000 {
		compatible = "mediatek,mdp_wrot0";
		reg = <0 0x1f016000 0 0x1000>;
		interrupts = <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_WROT0>;
		clock-names = "MDP_WROT0";
	};

	mdp_wrot1: mdp_wrot1@1f017000 {
		compatible = "mediatek,mdp_wrot1";
		reg = <0 0x1f017000 0 0x1000>;
		interrupts = <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_WROT1>;
		clock-names = "MDP_WROT1";
	};

	mdp_wrot2: mdp_wrot2@1f018000 {
		compatible = "mediatek,mdp_wrot2";
		reg = <0 0x1f018000 0 0x1000>;
		interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_WROT2>;
		clock-names = "MDP_WROT2";
	};

	mdp_wrot3: mdp_wrot3@1f019000 {
		compatible = "mediatek,mdp_wrot3";
		reg = <0 0x1f019000 0 0x1000>;
		interrupts = <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_WROT3>;
		clock-names = "MDP_WROT3";
	};

	mdp_tdshp0: mdp_tdshp0@1f01a000 {
		compatible = "mediatek,mdp_tdshp0";
		reg = <0 0x1f01a000 0 0x1000>;
		interrupts = <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_TDSHP0>;
		clock-names = "MDP_TDSHP0";
	};

	mdp_tdshp1: mdp_tdshp1@1f01b000 {
		compatible = "mediatek,mdp_tdshp1";
		reg = <0 0x1f01b000 0 0x1000>;
		interrupts = <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_TDSHP1>;
		clock-names = "MDP_TDSHP1";
	};

	mdp_tdshp2: mdp_tdshp2@1f01c000 {
		compatible = "mediatek,mdp_tdshp2";
		reg = <0 0x1f01c000 0 0x1000>;
		interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_TDSHP2>;
		clock-names = "MDP_TDSHP2";
	};

	mdp_tdshp3: mdp_tdshp3@1f01d000 {
		compatible = "mediatek,mdp_tdshp3";
		reg = <0 0x1f01d000 0 0x1000>;
		interrupts = <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_TDSHP3>;
		clock-names = "MDP_TDSHP3";
	};

	mdp_tcc0: mdp_tcc0@1f01e000 {
		compatible = "mediatek,mdp_tcc0";
		reg = <0 0x1f01e000 0 0x1000>;
		interrupts = <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_TCC0>;
		clock-names = "MDP_TCC0";
	};

	mdp_tcc1: mdp_tcc1@1f01f000 {
		compatible = "mediatek,mdp_tcc1";
		reg = <0 0x1f01f000 0 0x1000>;
		interrupts = <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_TCC1>;
		clock-names = "MDP_TCC1";
	};

	mdp_tcc2: mdp_tcc2@1f010000 {
		compatible = "mediatek,mdp_tcc2";
		reg = <0 0x1f020000 0 0x1000>;
		interrupts = <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_TCC2>;
		clock-names = "MDP_TCC2";
	};

	mdp_tcc3: mdp_tcc3@1f011000 {
		compatible = "mediatek,mdp_tcc3";
		reg = <0 0x1f021000 0 0x1000>;
		interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_TCC3>;
		clock-names = "MDP_TCC3";
	};

	mdp_color0: mdp_color0@1f02c000 {
		compatible = "mediatek,mdp_color0";
		reg = <0 0x1f02c000 0 0x1000>;
		interrupts = <GIC_SPI 555 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_COLOR0>;
		clock-names = "MDP_COLOR0";
	};

	mdp_color1: mdp_color1@1f02d000 {
		compatible = "mediatek,mdp_color1";
		reg = <0 0x1f02d000 0 0x1000>;
		interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mdpsys_config MDP_MDP_COLOR1>;
		clock-names = "MDP_COLOR1";
	};

	mtkfb: mtkfb {
		compatible = "mediatek,mtkfb";
	};

	dispsys {
		compatible = "mediatek,dispsys";
		mediatek,larb = <&smi_larb0>;
		clocks = <&dispsys_config SCP_SYS_DIS>,
			<&dispsys_config MM_SMI_COMMON>,
			<&dispsys_config MM_SMI_GALS>,
			<&dispsys_config MM_SMI_INFRA>,
			<&dispsys_config MM_SMI_IOMMU>,
			<&dispsys_config MM_DISP_OVL0>,
			<&dispsys_config MM_DISP_OVL1>,
			<&dispsys_config MM_DISP_OVL0_2L>,
			<&dispsys_config MM_DISP_OVL1_2L>,
			<&dispsys_config MM_DISP_OVL2_2L>,
			<&dispsys_config MM_DISP_OVL3_2L>,
			<&dispsys_config MM_DISP_RDMA0>,
			<&dispsys_config MM_DISP_RDMA4>,
			<&dispsys_config MM_DISP_RDMA5>,
			<&dispsys_config MM_DISP_WDMA0>,
			<&dispsys_config MM_DISP_WDMA1>,
			<&dispsys_config MM_DISP_COLOR0>,
			<&dispsys_config MM_DISP_CCORR0>,
			<&dispsys_config MM_DISP_AAL0>,
			<&dispsys_config MM_MDP_AAL4>,
			<&dispsys_config MM_DISP_GAMMA0>,
			<&dispsys_config MM_DISP_POSTMASK0>,
			<&dispsys_config MM_DISP_DITHER0>,
			<&dispsys_config MM_DISP_DSI0>,
			<&dispsys_config MM_DSI_DSI0>,
			<&dispsys_config MM_26MHZ>,
			<&dispsys_config MM_DISP_RSZ0>,
			<&dispsys_config MM_DISP_MUTEX0>,
			<&dispsys_config MM_DISP_MERGE1>,
			<&dispsys_config  MM_DISP_DP_INTF>,
			<&dispsys_config  MM_DP_INTF>,
			<&apmixed APMIXED_MIPID0_26M>,
			<&topckgen TOP_MUX_DISP_PWM>,
			<&infracfg_ao INFRACFG_AO_DISP_PWM_CG>,
			<&clk26m>,
			<&topckgen TOP_UNIVPLL_D6_D4>,
			<&topckgen TOP_OSC_D2>,
			<&topckgen TOP_OSC_D4>,
			<&topckgen TOP_OSC_D16>;

		clock-names = "MMSYS_MTCMOS",
			"MMSYS_SMI_COMMON",
			"MMSYS_SMI_GALS",
			"MMSYS_SMI_INFRA",
			"MMSYS_SMI_IOMMU",
			"MMSYS_DISP_OVL0",
			"MMSYS_DISP_OVL1",
			"MMSYS_DISP_OVL0_2L",
			"MMSYS_DISP_OVL1_2L",
			"MMSYS_DISP_OVL2_2L",
			"MMSYS_DISP_OVL3_2L",
			"MMSYS_DISP_RDMA0",
			"MMSYS_DISP_RDMA4",
			"MMSYS_DISP_RDMA5",
			"MMSYS_DISP_WDMA0",
			"MMSYS_DISP_WDMA1",
			"MMSYS_DISP_COLOR0",
			"MMSYS_DISP_CCORR0",
			"MMSYS_DISP_AAL0",
			"MMSYS_DISP_MDP_AAL4",
			"MMSYS_DISP_GAMMA0",
			"MMSYS_DISP_POSTMASK0",
			"MMSYS_DISP_DITHER0",
			"MMSYS_DSI0_MM_CK",
			"MMSYS_DSI0_IF_CK",
			"MMSYS_26M",
			"MMSYS_DISP_RSZ0",
			"MMSYS_DISP_MUTEX0",
			"MMSYS_DISP_MERGE1",
			"MMSYS_DP_INTF0",
			"MM_DP_INTF0",
			"APMIXED_MIPI_26M",
			"TOP_MUX_DISP_PWM",
			"DISP_PWM",
			"TOP_26M",
			"TOP_UNIVPLL_D6_D4",
			"TOP_OSC_D2",
			"TOP_OSC_D4",
			"TOP_OSC_D16";
	};

	disp_pwm: disp_pwm0@1100e000 {
		compatible = "mediatek,disp_pwm0",
				"mediatek,mt6885-disp-pwm";
		reg = <0 0x1100e000 0 0x1000>;
		interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_LOW>;
		#pwm-cells = <2>;
		clocks = <&infracfg_ao INFRACFG_AO_DISP_PWM_CG>,
			<&topckgen TOP_MUX_DISP_PWM>,
			<&topckgen TOP_OSC_D4>;
		clock-names = "main", "mm", "pwm_src";
	};

	disp_ovl0: disp_ovl@14000000 {
		compatible = "mediatek,disp_ovl0",
					"mediatek,mt6885-disp-ovl";
		reg = <0 0x14000000 0 0x1000>;
		interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_OVL0>;
		mediatek,larb = <&smi_larb0>;
		mediatek,smi-id = <0>;
		iommus = <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
			 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>;
	};

	disp_ovl0_2l: disp_ovl@14001000 {
		compatible = "mediatek,disp_ovl0_2l",
					"mediatek,mt6885-disp-ovl";
		reg = <0 0x14001000 0 0x1000>;
		interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_OVL0_2L>;
		mediatek,larb = <&smi_larb1>;
		mediatek,smi-id = <1>;
		iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
			 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>;
	};

	disp_ovl2_2l: disp_ovl@14002000 {
		compatible = "mediatek,disp_ovl2_2l",
					"mediatek,mt6885-disp-ovl";
		reg = <0 0x14002000 0 0x1000>;
		interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_OVL2_2L>;
		mediatek,larb = <&smi_larb1>;
		mediatek,smi-id = <1>;
		iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
			 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>;
	};

	disp_rdma0: disp_rdma@14003000 {
		compatible = "mediatek,disp_rdma0",
					"mediatek,mt6885-disp-rdma";
		reg = <0 0x14003000 0 0x1000>;
		interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_RDMA0>;
		mediatek,larb = <&smi_larb0>;
		mediatek,smi-id = <0>;
		iommus = <&iommu0 M4U_PORT_L0_DISP_RDMA0>;
	};

	reserved@14004000 {
		compatible = "mediatek,reserved";
		reg = <0 0x14004000 0 0x1000>;
	};

	disp_rdma4: disp_rdma@14005000 {
		compatible = "mediatek,disp_rdma4",
					"mediatek,mt6885-disp-rdma";
		reg = <0 0x14005000 0 0x1000>;
		interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_RDMA4>;
		mediatek,larb = <&smi_larb0>;
		mediatek,smi-id = <0>;
		iommus = <&iommu0 M4U_PORT_L0_DISP_FAKE0>;
	};

	disp_wdma0: disp_wdma@14006000 {
		compatible = "mediatek,disp_wdma0",
					"mediatek,mt6885-disp-wdma";
		reg = <0 0x14006000 0 0x1000>;
		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_WDMA0>;
		mediatek,larb = <&smi_larb0>;
		mediatek,smi-id = <0>;
		iommus = <&iommu0 M4U_PORT_L0_DISP_WDMA0>;
	};

	disp_color0: disp_color@14007000 {
		compatible = "mediatek,disp_color0",
					"mediatek,mt6885-disp-color";
		reg = <0 0x14007000 0 0x1000>;
		interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_COLOR0>;
	};

	disp_ccorr0: disp_ccorr@14008000 {
		compatible = "mediatek,disp_ccorr0",
					"mediatek,mt6885-disp-ccorr";
		reg = <0 0x14008000 0 0x1000>;
		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_CCORR0>;
	};

	disp_aal0: disp_aal@14009000 {
		compatible = "mediatek,disp_aal0",
					"mediatek,mt6885-disp-aal";
		reg = <0 0x14009000 0 0x1000>;
		interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_AAL0>;
		aal_dre3 = <&mdp_aal4>;
	};

	disp_gamma0: disp_gamma@1400a000 {
		compatible = "mediatek,disp_gamma0",
					"mediatek,mt6885-disp-gamma";
		reg = <0 0x1400a000 0 0x1000>;
		interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_GAMMA0>;
	};

	disp_dither0: disp_dither@1400b000 {
		compatible = "mediatek,disp_dither0",
					"mediatek,mt6885-disp-dither";
		reg = <0 0x1400b000 0 0x1000>;
		interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_DITHER0>;
	};

	disp_rsz0: disp_rsz@1400c000 {
		compatible = "mediatek,disp_rsz0",
					"mediatek,mt6885-disp-rsz";
		reg = <0 0x1400c000 0 0x1000>;
		interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_RSZ0>;
	};

	disp_postmask0: disp_postmask@1400d000 {
		compatible = "mediatek,disp_postmask0",
					"mediatek,mt6885-disp-postmask";
		reg = <0 0x1400d000 0 0x1000>;
		interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_POSTMASK0>;
		mediatek,larb = <&smi_larb0>;
		mediatek,smi-id = <0>;
		iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>;
	};

	dsi0: dsi@1400e000 {
		compatible = "mediatek,dsi0",
					"mediatek,mt6885-dsi";
		reg = <0 0x1400e000 0 0x1000>;
		interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_DSI0>,
			<&dispsys_config MM_DSI_DSI0>,
			<&mipi_tx_config0>;
		clock-names = "engine", "digital", "hs";
		phys = <&mipi_tx_config0>;
		phy-names = "dphy";
	};

	dsi_te: dsi_te {
		compatible = "mediatek, dsi_te-eint";
		status = "disabled";
	};

	mdp_rdma4@1400f000 {
		compatible = "mediatek,mdp_rdma4";
		reg = <0 0x1400f000 0 0x1000>;
	};

	mdp_aal4: mdp_aal4@14010000 {
		compatible = "mediatek,mdp_aal4",
					"mediatek,mt6885-dmdp-aal";
		reg = <0 0x14010000 0 0x1000>;
		interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_MDP_AAL4>;
		clock-names = "DRE3_AAL0";
	};

	mdp_hdr4@14011000 {
		compatible = "mediatek,mdp_hdr4";
		reg = <0 0x14011000 0 0x1000>;
	};

	mdp_rsz4@14012000 {
		compatible = "mediatek,mdp_rsz4";
		reg = <0 0x14012000 0 0x1000>;
	};

	mdp_tdshp4@14013000 {
		compatible = "mediatek,mdp_tdshp4";
		reg = <0 0x14013000 0 0x1000>;
	};

	reserved@14014000 {
		compatible = "mediatek,reserved";
		reg = <0 0x14014000 0 0x1000>;
	};

	disp_merge0: disp_merge@14015000 {
		compatible = "mediatek,disp_merge0",
					"mediatek,mt6885-disp-merge";
		reg = <0 0x14015000 0 0x1000>;
		interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_MERGE0>;
	};

	disp_ovl1: disp_ovl@14100000 {
		compatible = "mediatek,disp_ovl1",
					"mediatek,mt6885-disp-ovl";
		reg = <0 0x14100000 0 0x1000>;
		interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_OVL1>;
		mediatek,larb = <&smi_larb1>;
		mediatek,smi-id = <1>;
		iommus = <&iommu0 M4U_PORT_L1_OVL_RDMA1>,
			 <&iommu0 M4U_PORT_L1_OVL_RDMA1_HDR>;
	};

	disp_ovl1_2l: disp_ovl@14101000 {
		compatible = "mediatek,disp_ovl1_2l",
					"mediatek,mt6885-disp-ovl";
		reg = <0 0x14101000 0 0x1000>;
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_OVL1_2L>;
		mediatek,larb = <&smi_larb0>;
		mediatek,smi-id = <0>;
		iommus = <&iommu0 M4U_PORT_L0_OVL_2L_RDMA1>,
			 <&iommu0 M4U_PORT_L0_OVL_2L_RDMA1_HDR>;
	};

	disp_ovl3_2l: disp_ovl@14102000 {
		compatible = "mediatek,disp_ovl3_2l",
					"mediatek,mt6885-disp-ovl";
		reg = <0 0x14102000 0 0x1000>;
		interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_OVL3_2L>;
		mediatek,larb = <&smi_larb0>;
		mediatek,smi-id = <0>;
		iommus = <&iommu0 M4U_PORT_L0_OVL_2L_RDMA3>,
			 <&iommu0 M4U_PORT_L0_OVL_2L_RDMA3_HDR>;
	};

	disp_rdma1@14103000 {
		compatible = "mediatek,disp_rdma1";
		reg = <0 0x14103000 0 0x1000>;
		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
	};

	reserved@14104000 {
		compatible = "mediatek,reserved";
		reg = <0 0x14104000 0 0x1000>;
	};

	disp_rdma5: disp_rdma@14105000 {
		compatible = "mediatek,disp_rdma5",
					"mediatek,mt6885-disp-rdma";
		reg = <0 0x14105000 0 0x1000>;
		interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_RDMA5>;
		mediatek,larb = <&smi_larb1>;
		mediatek,smi-id = <1>;
		iommus = <&iommu0 M4U_PORT_L1_DISP_FAKE1>;
	};

	disp_wdma1: disp_wdma@14106000 {
		compatible = "mediatek,disp_wdma1",
					"mediatek,mt6885-disp-wdma";
		reg = <0 0x14106000 0 0x1000>;
		interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_WDMA1>;
		mediatek,larb = <&smi_larb1>;
		mediatek,smi-id = <0>;
		iommus = <&iommu0 M4U_PORT_L1_DISP_WDMA1>;
	};

	disp_color1@14107000 {
		compatible = "mediatek,disp_color1";
		reg = <0 0x14107000 0 0x1000>;
		interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
	};

	disp_ccorr1@14108000 {
		compatible = "mediatek,disp_ccorr1";
		reg = <0 0x14108000 0 0x1000>;
		interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
	};

	disp_aal1@14109000 {
		compatible = "mediatek,disp_aal1";
		reg = <0 0x14109000 0 0x1000>;
		interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
	};

	disp_gamma1@1410a000 {
		compatible = "mediatek,disp_gamma1";
		reg = <0 0x1410a000 0 0x1000>;
		interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
	};

	disp_dither1@1410b000 {
		compatible = "mediatek,disp_dither1";
		reg = <0 0x1410b000 0 0x1000>;
		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
	};

	disp_rsz1@1410c000 {
		compatible = "mediatek,disp_rsz1";
		reg = <0 0x1410c000 0 0x1000>;
		interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>;
	};

	disp_postmask1@1410d000 {
		compatible = "mediatek,disp_postmask1";
		reg = <0 0x1410d000 0 0x1000>;
		interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
	};

	dsi1@1410e000 {
		compatible = "mediatek,dsi1";
		reg = <0 0x1410e000 0 0x1000>;
		interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>;
	};

	mdp_rdma5@1410f000 {
		compatible = "mediatek,mdp_rdma5";
		reg = <0 0x1410f000 0 0x1000>;
	};

	mdp_aal5@14110000 {
		compatible = "mediatek,mdp_aal5";
		reg = <0 0x14110000 0 0x1000>;
		interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
	};

	mdp_hdr5@14111000 {
		compatible = "mediatek,mdp_hdr5";
		reg = <0 0x14111000 0 0x1000>;
	};

	mdp_rsz5@14112000 {
		compatible = "mediatek,mdp_rsz5";
		reg = <0 0x14112000 0 0x1000>;
	};

	mdp_tdshp5@14113000 {
		compatible = "mediatek,mdp_tdshp5";
		reg = <0 0x14113000 0 0x1000>;
	};

	reserved@14114000 {
		compatible = "mediatek,reserved";
		reg = <0 0x14114000 0 0x1000>;
	};

	disp_merge1: disp_merge@14115000 {
		compatible = "mediatek,disp_merge1",
				"mediatek,mt6885-disp-merge";
		reg = <0 0x14115000 0 0x1000>;
		interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_MERGE1>;
	};

	dispsys_config: dispsys_config@14116000 {
		compatible = "mediatek,dispsys_config",
					"syscon",
					"mediatek,mt6885-mmsys";
		reg = <0 0x14116000 0 0x1000>;
		#clock-cells = <1>;
		iommus = <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>;
		mediatek,larb = <&smi_larb1>;
		fake-engine = <&smi_larb0 M4U_PORT_L0_DISP_FAKE0>,
				<&smi_larb1 M4U_PORT_L1_DISP_FAKE1>;

		clocks = <&scpsys SCP_SYS_DIS>,
				<&dispsys_config MM_26MHZ>,
				<&dispsys_config MM_DISP_MUTEX0>;
		clock-num = <3>;

		/* define threads, see mt6885-gce.h */
		mediatek,mailbox-gce = <&gce_mbox>;
		mboxes = <&gce_mbox 0 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 1 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 2 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 3 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
			<&gce_mbox 5 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
			<&gce_mbox 4 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 6 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox_sec 8 0 CMDQ_THR_PRIO_3>,
			<&gce_mbox_sec 9 0 CMDQ_THR_PRIO_3>,
			<&gce_mbox_sec 9 0 CMDQ_THR_PRIO_3>;
#else
			<&gce_mbox 4 0 CMDQ_THR_PRIO_4>,
			<&gce_mbox 6 0 CMDQ_THR_PRIO_3>;
#endif

		gce-client-names = "CLIENT_CFG0",
			"CLIENT_CFG1",
			"CLIENT_CFG2",
			"CLIENT_TRIG_LOOP0",
			"CLIENT_TRIG_LOOP1",
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
			"CLIENT_SUB_CFG0",
			"CLIENT_DSI_CFG0",
			"CLIENT_SEC_CFG0",
			"CLIENT_SEC_CFG1",
			"CLIENT_SEC_CFG2";
#else
			"CLIENT_SUB_CFG0",
			"CLIENT_DSI_CFG0";
#endif

		/* define subsys, see mt6885-gce.h */
		gce-subsys = <&gce_mbox 0x14000000 SUBSYS_1400XXXX>,
			<&gce_mbox 0x14010000 SUBSYS_1401XXXX>,
			<&gce_mbox 0x14020000 SUBSYS_1402XXXX>;

		/* define events, see mt6885-gce.h */
		gce-event-names = "disp_mutex0_eof",
			"disp_mutex1_eof",
			"disp_token_stream_dirty0",
			"disp_wait_dsi0_te",
			"disp_token_stream_eof0",
			"disp_dsi0_eof",
			"disp_token_esd_eof0",
			"disp_rdma0_eof0",
			"disp_wdma0_eof0",
			"disp_token_stream_block0",
			"disp_token_cabc_eof0",
			"disp_wdma0_eof2",
			"disp_wait_dp_intf0_te",
			"disp_dp_intf0_eof",
			"disp_mutex2_eof",
			"disp_wdma1_eof2",
			"disp_dsi0_sof0";

		gce-events = <&gce_mbox CMDQ_EVENT_DISP_STREAM_DONE_0>,
			<&gce_mbox CMDQ_EVENT_DP_INTF_FRAME_DONE_MM>,
			<&gce_mbox CMDQ_SYNC_TOKEN_CONFIG_DIRTY>,
			<&gce_mbox CMDQ_EVENT_DSI0_TE>,
			<&gce_mbox CMDQ_SYNC_TOKEN_STREAM_EOF>,
			<&gce_mbox CMDQ_EVENT_DSI0_FRAME_DONE>,
			<&gce_mbox CMDQ_SYNC_TOKEN_ESD_EOF>,
			<&gce_mbox CMDQ_EVENT_DISP_RDMA0_FRAME_DONE>,
			<&gce_mbox CMDQ_EVENT_DISP_WDMA0_FRAME_DONE>,
			<&gce_mbox CMDQ_SYNC_TOKEN_STREAM_BLOCK>,
			<&gce_mbox CMDQ_SYNC_TOKEN_CABC_EOF>,
			<&gce_mbox CMDQ_EVENT_DISP_WDMA0_FRAME_DONE>,
			<&gce_mbox CMDQ_EVENT_DP_INTF_SOF>,
			<&gce_mbox CMDQ_EVENT_DP_INTF_FRAME_DONE_MM>,
			<&gce_mbox CMDQ_EVENT_DP_INTF_FRAME_DONE_MM>,
			<&gce_mbox CMDQ_EVENT_DISP_WDMA1_FRAME_DONE>,
			<&gce_mbox CMDQ_EVENT_DSI0_SOF>;

		helper-name = "MTK_DRM_OPT_STAGE",
			"MTK_DRM_OPT_USE_CMDQ",
			"MTK_DRM_OPT_USE_M4U",
			"MTK_DRM_OPT_SODI_SUPPORT",
			"MTK_DRM_OPT_IDLE_MGR",
			"MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE",
			"MTK_DRM_OPT_IDLEMGR_BY_REPAINT",
			"MTK_DRM_OPT_IDLEMGR_ENTER_ULPS",
			"MTK_DRM_OPT_IDLEMGR_KEEP_LP11",
			"MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING",
			"MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ",
			"MTK_DRM_OPT_MET_LOG",
			"MTK_DRM_OPT_USE_PQ",
			"MTK_DRM_OPT_ESD_CHECK_RECOVERY",
			"MTK_DRM_OPT_ESD_CHECK_SWITCH",
			"MTK_DRM_OPT_PRESENT_FENCE",
			"MTK_DRM_OPT_RDMA_UNDERFLOW_AEE",
			"MTK_DRM_OPT_DSI_UNDERRUN_AEE",
			"MTK_DRM_OPT_HRT",
			"MTK_DRM_OPT_HRT_MODE",
			"MTK_DRM_OPT_DELAYED_TRIGGER",
			"MTK_DRM_OPT_OVL_EXT_LAYER",
			"MTK_DRM_OPT_AOD",
			"MTK_DRM_OPT_RPO",
			"MTK_DRM_OPT_DUAL_PIPE",
			"MTK_DRM_OPT_DC_BY_HRT",
			"MTK_DRM_OPT_OVL_WCG",
			"MTK_DRM_OPT_OVL_SBCH",
			"MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK",
			"MTK_DRM_OPT_MET",
			"MTK_DRM_OPT_REG_PARSER_RAW_DUMP",
			"MTK_DRM_OPT_VP_PQ",
			"MTK_DRM_OPT_GAME_PQ",
			"MTK_DRM_OPT_MMPATH",
			"MTK_DRM_OPT_HBM",
			"MTK_DRM_OPT_VDS_PATH_SWITCH",
			"MTK_DRM_OPT_LAYER_REC";

		helper-value = <0>, /*MTK_DRM_OPT_STAGE*/
			<1>, /*MTK_DRM_OPT_USE_CMDQ*/
			<1>, /*MTK_DRM_OPT_USE_M4U*/
			<0>, /*MTK_DRM_OPT_SODI_SUPPORT*/
			<1>, /*MTK_DRM_OPT_IDLE_MGR*/
			<0>, /*MTK_DRM_OPT_IDLEMGR_SWTCH_DECOUPLE*/
			<1>, /*MTK_DRM_OPT_IDLEMGR_BY_REPAINT*/
			<0>, /*MTK_DRM_OPT_IDLEMGR_ENTER_ULPS*/
			<0>, /*MTK_DRM_OPT_IDLEMGR_KEEP_LP11*/
			<0>, /*MTK_DRM_OPT_DYNAMIC_RDMA_GOLDEN_SETTING*/
			<1>, /*MTK_DRM_OPT_IDLEMGR_DISABLE_ROUTINE_IRQ*/
			<0>, /*MTK_DRM_OPT_MET_LOG*/
			<1>, /*MTK_DRM_OPT_USE_PQ*/
			<1>, /*MTK_DRM_OPT_ESD_CHECK_RECOVERY*/
			<1>, /*MTK_DRM_OPT_ESD_CHECK_SWITCH*/
			<1>, /*MTK_DRM_OPT_PRESENT_FENCE*/
			<0>, /*MTK_DRM_OPT_RDMA_UNDERFLOW_AEE*/
			<0>, /*MTK_DRM_OPT_DSI_UNDERRUN_AEE*/
			<1>, /*MTK_DRM_OPT_HRT*/
			<1>, /*MTK_DRM_OPT_HRT_MODE*/
			<0>, /*MTK_DRM_OPT_DELAYED_TRIGGER*/
			<1>, /*MTK_DRM_OPT_OVL_EXT_LAYER*/
			<0>, /*MTK_DRM_OPT_AOD*/
			<1>, /*MTK_DRM_OPT_RPO*/
			<0>, /*MTK_DRM_OPT_DUAL_PIPE*/
			<0>, /*MTK_DRM_OPT_DC_BY_HRT*/
			<1>, /*MTK_DRM_OPT_OVL_WCG*/
			<0>, /*MTK_DRM_OPT_OVL_SBCH*/
			<1>, /*MTK_DRM_OPT_COMMIT_NO_WAIT_VBLANK*/
			<0>, /*MTK_DRM_OPT_MET*/
			<0>, /*MTK_DRM_OPT_REG_PARSER_RAW_DUMP*/
			<0>, /*MTK_DRM_OPT_VP_PQ*/
			<0>, /*MTK_DRM_OPT_GAME_PQ*/
			<0>, /*MTK_DRM_OPT_MMPATH*/
			<0>, /*MTK_DRM_OPT_HBM*/
			<0>, /*MTK_DRM_OPT_VDS_PATH_SWITCH*/
			<0>; /*MTK_DRM_OPT_LAYER_REC*/
	};

	disp_mutex0: disp_mutex@14117000 {
		compatible = "mediatek,disp_mutex0",
					"mediatek,mt6885-disp-mutex";
		reg = <0 0x14117000 0 0x1000>;
		interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config MM_DISP_MUTEX0>;
	};

	smi_larb0: smi_larb0@14118000 {
		compatible = "mediatek,smi_larb0", "mediatek,smi_larb";
		reg = <0 0x14118000 0 0x1000>;
		mediatek,larb-id = <0>;
		interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_DIS>;
		clock-names = "scp-dis";
		mediatek,smi-id = <0>;
	};

	smi_larb1: smi_larb1@14119000 {
		compatible = "mediatek,smi_larb1", "mediatek,smi_larb";
		reg = <0 0x14119000 0 0x1000>;
		mediatek,larb-id = <1>;
		interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_DIS>;
		clock-names = "scp-dis";
		mediatek,smi-id = <1>;
	};

	smi_common: smi_common@1411f000 {
		compatible = "mediatek,smi_common";
		reg = <0 0x1411f000 0 0x1000>;
		clocks = <&scpsys SCP_SYS_DIS>,
			 <&dispsys_config MM_SMI_COMMON>,
			 <&dispsys_config MM_SMI_GALS>,
			 <&dispsys_config MM_SMI_INFRA>,
			 <&dispsys_config MM_SMI_IOMMU>;
		clock-names = "scp-dis",
			      "mm-comm", "mm-gals", "mm-infra", "mm-iommu";
		mediatek,smi-id = <21>;
		mediatek,smi-cnt = <32>;
		mmsys_config = <&dispsys_config>;
	};

	disp_smi_subcom@14120000 {
		compatible = "mediatek,disp_smi_subcom", "mediatek,smi_common";
		reg = <0 0x14120000 0 0x1000>;
		clocks = <&scpsys SCP_SYS_DIS>;
		clock-names = "scp-dis";
		mediatek,smi-id = <24>;
	};

	disp_smi_subcom1@14121000 {
		compatible = "mediatek,disp_smi_subcom1", "mediatek,smi_common";
		reg = <0 0x14121000 0 0x3000>;
		clocks = <&scpsys SCP_SYS_DIS>;
		clock-names = "scp-dis";
		mediatek,smi-id = <25>;
	};

	mdp_smi_common: mdp_smi_common@1f002000 {
		compatible = "mediatek,mdp_smi_common", "mediatek,smi_common";
		reg = <0 0x1f002000 0 0x1000>;
		clocks = <&scpsys SCP_SYS_MDP>,
			 <&mdpsys_config MDP_SMI1>, <&mdpsys_config MDP_SMI2>;
		clock-names = "scp-mdp", "mdp-smi1", "mdp-smi2";
		mediatek,smi-id = <22>;
	};

	smi_larb2: smi_larb2@1f003000 {
		compatible = "mediatek,smi_larb2", "mediatek,smi_larb";
		reg = <0 0x1f003000 0 0x1000>;
		mediatek,larb-id = <2>;
		interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_MDP>;
		clock-names = "scp-mdp";
		mediatek,smi-id = <2>;
	};

	smi_larb3: smi_larb3@1f004000 {
		compatible = "mediatek,smi_larb3", "mediatek,smi_larb";
		reg = <0 0x1f004000 0 0x1000>;
		mediatek,larb-id = <3>;
		interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_MDP>;
		clock-names = "scp-mdp";
		mediatek,smi-id = <3>;
	};

	sysram_smi_common@1f022000 {
		compatible = "mediatek,sysram_smi_common",
			     "mediatek,smi_common";
		reg = <0 0x1f022000 0 0x1000>;
		clocks = <&scpsys SCP_SYS_MDP>, <&mdpsys_config MDP_SMI0>;
		clock-names = "scp-mdp", "mdp-smi0";
		mediatek,smi-id = <23>;
	};

	mdp_smi_subcom@1f023000 {
		compatible = "mediatek,mdp_smi_subcom", "mediatek,smi_common";
		reg = <0 0x1f023000 0 0x1000>;
		clocks = <&scpsys SCP_SYS_MDP>;
		clock-names = "scp-mdp";
		mediatek,smi-id = <26>;
	};

	mdp_smi_subcom1@1f024000 {
		compatible = "mediatek,mdp_smi_subcom1", "mediatek,smi_common";
		reg = <0 0x1f024000 0 0x3000>;
		clocks = <&scpsys SCP_SYS_MDP>;
		clock-names = "scp-mdp";
		mediatek,smi-id = <27>;
	};

	mmdvfs_pmqos {
		compatible = "mediatek,mmdvfs_pmqos";
		larb_groups = <0 1 2 3 4 5 7 8 9 11 13 14 16 17 18 19 20>;
		larb0 = <8 7 7 7 7 8 8 8 7 7 7 9 8 7 7>;
		larb1 = <8 7 7 7 7 8 8 8 7 7 7 9 8 7 7>;
		larb2 = <7 7 8 8 8 8>;
		larb3 = <7 7 8 8 8 8>;
		larb4 = <6 7 8 7 7 7 7 7 7 6 7>;
		larb5 = <7 7 6 7 7 8 7 7>;
		larb7 = <7 8 8 8 7 7 7 7 7 7 8 8 7 8 8 7 7 7 7 7
			8 7 8 8 7 8 8>;
		larb8 = <7 8 8 8 7 7 7 7 7 7 8 8 7 8 8 7 7 7 7 7
			8 7 8 8 7 8 8>;
		larb9 = <7 7 7 7 7 7 8 8 8 8 7 7 8 9 8 6 6 7 7 7
			7 7 7 7 8 8 8 8 7>;
		larb11 = <7 7 7 7 7 7 8 8 8 8 7 7 8 9 8 6 6 7 7 7
			7 7 7 7 8 8 8 8 7>;
		larb13 = <7 8 8 8 8 8 8 8 8 7 8 7>;
		larb14 = <7 8 8 8 7 8>;
		larb16 = <8 8 7 7 8 7 7 7 8 8 8 8 8 8 8 8 7>;
		larb17 = <8 8 7 7 8 7 7 7 8 8 8 8 8 8 8 8 7>;
		larb18 = <8 8 7 7 8 7 7 7 8 8 8 8 8 8 8 8 7>;
		larb19 = <7 8 7 8>;
		larb20 = <7 7 8 8 6 7>;
		vcore-supply = <&mt_pmic_vgpu11_buck_reg>;
		/* include SMI common CCU */
		cam_larb = <13 14 16 17 18 23 24>;
		max_ostd_larb = <0 1>;
		max_ostd = <40>;
		comm_freq = "disp_freq", "mdp_freq";
		disp_step0 = <546 1 0 10>;
		disp_step1 = <416 1 0 11>;
		disp_step2 = <312 1 0 12>;
		disp_step3 = <249 1 0 13>;
		mdp_step0 = <594 1 1 14>;
		mdp_step1 = <416 1 1 11>;
		mdp_step2 = <312 1 1 12>;
		mdp_step3 = <273 1 1 15>;
		cam_step0 = <624 1 2 16>;
		cam_step1 = <499 1 2 17>;
		cam_step2 = <392 1 2 18>;
		cam_step3 = <312 1 2 12>;
		img_step0 = <624 1 3 16>;
		img_step1 = <416 1 3 11>;
		img_step2 = <343 1 3 19>;
		img_step3 = <273 1 3 15>;
		img2_step0 = <624 1 4 16>;
		img2_step1 = <416 1 4 11>;
		img2_step2 = <343 1 4 19>;
		img2_step3 = <273 1 4 15>;
		venc_step0 = <624 1 5 16>;
		venc_step1 = <416 1 5 11>;
		venc_step2 = <312 1 5 12>;
		venc_step3 = <273 1 5 15>;
		vdec_step0 = <546 1 6 10>;
		vdec_step1 = <416 1 6 11>;
		vdec_step2 = <312 1 6 12>;
		vdec_step3 = <249 1 6 13>;
		dpe_step0 = <546 1 7 10>;
		dpe_step1 = <458 1 7 20>;
		dpe_step2 = <364 1 7 21>;
		dpe_step3 = <312 1 7 12>;
		ipe_step0 = <546 1 8 10>;
		ipe_step1 = <416 1 8 11>;
		ipe_step2 = <312 1 8 12>;
		ipe_step3 = <273 1 8 15>;
		ccu_step0 = <499 1 9 17>;
		ccu_step1 = <392 1 9 18>;
		ccu_step2 = <364 1 9 21>;
		ccu_step3 = <312 1 9 12>;
		/* fmeter_mux_ids: Mapping to mux sequence in clocks */
		fmeter_mux_ids = <5 6 11 7 8 56 57 10 9>;
		vopp_steps = <0 1 2 3>;
		disp_freq = "disp_step0", "disp_step1",
				"disp_step2", "disp_step3";
		mdp_freq = "mdp_step0", "mdp_step1",
				"mdp_step2", "mdp_step3";
		cam_freq = "cam_step0", "cam_step1",
				"cam_step2", "cam_step3";
		img_freq = "img_step0", "img_step1",
				"img_step2", "img_step3";
		img2_freq = "img2_step0", "img2_step1",
				"img2_step2", "img2_step3";
		venc_freq = "venc_step0", "venc_step1",
				"venc_step2", "venc_step3";
		vdec_freq = "vdec_step0", "vdec_step1",
				"vdec_step2", "vdec_step3";
		dpe_freq = "dpe_step0", "dpe_step1",
				"dpe_step2", "dpe_step3";
		ipe_freq = "ipe_step0", "ipe_step1",
				"ipe_step2", "ipe_step3";
		ccu_freq = "ccu_step0", "ccu_step1",
				"ccu_step2", "ccu_step3";
		clocks = <&topckgen TOP_MUX_DISP>,		/* 0 */
			<&topckgen TOP_MUX_MDP>,		/* 1 */
			<&topckgen TOP_MUX_CAM>,		/* 2 */
			<&topckgen TOP_MUX_IMG1>,		/* 3 */
			<&topckgen TOP_MUX_IMG2>,		/* 4 */
			<&topckgen TOP_MUX_VENC>,		/* 5 */
			<&topckgen TOP_MUX_VDEC>,		/* 6 */
			<&topckgen TOP_MUX_DPE>,		/* 7 */
			<&topckgen TOP_MUX_IPE>,		/* 8 */
			<&topckgen TOP_MUX_CCU>,		/* 9 */
			<&topckgen TOP_MAINPLL_D4>,		/* 10 */
			<&topckgen TOP_UNIVPLL_D6>,		/* 11 */
			<&topckgen TOP_UNIVPLL_D4_D2>,		/* 12 */
			<&topckgen TOP_UNIVPLL_D5_D2>,		/* 13 */
			<&topckgen TOP_TVDPLL_CK>,		/* 14 */
			<&topckgen TOP_MAINPLL_D4_D2>,		/* 15 */
			<&topckgen TOP_UNIVPLL_D4>,		/* 16 */
			<&topckgen TOP_UNIVPLL_D5>,		/* 17 */
			<&topckgen TOP_MMPLL_D7>,		/* 18 */
			<&topckgen TOP_MMPLL_D4_D2>,		/* 19 */
			<&topckgen TOP_MMPLL_D6>,		/* 20 */
			<&topckgen TOP_MAINPLL_D6>,		/* 21 */
			<&topckgen TOP_MUX_DP>;		/* 22 */
		clock-names = "TOP_MUX_DISP",	/* 0 */
			"TOP_MUX_MDP",		/* 1 */
			"TOP_MUX_CAM",		/* 2 */
			"TOP_MUX_IMG1",		/* 3 */
			"TOP_MUX_IMG2",		/* 4 */
			"TOP_MUX_VENC",		/* 5 */
			"TOP_MUX_VDEC",		/* 6 */
			"TOP_MUX_DPE",		/* 7 */
			"TOP_MUX_IPE",		/* 8 */
			"TOP_MUX_CCU",		/* 9 */
			"TOP_MAINPLL_D4",	/* 10 */
			"TOP_UNIVPLL_D6",	/* 11 */
			"TOP_UNIVPLL_D4_D2",	/* 12 */
			"TOP_UNIVPLL_D5_D2",	/* 13 */
			"TOP_TVDPLL_CK",	/* 14 */
			"TOP_MAINPLL_D4_D2",	/* 15 */
			"TOP_UNIVPLL_D4",	/* 16 */
			"TOP_UNIVPLL_D5",	/* 17 */
			"TOP_MMPLL_D7",		/* 18 */
			"TOP_MMPLL_D4_D2",	/* 19 */
			"TOP_MMPLL_D6",		/* 20 */
			"TOP_MAINPLL_D6",	/* 21 */
			"TOP_MUX_DP";	/* 22 */
	};


	disp_dsc_wrap: disp_dsc_wrap@14124000 {
		compatible = "mediatek,disp_dsc_wrap",
					"mediatek,mt6885-disp-dsc";
		reg = <0 0x14124000 0 0x1000>;
		interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config  MM_DISP_DSC_WRAP>;
	};

	dp_intf: dp_intf@14125000 {
		compatible = "mediatek,dp_intf",
					"mediatek,mt6885-dp-intf";
		reg = <0 0x14125000 0 0x1000>;
		interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispsys_config  MM_DISP_DP_INTF>,
			<&dispsys_config MM_DP_INTF>,
			<&topckgen TOP_MUX_DP>,
			<&topckgen TOP_TVDPLL_D2>,
			<&topckgen TOP_TVDPLL_D4>,
			<&topckgen TOP_TVDPLL_D8>,
			<&topckgen TOP_TVDPLL_D16>,
			<&topckgen TOP_TVDPLL_CK>;
		clock-names = "hf_fmm_ck",
		  "hf_fdp_ck",
			"MUX_DP",
			"TVDPLL_D2",
			"TVDPLL_D4",
			"TVDPLL_D8",
			"TVDPLL_D16",
			"DPI_CK";
		phys = <&dp_tx>;
		phy-names = "dp_tx";
	};

	inlinerot@14126000 {
		compatible = "mediatek,inlinerot";
		reg = <0 0x14126000 0 0x1000>;
	};

	dp_tx: dp_tx@14800000 {
		compatible = "mediatek,dp_tx",
					"mediatek,mt6885-dp_tx";
		reg = <0 0x14800000 0 0x8000>;
		clocks = <&scpsys SCP_SYS_DP_TX>;
		clock-names = "dp_tx_faxi";
		interrupts = <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>;
	};

	mipi_tx_config0: mipi_tx_config@11e50000 {
		compatible = "mediatek,mipi_tx_config0",
					"mediatek,mt6885-mipi-tx";
		reg = <0 0x11e50000 0 0x1000>;
		clocks = <&clk26m>;
		#clock-cells = <0>;
		#phy-cells = <0>;
		clock-output-names = "mipi_tx0_pll";
	};

	mipi_tx_config1@11e60000 {
		compatible = "mediatek,mipi_tx_config1";
		reg = <0 0x11e60000 0 0x1000>;
	};

	seninf1@1a004000 {
		compatible = "mediatek,seninf1";
		reg = <0 0x1a004000 0 0x1000>;
	};

	seninf2@1a005000 {
		compatible = "mediatek,seninf2";
		reg = <0 0x1a005000 0 0x1000>;
	};

	seninf3@1a006000 {
		compatible = "mediatek,seninf3";
		reg = <0 0x1a006000 0 0x1000>;
	};

	seninf4@1a007000 {
		compatible = "mediatek,seninf4";
		reg = <0 0x1a007000 0 0x1000>;
	};

	seninf5@1a008000 {
		compatible = "mediatek,seninf5";
		reg = <0 0x1a008000 0 0x1000>;
	};

	seninf6@1a009000 {
		compatible = "mediatek,seninf6";
		reg = <0 0x1a009000 0 0x1000>;
	};

	seninf7@1a00a000 {
		compatible = "mediatek,seninf7";
		reg = <0 0x1a00a000 0 0x1000>;
	};

	seninf8@1a00b000 {
		compatible = "mediatek,seninf8";
		reg = <0 0x1a00b000 0 0x1000>;
	};

	seninf_top@1a004000 {
		compatible = "mediatek,seninf_top";
		reg = <0 0x1a004000 0 0x1000>;
#if 0
		interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_LOW>;
#endif

		clocks = <&scpsys SCP_SYS_MDP>,
			<&scpsys SCP_SYS_CAM>,
			<&camsys CAMSYS_MAIN_SENINF_CGPDN>,
			<&topckgen TOP_MUX_SENINF>,
			<&topckgen TOP_MUX_SENINF1>,
			<&topckgen TOP_MUX_SENINF2>,
			<&topckgen TOP_MUX_SENINF3>,
			<&topckgen TOP_MUX_CAMTG>,
			<&topckgen TOP_MUX_CAMTG2>,
			<&topckgen TOP_MUX_CAMTG3>,
			<&topckgen TOP_MUX_CAMTG4>,
			<&topckgen TOP_MUX_CAMTG5>,
			<&topckgen TOP_MUX_CAMTG6>,
			<&clk26m>,
			<&topckgen TOP_UNIVP_192M_D8>,
			<&topckgen TOP_UNIVPLL_D6_D8>,
			<&topckgen TOP_UNIVP_192M_D4>,
			<&topckgen TOP_F26M_CK_D2>,
			<&topckgen TOP_UNIVP_192M_D16>,
			<&topckgen TOP_UNIVP_192M_D32>;
		clock-names = "SCP_SYS_MDP",
			"SCP_SYS_CAM",
			"CAMSYS_SENINF_CGPDN",
			"TOP_MUX_SENINF",
			"TOP_MUX_SENINF1",
			"TOP_MUX_SENINF2",
			"TOP_MUX_SENINF3",
			"TOP_MUX_CAMTG",
			"TOP_MUX_CAMTG2",
			"TOP_MUX_CAMTG3",
			"TOP_MUX_CAMTG4",
			"TOP_MUX_CAMTG5",
			"TOP_MUX_CAMTG6",
			"TOP_CLK26M",
			"TOP_UNIVP_192M_D8",
			"TOP_UNIVPLL_D6_D8",
			"TOP_UNIVP_192M_D4",
			"TOP_F26M_CK_D2",
			"TOP_UNIVP_192M_D16",
			"TOP_UNIVP_192M_D32";
	};

	kd_camera_hw1:kd_camera_hw1@1a004000 {
		compatible = "mediatek,imgsensor";
	};

	camsys: camsys@1a000000 {
		compatible = "mediatek,camsys", "syscon";
		reg = <0 0x1a000000 0 0x10000>;
		#clock-cells = <1>;
		/* Camera CCF */
		clocks = <&scpsys SCP_SYS_MDP>,
				<&scpsys SCP_SYS_CAM>,
				<&scpsys SCP_SYS_CAM_RAWA>,
				<&scpsys SCP_SYS_CAM_RAWB>,
				<&scpsys SCP_SYS_CAM_RAWC>,
				<&camsys CAMSYS_MAIN_CAM_CGPDN>,
				<&camsys CAMSYS_MAIN_CAMTG_CGPDN>,
				<&camsys CAMSYS_MAIN_CAMSV0_CGPDN>,
				<&camsys CAMSYS_MAIN_CAMSV1_CGPDN>,
				<&camsys CAMSYS_MAIN_CAMSV2_CGPDN>,
				<&camsys CAMSYS_MAIN_CAMSV3_CGPDN>,
				<&camsys CAMSYS_MAIN_LARB13_CGPDN>,
				<&camsys CAMSYS_MAIN_LARB14_CGPDN>,
				<&camsys CAMSYS_MAIN_LARB15_CGPDN>,
				<&camsys CAMSYS_MAIN_CCU0_CGPDN>,
				<&camsys CAMSYS_MAIN_SENINF_CGPDN>,
				<&camsys_rawa CAMSYS_RAWA_LARBX_CGPDN>,
				<&camsys_rawa CAMSYS_RAWA_CAM_CGPDN>,
				<&camsys_rawa CAMSYS_RAWA_CAMTG_CGPDN>,
				<&camsys_rawb CAMSYS_RAWB_LARBX_CGPDN>,
				<&camsys_rawb CAMSYS_RAWB_CAM_CGPDN>,
				<&camsys_rawb CAMSYS_RAWB_CAMTG_CGPDN>,
				<&camsys_rawc CAMSYS_RAWC_LARBX_CGPDN>,
				<&camsys_rawc CAMSYS_RAWC_CAM_CGPDN>,
				<&camsys_rawc CAMSYS_RAWC_CAMTG_CGPDN>,
				<&topckgen TOP_MUX_CCU>,
				<&topckgen TOP_MUX_CAMTM>;
		clock-names = "ISP_SCP_SYS_MDP",
				"ISP_SCP_SYS_CAM",
				"ISP_SCP_SYS_RAWA",
				"ISP_SCP_SYS_RAWB",
				"ISP_SCP_SYS_RAWC",
				"CAMSYS_CAM_CGPDN",
				"CAMSYS_CAMTG_CGPDN",
				"CAMSYS_CAMSV0_CGPDN",
				"CAMSYS_CAMSV1_CGPDN",
				"CAMSYS_CAMSV2_CGPDN",
				"CAMSYS_CAMSV3_CGPDN",
				"CAMSYS_LARB13_CGPDN",
				"CAMSYS_LARB14_CGPDN",
				"CAMSYS_LARB15_CGPDN",
				"CAMSYS_CCU0_CGPDN",
				"CAMSYS_SENINF_CGPDN",
				"CAMSYS_RAWALARB16_CGPDN",
				"CAMSYS_RAWACAM_CGPDN",
				"CAMSYS_RAWATG_CGPDN",
				"CAMSYS_RAWBLARB17_CGPDN",
				"CAMSYS_RAWBCAM_CGPDN",
				"CAMSYS_RAWBTG_CGPDN",
				"CAMSYS_RAWCLARB18_CGPDN",
				"CAMSYS_RAWCCAM_CGPDN",
				"CAMSYS_RAWCTG_CGPDN",
				"TOPCKGEN_TOP_MUX_CCU",
				"TOPCKGEN_TOP_MUX_CAMTM";
	};

	smi_larb13: smi_larb13@1a001000 {
		compatible = "mediatek,smi_larb13", "mediatek,smi_larb";
		reg = <0 0x1a001000 0 0x1000>;
		mediatek,larb-id = <13>;
		interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_CAM>,
			 <&camsys CAMSYS_MAIN_LARB13_CGPDN>;
		clock-names = "scp-cam", "cam-larb13";
		mediatek,smi-id = <13>;
	};

	smi_larb14: smi_larb14@1a002000 {
		compatible = "mediatek,smi_larb14", "mediatek,smi_larb";
		reg = <0 0x1a002000 0 0x1000>;
		mediatek,larb-id = <14>;
		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_CAM>,
			 <&camsys CAMSYS_MAIN_LARB14_CGPDN>;
		clock-names = "scp-cam", "cam-larb14";
		mediatek,smi-id = <14>;
	};

	smi_larb15: smi_larb15@1a003000 {
		compatible = "mediatek,smi_larb15", "mediatek,smi_larb";
		reg = <0 0x1a003000 0 0x1000>;
		mediatek,larb-id = <15>;
		clocks = <&scpsys SCP_SYS_CAM>,
			 <&camsys CAMSYS_MAIN_LARB15_CGPDN>;
		clock-names = "scp-cam", "cam-larb15";
		mediatek,smi-id = <15>;
	};

	cam_smi_subcom@1a00c000 {
		compatible = "mediatek,cam_smi_subcom", "mediatek,smi_common";
		reg = <0 0x1a00c000 0 0x1000>;
		clocks = <&scpsys SCP_SYS_CAM>;
		clock-names = "scp-cam";
		mediatek,smi-id = <29>;
	};

	cam_smi_subcom1@1a00d000 {
		compatible = "mediatek,cam_smi_subcom1", "mediatek,smi_common";
		reg = <0 0x1a00d000 0 0x1000>;
		clocks = <&scpsys SCP_SYS_CAM>;
		clock-names = "scp-cam";
		mediatek,smi-id = <30>;
	};

	cam_smi_subcom2@1a00e000 {
		compatible = "mediatek,cam_smi_subcom2", "mediatek,smi_common";
		reg = <0 0x1a00e000 0 0x1000>;
		clocks = <&scpsys SCP_SYS_CAM>;
		clock-names = "scp-cam";
		mediatek,smi-id = <31>;
	};

	smi_larb16: smi_larb16@1a00f000 {
		compatible = "mediatek,smi_larb16", "mediatek,smi_larb";
		reg = <0 0x1a00f000 0 0x1000>;
		mediatek,larb-id = <16>;
		interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_CAM_RAWA>,
			 <&camsys_rawa CAMSYS_RAWA_LARBX_CGPDN>;
		clock-names = "scp-cam-rawa", "cam-rawa-larb";
		mediatek,smi-id = <16>;
	};

	smi_larb17: smi_larb17@1a010000 {
		compatible = "mediatek,smi_larb17", "mediatek,smi_larb";
		reg = <0 0x1a010000 0 0x1000>;
		mediatek,larb-id = <17>;
		interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_CAM_RAWB>,
			 <&camsys_rawb CAMSYS_RAWB_LARBX_CGPDN>;
		clock-names = "scp-cam-rawb", "cam-rawb-larb";
		mediatek,smi-id = <17>;
	};

	smi_larb18: smi_larb18@1a011000 {
		compatible = "mediatek,smi_larb18", "mediatek,smi_larb";
		reg = <0 0x1a011000 0 0x1000>;
		mediatek,larb-id = <18>;
		interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_CAM_RAWC>,
			 <&camsys_rawc CAMSYS_RAWC_LARBX_CGPDN>;
		clock-names = "scp-cam-rawc", "cam-rawc-larb";
		mediatek,smi-id = <18>;
	};

	camsys_rawa: camsys_rawa@1a04f000 {
		compatible = "mediatek,camsys_rawa", "syscon";
		reg = <0 0x1a04f000 0 0x1000>;
		#clock-cells = <1>;
	};

	camsys_rawb: camsys_rawb@1a06f000 {
		compatible = "mediatek,camsys_rawb", "syscon";
		reg = <0 0x1a06f000 0 0x1000>;
		#clock-cells = <1>;
	};

	camsys_rawc: camsys_rawc@1a08f000 {
		compatible = "mediatek,camsys_rawc", "syscon";
		reg = <0 0x1a08f000 0 0x1000>;
		#clock-cells = <1>;
	};

	cam1_inner@1a038000 {
		compatible = "mediatek,cam1_inner";
		reg = <0 0x1a038000 0 0x8000>;
	};

	cam2_inner@1a058000 {
		compatible = "mediatek,cam2_inner";
		reg = <0 0x1a058000 0 0x8000>;
	};

	cam3_inner@1a078000 {
		compatible = "mediatek,cam3_inner";
		reg = <0 0x1a078000 0 0x8000>;
	};

	cam1@1a030000 {
		compatible = "mediatek,cam1";
		reg = <0 0x1a030000 0 0x8000>;
		interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
	};

	cam2@1a050000 {
		compatible = "mediatek,cam2";
		reg = <0 0x1a050000 0 0x8000>;
		interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>;
	};

	cam3@1a070000 {
		compatible = "mediatek,cam3";
		reg = <0 0x1a070000 0 0x8000>;
		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>;
	};

	camsv1@1a090000 {
		compatible = "mediatek,camsv1";
		reg = <0 0x1a090000 0 0x1000>;
		interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>;
	};

	camsv2@1a091000 {
		compatible = "mediatek,camsv2";
		reg = <0 0x1a091000 0 0x1000>;
		interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>;
	};

	camsv3@1a092000 {
		compatible = "mediatek,camsv3";
		reg = <0 0x1a092000 0 0x1000>;
		interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>;
	};

	camsv4@1a093000 {
		compatible = "mediatek,camsv4";
		reg = <0 0x1a093000 0 0x1000>;
		interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>;
	};

	camsv5@1a094000 {
		compatible = "mediatek,camsv5";
		reg = <0 0x1a094000 0 0x1000>;
		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
	};

	camsv6@1a095000 {
		compatible = "mediatek,camsv6";
		reg = <0 0x1a095000 0 0x1000>;
		interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
	};

	camsv7@1a096000 {
		compatible = "mediatek,camsv7";
		reg = <0 0x1a096000 0 0x1000>;
		interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
	};

	camsv8@1a097000 {
		compatible = "mediatek,camsv8";
		reg = <0 0x1a097000 0 0x1000>;
		interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>;
	};

	imgsys_config: imgsys_config@15020000 {
		compatible = "mediatek,imgsys", "syscon";
		reg = <0 0x15020000 0 0x1000>;
		#clock-cells = <1>;
		clocks =
				<&imgsys_config IMGSYS1_LARB9_CGPDN>,
				<&imgsys_config IMGSYS1_DIP_CGPDN>,
				<&imgsys2_config IMGSYS2_LARB11_CGPDN>,
				<&imgsys2_config IMGSYS2_DIP_CGPDN>,
				<&imgsys_config IMGSYS1_MSS_CGPDN>,
				<&imgsys_config IMGSYS1_MFB_CGPDN>;
		clock-names =
				"DIP_CG_IMG_LARB9",
				"DIP_CG_IMG_DIP",
				"DIP_CG_IMG_LARB11",
				"DIP_CG_IMG_DIP2",
				"DIP_CG_IMG_DIP_MSS",
				"DIP_CG_IMG_MFB_DIP";
	};

	dip_a0@15021000 {
		compatible = "mediatek,dip1";
		reg = <0 0x15021000 0 0xc000>;
		interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
	};

	dip_a1@15022000 {
		compatible = "mediatek,dip_a1";
		reg = <0 0x15022000 0 0x1000>;
	};

	dip_a2@15023000 {
		compatible = "mediatek,dip_a2";
		reg = <0 0x15023000 0 0x1000>;
	};

	dip_a3@15024000 {
		compatible = "mediatek,dip_a3";
		reg = <0 0x15024000 0 0x1000>;
	};

	dip_a4@15025000 {
		compatible = "mediatek,dip_a4";
		reg = <0 0x15025000 0 0x1000>;
	};

	dip_a5@15026000 {
		compatible = "mediatek,dip_a5";
		reg = <0 0x15026000 0 0x1000>;
	};

	dip_a6@15027000 {
		compatible = "mediatek,dip_a6";
		reg = <0 0x15027000 0 0x1000>;
	};

	dip_a7@15028000 {
		compatible = "mediatek,dip_a7";
		reg = <0 0x15028000 0 0x1000>;
	};

	dip_a8@15029000 {
		compatible = "mediatek,dip_a8";
		reg = <0 0x15029000 0 0x1000>;
	};

	dip_a9@1502a000 {
		compatible = "mediatek,dip_a9";
		reg = <0 0x1502a000 0 0x1000>;
	};

	dip_a10@1502b000 {
		compatible = "mediatek,dip_a10";
		reg = <0 0x1502b000 0 0x1000>;
	};

	dip_a11@1502c000 {
		compatible = "mediatek,dip_a11";
		reg = <0 0x1502c000 0 0x1000>;
	};

	camera_af_hw_node: camera_af_hw_node {
		compatible = "mediatek,camera_af_lens";
	};

	flashlight_core: flashlight_core {
		compatible = "mediatek,flashlight_core";
	};

	flashlights_mt6360: flashlights_mt6360 {
		compatible = "mediatek,flashlights_mt6360";
		decouple = <1>;
		channel@1 {
			type = <0>;
			ct = <0>;
			part = <0>;
		};
		channel@2 {
			type = <0>;
			ct = <1>;
			part = <0>;
		};
	};

	smi_larb9: smi_larb9@1502e000 {
		compatible = "mediatek,smi_larb9", "mediatek,smi_larb";
		reg = <0 0x1502e000 0 0x1000>;
		mediatek,larb-id = <9>;
		interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_ISP>,
			 <&imgsys_config IMGSYS1_LARB9_CGPDN>;
		clock-names = "scp-isp", "img1-larb9";
		mediatek,smi-id = <9>;
	};

	smi_larb10@1502f000 {
		compatible = "mediatek,smi_larb10", "mediatek,smi_larb";
		reg = <0 0x1502f000 0 0x1000>;
		mediatek,larb-id = <10>;
		clocks = <&scpsys SCP_SYS_ISP>;
		clock-names = "scp-isp";
		mediatek,smi-id = <10>;
	};

	mssdl@15012000 {
		compatible = "mediatek,mssdl";
		reg = <0 0x15012000 0 0x1000>;
		interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
	};

	wpe_a@15011000 {
		compatible = "mediatek,wpe_a";
		reg = <0 0x15011000 0 0x1000>;
		interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>;
		clocks =
				<&imgsys_config IMGSYS1_LARB9_CGPDN>,
				<&imgsys_config IMGSYS1_WPE_CGPDN>;
		clock-names =
				"WPE_CLK_IMG_LARB9",
				"WPE_CLK_IMG_WPE_A";
	};

	wpe_b@15811000 {
		compatible = "mediatek,wpe_b";
		reg = <0 0x15811000 0 0x1000>;
		interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
		clocks =
				<&imgsys2_config IMGSYS2_LARB11_CGPDN>,
				<&imgsys2_config IMGSYS2_WPE_CGPDN>;
		clock-names =
				"WPE_CLK_IMG_LARB11",
				"WPE_CLK_IMG_WPE_B";
	};

	msfdl@15010000 {
		compatible = "mediatek,msfdl";
		reg = <0 0x15010000 0 0x1000>;
		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
	};

	mss@15012000 {
		compatible = "mediatek,mss";
		reg = <0 0x15012000 0 0x1000>;
		interrupts = <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>;
		mboxes = <&gce_mbox_m 19 0 CMDQ_THR_PRIO_1>;
		mss_frame_done =
		/bits/ 16 <CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_23>;
		mss_token =
		/bits/ 16 <CMDQ_SYNC_TOKEN_MSS>;
	};

	msf@15010000 {
		compatible = "mediatek,msf";
		reg = <0 0x15010000 0 0x1000>;
		interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
		mboxes = <&gce_mbox_m 20 0 CMDQ_THR_PRIO_1>;
		msf_frame_done =
		/bits/ 16 <CMDQ_EVENT_IMG1_EVENT_TX_FRAME_DONE_21>;
		msf_token =
		/bits/ 16 <CMDQ_SYNC_TOKEN_MSF>;
		clocks =
				<&imgsys_config IMGSYS1_LARB9_CGPDN>,
				<&imgsys_config IMGSYS1_MSS_CGPDN>,
				<&imgsys_config IMGSYS1_MFB_CGPDN>;
		clock-names =
				"MFB_CG_IMG1_LARB9",
				"MFB_CG_IMG1_MSS",
				"MFB_CG_IMG1_MFB";
	};

	imgsys_mfb@15020000 {
		compatible = "mediatek,imgsys_mfb";
		reg = <0 0x15020000 0 0x1000>;
	};

	imgsys2_config: imgsys2_config@15820000 {
		compatible = "mediatek,imgsys2", "syscon";
		reg = <0 0x15820000 0 0x1000>;
		#clock-cells = <1>;
	};

	dip_b0@15821000 {
		compatible = "mediatek,dip2";
		reg = <0 0x15821000 0 0xc000>;
		interrupts = <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>;
	};

	dip_b1@15822000 {
		compatible = "mediatek,dip_b1";
		reg = <0 0x15822000 0 0x1000>;
	};

	dip_b2@15823000 {
		compatible = "mediatek,dip_b2";
		reg = <0 0x15823000 0 0x1000>;
	};

	dip_b3@15824000 {
		compatible = "mediatek,dip_b3";
		reg = <0 0x15824000 0 0x1000>;
	};

	dip_b4@15825000 {
		compatible = "mediatek,dip_b4";
		reg = <0 0x15825000 0 0x1000>;
	};

	dip_b5@15826000 {
		compatible = "mediatek,dip_b5";
		reg = <0 0x15826000 0 0x1000>;
	};

	dip_b6@15827000 {
		compatible = "mediatek,dip_b6";
		reg = <0 0x15827000 0 0x1000>;
	};

	dip_b7@15828000 {
		compatible = "mediatek,dip_b7";
		reg = <0 0x15828000 0 0x1000>;
	};

	dip_b8@15829000 {
		compatible = "mediatek,dip_b8";
		reg = <0 0x15829000 0 0x1000>;
	};

	dip_b9@1582a000 {
		compatible = "mediatek,dip_b9";
		reg = <0 0x1582a000 0 0x1000>;
	};

	dip_b10@1582b000 {
		compatible = "mediatek,dip_b10";
		reg = <0 0x1582b000 0 0x1000>;
	};

	dip_b11@1582c000 {
		compatible = "mediatek,dip_b11";
		reg = <0 0x1582c000 0 0x1000>;
	};

	smi_larb11: smi_larb11@1582e000 {
		compatible = "mediatek,smi_larb11", "mediatek,smi_larb";
		reg = <0 0x1582e000 0 0x1000>;
		mediatek,larb-id = <11>;
		interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_ISP2>,
			 <&imgsys2_config IMGSYS2_LARB11_CGPDN>;
		clock-names = "scp-isp2", "img2-larb11";
		mediatek,smi-id = <11>;
	};

	smi_larb12@1582f000 {
		compatible = "mediatek,smi_larb12", "mediatek,smi_larb";
		reg = <0 0x1582f000 0 0x1000>;
		mediatek,larb-id = <12>;
		interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_ISP2>;
		clock-names = "scp-isp2";
		mediatek,smi-id = <12>;
	};

	mfb@15810000 {
		compatible = "mediatek,mfb";
		reg = <0 0x15810000 0 0x1000>;
	};

	mfb@15812000 {
		compatible = "mediatek,mfb";
		reg = <0 0x15812000 0 0x1000>;
	};

	venc_gcon: venc_gcon@17000000 {
		compatible = "mediatek,venc_gcon", "syscon";
		reg = <0 0x17000000 0 0x10000>;
		#clock-cells = <1>;
	};

	venc@17000000 {
		compatible = "mediatek,mt6885-vcodec-enc";
		reg = <0 0x17020000 0 0x2000>,
			<0 0x17820000 0 0x2000>;
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu0 M4U_PORT_L7_VENC_RD_COMV_DISP>;
#endif
		mediatek,larb = <&smi_larb7>;
		interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
		mediatek,vcu = <&vcu>;
		clocks =
			<&venc_gcon VENC_GCON_SET1_VENC>,
			<&venc_c1_gcon VENC_C1_GCON_SET1_VENC>;
		clock-names =
			"MT_CG_VENC0",
			"MT_CG_VENC1";
	};

	smi_larb7: smi_larb7@17010000 {
		compatible = "mediatek,smi_larb7", "mediatek,smi_larb";
		reg = <0 0x17010000 0 0x1000>;
		mediatek,larb-id = <7>;
		interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_VENC>,
			 <&venc_gcon VENC_GCON_SET1_VENC>;
		clock-names = "scp-venc", "venc-set1";
		mediatek,smi-id = <7>;
	};

	venc@17020000 {
		compatible = "mediatek,venc";
		reg = <0 0x17020000 0 0x10000>;
		interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
	};

	jpgenc@17030000 {
		compatible = "mediatek,jpgenc";
		reg = <0 0x17030000 0 0x10000>;
		mediatek,larb = <&smi_larb7>;
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu0 M4U_PORT_L7_JPGENC_Y_RDMA_DISP>;
#endif
		interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&venc_gcon VENC_GCON_SET2_JPGENC>;
		clock-names = "jpgenc";
		cshot-spec = <368>;
		port-id = <M4U_PORT_L7_JPGENC_Y_RDMA_DISP>,
				<M4U_PORT_L7_JPGENC_C_RDMA_DISP>,
				<M4U_PORT_L7_JPGENC_Q_TABLE_DISP>,
				<M4U_PORT_L7_JPGENC_BSDMA_DISP>;
	};

	jpgdec@17040000 {
		compatible = "mediatek,jpgdec";
		reg = <0 0x17040000 0 0x10000>,
		<0 0x17050000 0 0x10000>,
		<0 0x17840000 0 0x10000>;
		interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&venc_gcon VENC_GCON_SET3_JPGDEC>,
			<&venc_gcon  VENC_GCON_SET4_JPGDEC_C1>,
			<&venc_c1_gcon  VENC_C1_GCON_SET3_JPGDEC>;
		clock-names = "MT_CG_VENC_JPGDEC",
			"MT_CG_VENC_JPGDEC_C1",
			"MT_CG_VENC_C1_JPGDEC";
	};

	mbist@17060000 {
		compatible = "mediatek,mbist";
		reg = <0 0x17060000 0 0x10000>;
	};

	venc_c1_gcon: venc_c1_gcon@17800000 {
		compatible = "mediatek,venc_c1_gcon", "syscon";
		reg = <0 0x17800000 0 0x10000>;
		#clock-cells = <1>;
	};

	smi_larb8: smi_larb8@17810000 {
		compatible = "mediatek,smi_larb8", "mediatek,smi_larb";
		reg = <0 0x17810000 0 0x10000>;
		mediatek,larb-id = <8>;
		interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_VENC_CORE1>,
			 <&venc_c1_gcon VENC_C1_GCON_SET1_VENC>;
		clock-names = "scp-venc-c1", "venc-c1-set1";
		mediatek,smi-id = <8>;
	};

	dvs@1b100000 {
		compatible = "mediatek,dvs";
		reg = <0 0x1b100000 0 0x1000>;
		interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
		mboxes = <&gce_mbox_m 16 0 CMDQ_THR_PRIO_1>;
		EVENT_IPE_DVS_DONE = <CMDQ_EVENT_IPE_EVENT_TX_FRAME_DONE_3>;
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu0 M4U_PORT_L19_IPE_DVS_RDMA_DISP>;
#endif
		clocks =
				<&topckgen TOP_MUX_DPE>,
				<&ipesys_config IPESYS_DPE_CGPDN>;
		clock-names =
				"DPE_TOP_MUX",
				"DPE_CLK_IPE_DPE";
	};

	dvp@1b100800 {
		compatible = "mediatek,dvp";
		reg = <0 0x1b100000 0 0x1000>;
		interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
		EVENT_IPE_DVP_DONE = <CMDQ_EVENT_IPE_EVENT_TX_FRAME_DONE_4>;
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu0 M4U_PORT_L19_IPE_DVS_RDMA_DISP>;
#endif
		clocks =
				<&topckgen TOP_MUX_DPE>,
				<&ipesys_config IPESYS_DPE_CGPDN>;
		clock-names =
				"DPE_TOP_MUX",
				"DPE_CLK_IPE_DPE";
	};

	venc@17820000 {
		compatible = "mediatek,venc";
		reg = <0 0x17820000 0 0x10000>;
		interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>;
	};

	jpgenc@17830000 {
		compatible = "mediatek,jpgenc";
		reg = <0 0x17830000 0 0x10000>;
		mediatek,larb = <&smi_larb8>;
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu0 M4U_PORT_L8_JPGENC_Y_RDMA_MDP>;
#endif
		interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&venc_c1_gcon VENC_GCON_SET2_JPGENC>;
		clock-names = "jpgenc";
		cshot-spec = <368>;
		port-id = <M4U_PORT_L8_JPGENC_Y_RDMA_MDP>,
				<M4U_PORT_L8_JPGENC_C_RDMA_MDP>,
				<M4U_PORT_L8_JPGENC_Q_TABLE_MDP>,
				<M4U_PORT_L8_JPGENC_BSDMA_MDP>;
	};

	mbist@17860000 {
		compatible = "mediatek,mbist";
		reg = <0 0x17860000 0 0x10000>;
	};

	vcu: vcu@16000000 {
		compatible = "mediatek-vcu";
		mediatek,vcuid = <0>;
		mediatek,vcuname = "vcu";
		reg = <0 0x16000000 0 0x40000>,	    /* VDEC_BASE */
			 <0 0x17020000 0 0x10000>,  /* VENC_BASE */
			 <0 0x17820000 0 0x10000>;  /* VENC_C1_BASE */
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT_MDP>;
#endif
		mediatek,mailbox-gce = <&gce_mbox>;
		mediatek,dec_gce_th_num = <1>;
		mediatek,enc_gce_th_num = <2>;
		mboxes = <&gce_mbox 16 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 17 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox 18 0 CMDQ_THR_PRIO_1>,
			<&gce_mbox_sec 12 0 CMDQ_THR_PRIO_1>;
		gce-event-names = "venc_eof",
			"venc_eof_c1", "venc_wp_2nd_done", "venc_wp_3nd_done",
			"vdec_pic_start", "vdec_decode_done", "vdec_pause",
			"vdec_dec_error", "vdec_mc_busy_overflow_timeout",
			"vdec_all_dram_req_done", "vdec_ini_fetch_rdy",
			"vdec_process_flag", "vdec_search_start_code_done",
			"vdec_ref_reorder_done", "vdec_wp_tble_done",
			"vdec_count_sram_clr_done", "vdec_gce_cnt_op_threshold",
			"vdec_lat_pic_start", "vdec_lat_decode_done",
			"vdec_lat_pause", "vdec_lat_dec_error",
			"vdec_lat_mc_busy_overflow_timeout",
			"vdec_lat_all_dram_req_done", "vdec_lat_ini_fetch_rdy",
			"vdec_lat_process_flag",
			"vdec_lat_search_start_code_done",
			"vdec_lat_ref_reorder_done", "vdec_lat_wp_tble_done",
			"vdec_lat_count_sram_clr_done",
			"vdec_lat_gce_cnt_op_threshold";

		gce-events =  <&gce_mbox CMDQ_EVENT_VENC_CMDQ_FRAME_DONE>,
			<&gce_mbox CMDQ_EVENT_VENC_CMDQ_FRAME_DONE_C1>,
			<&gce_mbox CMDQ_EVENT_VENC_C0_CMDQ_WP_2ND_STAGE_DONE>,
			<&gce_mbox CMDQ_EVENT_VENC_C0_CMDQ_WP_3RD_STAGE_DONE>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_SOF_0>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_0>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_1>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_2>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_3>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_4>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_5>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_FRAME_DONE_6>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_0>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_1>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_2>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_3>,
			<&gce_mbox CMDQ_EVENT_VDEC_CORE0_7>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_SOF_0>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_0>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_1>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_2>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_3>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_4>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_5>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_FRAME_DONE_6>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_0>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_1>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_2>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_3>,
			<&gce_mbox CMDQ_EVENT_VDEC_LAT_7>;

		gce-gpr = <GCE_GPR_R10>, <GCE_GPR_R11>;
	};

	vdec@16000000 {
		compatible = "mediatek,mt6885-vcodec-dec";
		reg = <0 0x16000000 0 0x1000>,		/* VDEC_SYS */
			 <0 0x16020000 0 0x1000>,		/* VDEC_VLD */
			 <0 0x16025000 0 0x4000>,		/* VDEC_MISC */
			 <0 0x16010000 0 0x7000>, /* VDEC_LAT_MISC */
			 <0 0x16004000 0 0x1000>; /* VDEC_RACING_CTRL */
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT_MDP>;
#endif
		mediatek,larb = <&smi_larb4>;
		interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
		<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
		mediatek,vcu = <&vcu>;
		clocks =
			<&vdec_soc_gcon VDEC_SOC_GCON_VDEC_CKEN>,
			<&vdec_gcon VDEC_GCON_VDEC_CKEN>,
			<&vdec_soc_gcon VDEC_SOC_GCON_LAT_CKEN>;
		clock-names =
			"MT_CG_SOC",
			"MT_CG_VDEC0",
			"MT_CG_VDEC1";
	};

	vdec_gcon: vdec_gcon@1602f000 {
		compatible = "mediatek,vdec_gcon", "syscon";
		reg = <0 0x1602f000 0 0x10000>;
		#clock-cells = <1>;
	};

	smi_larb5: smi_larb5@1600d000 {
		compatible = "mediatek,smi_larb5", "mediatek,smi_larb";
		reg = <0 0x1600d000 0 0x1000>;
		mediatek,larb-id = <5>;
		interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_VDEC>,
			 <&vdec_soc_gcon VDEC_SOC_GCON_LARB1_CKEN>;
		clock-names = "scp-vdec", "vdec-soc-larb";
		mediatek,smi-id = <5>;
	};

	smi_larb6@1600e000 {
		compatible = "mediatek,smi_larb6", "mediatek,smi_larb";
		reg = <0 0x1600e000 0 0x1000>;
		mediatek,larb-id = <6>;
		clocks = <&scpsys SCP_SYS_VDEC2>;
		clock-names = "scp-vdec2";
		mediatek,smi-id = <6>;
	};

	vdec_soc_gcon: vdec_soc_gcon@1600f000 {
		compatible = "mediatek,vdec_soc_gcon", "syscon";
		reg = <0 0x1600f000 0 0x10000>;
		#clock-cells = <1>;
	};

	vdec: vdec@16020000 {
		compatible = "mediatek,vdec";
		reg = <0 0x16020000 0 0xd000>;
		interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
	};

	smi_larb4: smi_larb4@1602e000 {
		compatible = "mediatek,smi_larb4", "mediatek,smi_larb";
		reg = <0 0x1602e000 0 0x1000>;
		mediatek,larb-id = <4>;
		interrupts = <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_VDEC2>,
			 <&vdec_gcon VDEC_GCON_LARB1_CKEN>;
		clock-names = "scp-vdec2", "vdec-larb";
		mediatek,smi-id = <4>;
	};

	bt@18000000 {
		compatible = "mediatek,bt";
			/* conn_infra_rgu */
		reg = <0 0x18000000 0 0x1000>,
			/* conn_infra_cfg */
			<0 0x18001000 0 0x1000>,
			/* sys ram */
			<0 0x18050000 0 0x1000>,
			/* conn_host_csr_top */
			<0 0x18060000 0 0x1000>,
			/* bgfsys base */
			<0 0x18800000 0 0x1000>,
			/* bgfsys hw info base */
			<0 0x18812000 0 0x1000>,
			/* coninfra cfg ao */
			<0 0x10001000 0 0x1000>;
			/* coninfra ccif base */
			/* <0 0x10003300 0 0x100>, */
			/* bgf2md base */
			/* <0 0x1025C000 0 0x100>; */
			/* Rx Interrupt */
		interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>,
			/* Assert & FW log interrupt */
			<GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
	};

	consys: consys@18000000 {
		compatible = "mediatek,mt6885-consys";
			/* conn_infra_rgu */
		reg = <0 0x18000000 0 0x1000>,
			/* conn_infra_cfg */
			<0 0x18001000 0 0x1000>,
			/* conn_host_csr_top */
			<0 0x18060000 0 0x10000>,
			/* infracfg_ao */
			<0 0x10001000 0 0x1000>,
			/* TOP RGU */
			<0 0x10007000 0 0x1000>,
			/* SPM */
			<0 0x10006000 0 0x1000>,
			/* INFRACFG */
			<0 0x1020e000 0 0x1000>,
			/* conn_wt_slp_ctl_reg */
			<0 0x18005000 0 0x1000>,
			/* conn_afe_ctl */
			<0 0x18003000 0 0x1000>,
			/* conn_infra_sysram */
			<0 0x18050000 0 0x10000>,
			/* GPIO */
			<0 0x10005000 0 0x1000>,
			/* conn_rf_spi_mst_reg */
			<0 0x18004000 0 0x1000>,
			/* conn_semaphore */
			<0 0x18070000 0 0x10000>,
			/* conn_top_therm_ctl */
			<0 0x18002000 0 0x1000>,
			/* IOCFG_RT */
			<0 0x11ea0000 0 0x1000>,
			/* debug_ctrl */
			<0 0x1800f000 0 0x1000>;
		clocks = <&scpsys SCP_SYS_CONN>;
		clock-names = "conn";
	};

	ccu@1a101000 {
		compatible = "mediatek,ccu";
		reg = <0 0x1a101000 0 0x1000>;
		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&camsys CAMSYS_MAIN_CCU0_CGPDN>,
					<&topckgen TOP_MUX_CCU>,
					<&scpsys SCP_SYS_CAM>,
					<&scpsys SCP_SYS_MDP>;
		clock-names = "CCU_CLK_CAM_CCU",
						"CCU_CLK_TOP_MUX",
						"CAM_PWR",
						"MDP_PWR";
	};

	wifi: wifi@18000000 {
		compatible = "mediatek,wifi";
		reg = <0 0x18000000 0 0x700000>;
		interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
		memory-region = <&wifi_mem>;
	};

	fm: fm@18000000 {
		compatible = "mediatek,fm";
		family-id = <0x6885>;
		host-id = <0x6885>;
		conn-id = <0x2001>;
		interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>;
	};

	gps: gps@18C00000 {
		compatible = "mediatek,mt6885-gps";
		reg = <0 0x18000000 0 0x100000>,
			<0 0x18C00000 0 0x100000>,
			<0 0x10003304 0 0x4>,
			<0 0x1001C018 0 0xC>;
		reg-names = "conn_infra_base", "conn_gps_base",
			"status_dummy_cr", "tia_gps";
		interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>;
	};

	ipesys_config: ipesys_config@1b000000 {
		compatible = "mediatek,ipesys_config", "syscon";
		reg = <0 0x1b000000 0 0x1000>;
		#clock-cells = <1>;
	};

	fdvt@1b001000 {
		compatible = "mediatek,fdvt";
		reg = <0 0x1b001000 0 0x1000>;
		interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&ipesys_config IPESYS_FD_CGPDN>;
		clock-names = "FD_CLK_IPE_FD";
		mboxes = <&gce_mbox_m 17 0 CMDQ_THR_PRIO_1>,
			 <&gce_mbox_m_sec 11 0 CMDQ_THR_PRIO_1>;
		fdvt_frame_done = <CMDQ_EVENT_IPE_EVENT_TX_FRAME_DONE_0>;
	};

	fe@1b002000 {
		compatible = "mediatek,fe";
		reg = <0 0x1b002000 0 0x1000>;
		interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
	};

	hcp: hcp@0 {
		compatible = "mediatek,hcp";
	};

#ifdef CONFIG_VIDEO_MEDIATEK_ISP_RSC_SUPPORT
	rsc@1b003000 {
		compatible = "mediatek,rsc";
		mediatek,larb = <&smi_larb20>;
		mediatek,hcp = <&hcp>;
		reg = <0 0x1b003000 0 0x1000>;
		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
		mboxes = <&gce_mbox_m 18 0 CMDQ_THR_PRIO_1>;
		gce-event-names = "rsc_eof";
		gce-events = <&gce_mbox_m CMDQ_EVENT_RSC_EOF>;
		clocks = <&ipesys_config IPESYS_RSC_CGPDN>;
		clock-names = "RSC_CLK_IPE_RSC";
	};
#else
	rsc@1b003000 {
		compatible = "mediatek,rsc";
		mediatek,larb = <&smi_larb20>;
		reg = <0 0x1b003000 0 0x1000>;
		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
		mboxes = <&gce_mbox_m 18 0 CMDQ_THR_PRIO_1>;
		gce-event-names = "rsc_eof";
		gce-events = <&gce_mbox_m CMDQ_EVENT_RSC_EOF>;
		clocks = <&ipesys_config IPESYS_RSC_CGPDN>;
		clock-names = "RSC_CLK_IPE_RSC";
	};
#endif

	ipe_smi_subcom@1b00e000 {
		compatible = "mediatek,ipe_smi_subcom", "mediatek,smi_common";
		reg = <0 0x1b00e000 0 0x1000>;
		clocks = <&scpsys SCP_SYS_IPE>,
			 <&ipesys_config IPESYS_IPE_SMI_SUBCOM_CGPDN>;
		clock-names = "scp-ipe", "ipe-subcom";
		mediatek,smi-id = <28>;
	};

	smi_larb20: smi_larb20@1b00f000 {
		compatible = "mediatek,smi_larb20", "mediatek,smi_larb";
		reg = <0 0x1B00F000 0 0x1000>;
		mediatek,larb-id = <20>;
		interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_IPE>,
			 <&ipesys_config IPESYS_IPE_SMI_SUBCOM_CGPDN>,
			 <&ipesys_config IPESYS_LARB20_CGPDN>;
		clock-names = "scp-ipe", "ipe-subcom", "ipe-larb20";
		mediatek,smi-id = <20>;
	};

	depth@1b100000 {
		compatible = "mediatek,depth";
		reg = <0 0x1b100000 0 0x1000>;
		interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
	};

	smi_larb19: smi_larb19@1b10f000 {
		compatible = "mediatek,smi_larb19", "mediatek,smi_larb";
		reg = <0 0x1B10F000 0 0x1000>;
		mediatek,larb-id = <19>;
		interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&scpsys SCP_SYS_IPE>,
			 <&ipesys_config IPESYS_IPE_SMI_SUBCOM_CGPDN>,
			 <&ipesys_config IPESYS_LARB19_CGPDN>;
		clock-names = "scp-ipe", "ipe-subcom", "ipe-larb19";
		mediatek,smi-id = <19>;
	};

	mcupm@10300000 {
		compatible = "mediatek,mcupm";
		reg = <0 0x10301000 0 0xb800>,
			<0 0x1031fce0 0 0xa0>,
			<0 0x10300154 0 0x4>,
			<0 0x10300074 0 0x4>,
			<0 0x10300150 0 0x4>,
			<0 0x10300078 0 0x4>,
			<0 0x1031fd80 0 0xa0>,
			<0 0x10300154 0 0x4>,
			<0 0x10300074 0 0x4>,
			<0 0x10300150 0 0x4>,
			<0 0x10300078 0 0x4>,
			<0 0x1031fe20 0 0xa0>,
			<0 0x10300154 0 0x4>,
			<0 0x10300074 0 0x4>,
			<0 0x10300150 0 0x4>,
			<0 0x10300078 0 0x4>,
			<0 0x1031fec0 0 0xa0>,
			<0 0x10300154 0 0x4>,
			<0 0x10300074 0 0x4>,
			<0 0x10300150 0 0x4>,
			<0 0x10300078 0 0x4>,
			<0 0x1031ff60 0 0xa0>,
			<0 0x10300154 0 0x4>,
			<0 0x10300074 0 0x4>,
			<0 0x10300150 0 0x4>,
			<0 0x10300078 0 0x4>;

		reg-names = "mcupm_base",
			"mbox0_base",
			"mbox0_set",
			"mbox0_clr",
			"mbox0_send",
			"mbox0_recv",
			"mbox1_base",
			"mbox1_set",
			"mbox1_clr",
			"mbox1_send",
			"mbox1_recv",
			"mbox2_base",
			"mbox2_set",
			"mbox2_clr",
			"mbox2_send",
			"mbox2_recv",
			"mbox3_base",
			"mbox3_set",
			"mbox3_clr",
			"mbox3_send",
			"mbox3_recv",
			"mbox4_base",
			"mbox4_set",
			"mbox4_clr",
			"mbox4_send",
			"mbox4_recv";

		interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "mbox0",
			"mbox1",
			"mbox2",
			"mbox3",
			"mbox4";
	};

	odm: odm {
		compatible = "simple-bus";
		/* reserved for overlay by odm */
	};

	memory_ssmr_features: memory-ssmr-features {
		compatible = "mediatek,memory-ssmr-features";
		svp-region-based-size = <0 0x10000000>;
		iris-recognition-size = <0 0x10000000>;
		2d_fr-size = <0 0>;
		tui-size = <0 0x4000000>;
		wfd-size = <0 0x4000000>;
		prot-region-based-size = <0 0x8000000>;
		ta-elf-size = <0 0x1000000>;
		ta-stack-heap-size = <0 0x6000000>;
		sdsp-tee-sharedmem-size = <0 0x1000000>;
		sdsp-firmware-size = <0 0x1000000>;
	};


	/* IIC WRAP Center */
	imp_iic_wrap_c: imp_iic_wrap_c@11008000 {
		compatible = "mediatek,imp_iic_wrap_c", "syscon";
		reg = <0 0x11008000 0 0x1000>;
		#clock-cells = <1>;
	};
	/* IIC WRAP East */
	imp_iic_wrap_e: imp_iic_wrap_e@11cb2000 {
		compatible = "mediatek,imp_iic_wrap_e", "syscon";
		reg = <0 0x11cb2000 0 0x1000>;
		#clock-cells = <1>;
	};
	/* IIC WRAP North */
	imp_iic_wrap_n: imp_iic_wrap_n@11f02000 {
		compatible = "mediatek,imp_iic_wrap_n", "syscon";
		reg = <0 0x11f02000 0 0x1000>;
		#clock-cells = <1>;
	};
	/* IIC WRAP South */
	imp_iic_wrap_s: imp_iic_wrap_s@11d05000 {
		compatible = "mediatek,imp_iic_wrap_s", "syscon";
		reg = <0 0x11d05000 0 0x1000>;
		#clock-cells = <1>;
	};

	spi0: spi0@1100a000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x1100a000 0 0x100>;
		interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen TOP_MAINPLL_D5_D4>,
			 <&topckgen TOP_MUX_SPI>,
			 <&infracfg_ao INFRACFG_AO_SPI0_CG>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi1: spi1@11010000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11010000 0 0x100>;
		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen TOP_MAINPLL_D5_D4>,
			 <&topckgen TOP_MUX_SPI>,
			 <&infracfg_ao INFRACFG_AO_SPI1_CG>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi2: spi2@11012000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11012000 0 0x100>;
		interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen TOP_MAINPLL_D5_D4>,
			 <&topckgen TOP_MUX_SPI>,
			 <&infracfg_ao INFRACFG_AO_SPI2_CG>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi3: spi3@11013000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11013000 0 0x100>;
		interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen TOP_MAINPLL_D5_D4>,
			 <&topckgen TOP_MUX_SPI>,
			 <&infracfg_ao INFRACFG_AO_SPI3_CG>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi4: spi4@11018000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <2>;
		reg = <0 0x11018000 0 0x100>;
		interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen TOP_MAINPLL_D5_D4>,
			 <&topckgen TOP_MUX_SPI>,
			 <&infracfg_ao INFRACFG_AO_SPI4_CG>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi5: spi5@11019000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x11019000 0 0x100>;
		interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen TOP_MAINPLL_D5_D4>,
			 <&topckgen TOP_MUX_SPI>,
			 <&infracfg_ao INFRACFG_AO_SPI5_CG>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi6: spi6@1101d000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x1101d000 0 0x100>;
		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen TOP_MAINPLL_D5_D4>,
			 <&topckgen TOP_MUX_SPI>,
			 <&infracfg_ao INFRACFG_AO_SPI6_CK_CG>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	spi7: spi7@1101e000 {
		compatible = "mediatek,mt6765-spi";
		mediatek,pad-select = <0>;
		reg = <0 0x1101e000 0 0x100>;
		interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&topckgen TOP_MAINPLL_D5_D4>,
			 <&topckgen TOP_MUX_SPI>,
			 <&infracfg_ao INFRACFG_AO_SPI7_CK_CG>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
	};

	i2c_common: i2c_common {
		compatible = "mediatek,i2c_common";
		dma_support = /bits/ 8 <3>;
		idvfs = /bits/ 8 <1>;
		set_dt_div = /bits/ 8 <1>;
		check_max_freq = /bits/ 8 <1>;
		ver = /bits/ 8 <2>;
		set_ltiming = /bits/ 8 <1>;
		ext_time_config = /bits/ 16 <0x1801>;
		cnt_constraint = /bits/ 8 <1>;
		dma_ver = /bits/ 8 <1>;
	};

	i2c0: i2c0@11015000 {
		compatible = "mediatek,i2c";
		id = <0>;
		reg = <0 0x11015000 0 0x1000>,
			<0 0x11000080 0 0x80>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_c IMP_IIC_WRAP_C_AP_I2C0_CG_RO>,
			<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <204>;
		sda-gpio-id = <205>;
		gpio_start = <0x11F20000>;
		mem_len = <0x200>;
		eh_cfg = <0x20>;
		pu_cfg = <0x80>;
		rsel_cfg = <0xD0>;
		aed = <0x1a>;
	};

	i2c1: i2c1@11D00000 {
		compatible = "mediatek,i2c";
		id = <1>;
		reg = <0 0x11D00000 0 0x1000>,
			<0 0x11000100 0 0x80>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_s IMP_IIC_WRAP_S_AP_I2C1_CG_RO>,
			<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <118>;
		sda-gpio-id = <119>;
		gpio_start = <0x11D10000>;
		mem_len = <0x200>;
		eh_cfg = <0x40>;
		pu_cfg = <0xA0>;
		rsel_cfg = <0xE0>;
		aed = <0x1a>;
	};

	i2c2: i2c2@11D01000 {
		compatible = "mediatek,i2c";
		id = <2>;
		reg = <0 0x11D01000 0 0x1000>,
			<0 0x11000180 0 0x180>;
		interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_s IMP_IIC_WRAP_S_AP_I2C2_CG_RO>,
			<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <141>;
		sda-gpio-id = <142>;
		gpio_start = <0x11D10000>;
		mem_len = <0x200>;
		eh_cfg = <0x40>;
		pu_cfg = <0xB0>;
		rsel_cfg = <0xE0>;
		aed = <0x1a>;
		ch_offset_default = <0x100>;
		ch_offset_ccu = <0x200>;
	};

	i2c3: i2c3@11CB0000 {
		compatible = "mediatek,i2c";
		id = <3>;
		reg = <0 0x11CB0000 0 0x1000>,
			<0 0x11000300 0 0x80>;
		interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_e IMP_IIC_WRAP_E_AP_I2C3_CG_RO>,
			<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <160>;
		sda-gpio-id = <161>;
		gpio_start = <0x11EA0000>;
		mem_len = <0x200>;
		eh_cfg = <0x20>;
		pu_cfg = <0x70>;
		rsel_cfg = <0xB0>;
		aed = <0x1a>;
	};

	i2c4: i2c4@11D02000 {
		compatible = "mediatek,i2c";
		id = <4>;
		reg = <0 0x11D02000 0 0x1000>,
			<0 0x11000380 0 0x180>;
		interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_s IMP_IIC_WRAP_S_AP_I2C4_CG_RO>,
			<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <139>;
		sda-gpio-id = <140>;
		gpio_start = <0x11D10000>;
		mem_len = <0x200>;
		eh_cfg = <0x40>;
		pu_cfg = <0xB0>;
		rsel_cfg = <0xE0>;
		aed = <0x1a>;
		ch_offset_default = <0x100>;
		ch_offset_ccu = <0x200>;
	};

	i2c5: i2c5@11F00000 {
		compatible = "mediatek,i2c";
		id = <5>;
		reg = <0 0x11F00000 0 0x1000>,
			<0 0x11000500 0 0x80>;
		interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_n IMP_IIC_WRAP_N_AP_I2C5_CG_RO>,
			<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <202>;
		sda-gpio-id = <203>;
		gpio_start = <0x11F30000>;
		mem_len = <0x200>;
		eh_cfg = <0x30>;
		pu_cfg = <0x90>;
		rsel_cfg = <0xE0>;
		aed = <0x1a>;
	};

	i2c6: i2c6@11F01000 {
		compatible = "mediatek,i2c";
		id = <6>;
		reg = <0 0x11F01000 0 0x1000>,
			<0 0x11000580 0 0x80>;
		interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_n IMP_IIC_WRAP_N_AP_I2C6_CG_RO>,
			<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <200>;
		sda-gpio-id = <201>;
		gpio_start = <0x11F30000>;
		mem_len = <0x200>;
		eh_cfg = <0x30>;
		pu_cfg = <0x90>;
		rsel_cfg = <0xE0>;
		aed = <0x1a>;

		ext_buck_vmddr_mtk:ext_buck_vmddr@51 {
			compatible = "mediatek,ext_buck_vmddr";
			reg = <0x51>;
			regulator-name = "ext_buck_vmddr";
			regulator-min-microvolt = <300000>;
			regulator-max-microvolt = <1300000>;
			status = "okay";
		};
	};

	i2c7: i2c7@11D03000 {
		compatible = "mediatek,i2c";
		id = <7>;
		reg = <0 0x11D03000 0 0x1000>,
			<0 0x11000600 0 0x180>;
		interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_s IMP_IIC_WRAP_S_AP_I2C7_CG_RO>,
			<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <124>;
		sda-gpio-id = <125>;
		gpio_start = <0x11D10000>;
		mem_len = <0x200>;
		eh_cfg = <0x40>;
		pu_cfg = <0xB0>;
		rsel_cfg = <0xE0>;
		aed = <0x1a>;
	};

	i2c8: i2c8@11D04000 {
		compatible = "mediatek,i2c";
		id = <8>;
		reg = <0 0x11D04000 0 0x1000>,
			<0 0x11000780 0 0x180>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_s IMP_IIC_WRAP_S_AP_I2C8_CG_RO>,
			<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <122>;
		sda-gpio-id = <123>;
		gpio_start = <0x11D10000>;
		mem_len = <0x200>;
		eh_cfg = <0x40>;
		pu_cfg = <0xB0>;
		rsel_cfg = <0xE0>;
		aed = <0x1a>;
		ch_offset_default = <0x100>;
		ch_offset_ccu = <0x200>;
	};

	i2c9: i2c9@11CB1000 {
		compatible = "mediatek,i2c";
		id = <9>;
		reg = <0 0x11CB1000 0 0x1000>,
			<0 0x11000900 0 0x180>;
		interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_e IMP_IIC_WRAP_E_AP_I2C9_CG_RO>,
			<&infracfg_ao INFRACFG_AO_AP_DMA_CG>;
		clock-names = "main", "dma";
		clock-div = <5>;
		scl-gpio-id = <120>;
		sda-gpio-id = <121>;
		gpio_start = <0x11D10000>;
		mem_len = <0x200>;
		eh_cfg = <0x40>;
		pu_cfg = <0xB0>;
		rsel_cfg = <0xE0>;
		aed = <0x1a>;
		ch_offset_default = <0x100>;
		ch_offset_ccu = <0x200>;
	};

	i2c10: i2c10@11017000 {
		compatible = "mediatek,i2c";
		id = <10>;
		reg = <0 0x11017000 0 0x1000>;
		interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_c IMP_IIC_WRAP_C_AP_I2C10_CG_RO>;
		clock-names = "main";
		clock-div = <5>;
		aed = <0x1a>;
		mediatek,fifo_only;
	};

	i2c11: i2c11@1101A000 {
		compatible = "mediatek,i2c";
		id = <11>;
		reg = <0 0x1101A000 0 0x1000>;
		interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_c IMP_IIC_WRAP_C_AP_I2C11_CG_RO>;
		clock-names = "main";
		clock-div = <5>;
		aed = <0x1a>;
		mediatek,fifo_only;
	};

	i2c12: i2c12@1101B000 {
		compatible = "mediatek,i2c";
		id = <12>;
		reg = <0 0x1101B000 0 0x1000>;
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_c IMP_IIC_WRAP_C_AP_I2C12_CG_RO>;
		clock-names = "main";
		clock-div = <5>;
		aed = <0x1a>;
		mediatek,fifo_only;
	};

	i2c13: i2c13@11007000 {
		compatible = "mediatek,i2c";
		id = <13>;
		reg = <0 0x11007000 0 0x1000>;
		interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&imp_iic_wrap_c IMP_IIC_WRAP_C_AP_I2C13_CG_RO>;
		clock-names = "main";
		clock-div = <5>;
		aed = <0x1a>;
		mediatek,fifo_only;
	};

	goodix_fp: fingerprint {
		compatible = "mediatek,goodix-fp";
	};

	accdet: accdet {
		compatible = "mediatek,pmic-accdet";
	};

	mt6359_gauge {
		compatible = "mediatek,mt6359_gauge";
		gauge_name = "gauge";
		alias_name = "MT6359";
	};

	gauge_timer {
		compatible = "mediatek,gauge_timer_service";
	};

#if (CONFIG_MTK_GAUGE_VERSION == 30)
	#include "mediatek/bat_setting/mt6885_battery_prop.dtsi"
#endif

	spmi_bus: spmi@10027000 {
		compatible = "mediatek,mt6885-pmif";
		reg = <0 0x10027000 0 0x000e00>,
		      <0 0x10027f00 0 0x00008c>,
		      <0 0x10029000 0 0x000100>;
		reg-names = "pmif", "pmifmpu", "spmimst";
		interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "pmif_irq";
		irq_event_en = <0x0 0x0 0x00300000 0x00000100 0x0>;
		clocks = <&infracfg_ao INFRACFG_AO_PMIC_CG_AP>,
			<&infracfg_ao INFRACFG_AO_PMIC_CG_TMR>,
			<&topckgen TOP_MUX_PWRAP_ULPOSC>,
			<&topckgen TOP_OSC_D10>,
			<&clk26m>,
			<&topckgen TOP_MUX_SPMI_MST>,
			<&clk26m>,
			<&topckgen TOP_OSC_D10>;
		clock-names = "pmif_sys_ck",
			"pmif_tmr_ck",
			"pmif_clk_mux",
			"pmif_clk_osc_d10",
			"pmif_clk26m",
			"spmimst_clk_mux",
			"spmimst_clk26m",
			"spmimst_clk_osc_d10";
		swinf_ch_start = <4>;
		ap_swinf_no = <2>;
		#address-cells = <2>;
		#size-cells = <0>;
	};

	spmi_mpu@10027000 {
		compatible = "mediatek,spmi_mpu";
		reg = <0 0x10027000 0 0x0e00>;
	};

	apu0: apu0@19030000 {
		compatible = "mediatek,apu0", "syscon";
		reg = <0 0x19030000 0 0x1000>;
		#clock-cells = <1>;
	};

	apu1: apu1@19031000 {
		compatible = "mediatek,apu1", "syscon";
		reg = <0 0x19031000 0 0x1000>;
		#clock-cells = <1>;
	};

	apu2: apu1@19032000 {
		compatible = "mediatek,apu2", "syscon";
		reg = <0 0x19032000 0 0x1000>;
		#clock-cells = <1>;
	};

	apu_vcore: apu_vcore@19029000 {
		compatible = "mediatek,apu_vcore", "syscon";
		reg = <0 0x19029000 0 0x1000>;
		#clock-cells = <1>;
	};

	apu_conn: apu_conn@19020000 {
		compatible = "mediatek,apu_conn", "syscon";
		reg = <0 0x19020000 0 0x1000>;
		#clock-cells = <1>;
	};

	apu_mdla0: apu_mdla0@19034000 {
		compatible = "mediatek,apu_mdla0", "syscon";
		reg = <0 0x19034000 0 0x1000>;
		#clock-cells = <1>;
	};

	apu_mdla1: apu_mdla1@19038000 {
		compatible = "mediatek,apu_mdla1", "syscon";
		reg = <0 0x19038000 0 0x1000>;
		#clock-cells = <1>;
	};

	mtk_mdla: mdla@19036000 {
		compatible = "mtk,mdla";
		reg = <0 0x19034000 0 0x1000>,  /* dla0 config  */
		      <0 0x19036000 0 0x1000>,  /* dla0 command */
		      <0 0x19035000 0 0x1000>,  /* dla0 biu     */
		      <0 0x19038000 0 0x1000>,  /* dla1 config  */
		      <0 0x1903a000 0 0x1000>,  /* dla1 command */
		      <0 0x19039000 0 0x1000>,  /* dla1 biu     */
		      <0 0x1d000000 0 0x100000>,/* GSM,TODO      */
		      <0 0x19020000 0 0x40000>;  /* APU CONN     */
		interrupts = <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
	};

	apusys_mnoc@1906e000 {
		compatible = "mediatek,apusys_mnoc";
		reg = <0 0x1906e000 0 0x2000>,	/* mnoc reg  */
		      <0 0x19001000 0 0x1000>,	/* apusys int */
		      <0 0x19020000 0 0x1000>,	/* apu_conn_config */
		      <0 0x10001000 0 0x1000>,	/* slp prot 1 */
		      <0 0x10215000 0 0x1000>;	/* slp prot 2 */
		interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
	};

	apusys_reviser@19021000 {
		compatible = "mediatek,apusys_reviser";
		reg = <0 0x19021000 0 0x1000>,		/* apu_sctrl_reviser  */
			  <0 0x1d800000 0 0x200000>,	/* VLM          */
			  <0 0x1d000000 0 0x100000>,	/* TCM          */
			  <0 0x19001000 0 0x1000>;		/* apusys int */
		interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu2 M4U_PORT_L21_APU_FAKE_VLM>;
#endif
	};

	apusys_devapc@19064000 {
		compatible = "mediatek,apusys_devapc";
		reg = <0 0x19064000 0 0x1000>;
		interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
	};

	apusys_power {
		compatible = "mediatek,apusys_power";

		reg = <0 0x190f0000 0 0x1000>,
		      <0 0x190f1000 0 0x1000>,
		      <0 0x19029000 0 0x1000>;

		reg-names = "apusys_rpc",
			    "apusys_pcu",
			    "apusys_vcore";

		vvpu-supply = <&mt_pmic_vproc1_buck_reg>;
		vmdla-supply = <&mt_pmic_vproc2_buck_reg>;
		vsram_apu-supply = <&mt_pmic_vsram_md_ldo_reg>;
		vcore-supply = <&mt_pmic_vgpu11_buck_reg>;

		clocks = <&topckgen TOP_MUX_DSP>,	/* CONN */
			<&topckgen TOP_MUX_DSP1>,	/* VPU_CORE0 */
			<&topckgen TOP_MUX_DSP2>,	/* VPU_CORE1 */
			<&topckgen TOP_MUX_DSP3>,	/* VPU_CORE2 */
			<&topckgen TOP_MUX_DSP6>,	/* MDLA0 & MDLA1 */
			<&topckgen TOP_MUX_DSP7>,	/* IOMMU */
			<&topckgen TOP_MUX_IPU_IF>,	/* VCORE */
			<&apu0 APU0_JTAG_CG>,
			<&apu0 APU0_AXI_M_CG>,
			<&apu0 APU0_APU_CG>,
			<&apu1 APU1_JTAG_CG>,
			<&apu1 APU1_AXI_M_CG>,
			<&apu1 APU1_APU_CG>,
			<&apu2 APU2_JTAG_CG>,
			<&apu2 APU2_AXI_M_CG>,
			<&apu2 APU2_APU_CG>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG0>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG1>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG2>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG3>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG4>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG5>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG6>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG7>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG8>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG9>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG10>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG11>,
			<&apu_mdla0 APU_MDLA0_MDLA_CG12>,
			<&apu_mdla0 APU_MDLA0_APB_CG>,
			<&apu_mdla0 APU_MDLA0_AXI_M_CG>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG0>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG1>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG2>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG3>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG4>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG5>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG6>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG7>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG8>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG9>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG10>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG11>,
			<&apu_mdla1 APU_MDLA1_MDLA_CG12>,
			<&apu_mdla1 APU_MDLA1_APB_CG>,
			<&apu_mdla1 APU_MDLA1_AXI_M_CG>,
			<&apu_conn APU_CONN_AHB_CG>,
			<&apu_conn APU_CONN_AXI_CG>,
			<&apu_conn APU_CONN_ISP_CG>,
			<&apu_conn APU_CONN_CAM_ADL_CG>,
			<&apu_conn APU_CONN_IMG_ADL_CG>,
			<&apu_conn APU_CONN_EMI_26M_CG>,
			<&apu_conn APU_CONN_VPU_UDI_CG>,
			<&apu_conn APU_CONN_EDMA_0_CG>,
			<&apu_conn APU_CONN_EDMA_1_CG>,
			<&apu_conn APU_CONN_EDMAL_0_CG>,
			<&apu_conn APU_CONN_EDMAL_1_CG>,
			<&apu_conn APU_CONN_MNOC_CG>,
			<&apu_conn APU_CONN_TCM_CG>,
			<&apu_conn APU_CONN_MD32_CG>,
			<&apu_conn APU_CONN_IOMMU_0_CG>,
			<&apu_conn APU_CONN_IOMMU_1_CG>,
			<&apu_conn APU_CONN_MD32_32K_CG>,
			<&apu_vcore APUSYS_VCORE_AHB_CG>,
			<&apu_vcore APUSYS_VCORE_AXI_CG>,
			<&apu_vcore APUSYS_VCORE_ADL_CG>,
			<&apu_vcore APUSYS_VCORE_QOS_CG>,
			<&clk26m>,
			<&topckgen TOP_MAINPLL_D4_D2>,
			<&topckgen TOP_MAINPLL_D4_D4>,
			<&topckgen TOP_UNIVPLL_D4_D2>,
			<&topckgen TOP_UNIVPLL_D6_D2>,
			<&topckgen TOP_UNIVPLL_D6_D4>,
			<&topckgen TOP_MMPLL_D7>,
			<&topckgen TOP_MMPLL_D6>,
			<&topckgen TOP_MMPLL_D5>,
			<&topckgen TOP_MMPLL_D4>,
			<&topckgen TOP_UNIVPLL_D6>,
			<&topckgen TOP_UNIVPLL_D5>,
			<&topckgen TOP_UNIVPLL_D4>,
			<&topckgen TOP_UNIVPLL_D3>,
			<&topckgen TOP_MAINPLL_D6>,
			<&topckgen TOP_MAINPLL_D4>,
			<&topckgen TOP_MAINPLL_D3>,
			<&topckgen TOP_TVDPLL_CK>,
			<&topckgen TOP_TVDPLL_MAINPLL_D2_CK>,
			<&topckgen TOP_APUPLL_CK>,
			<&apmixed APMIXED_APUPLL>,
			<&scpsys SCP_SYS_VPU>;

		clock-names = "clk_top_dsp_sel",
			"clk_top_dsp1_sel",
			"clk_top_dsp2_sel",
			"clk_top_dsp3_sel",
			"clk_top_dsp6_sel",
			"clk_top_dsp7_sel",
			"clk_top_ipu_if_sel",
			"clk_apu_core0_jtag_cg",
			"clk_apu_core0_axi_m_cg",
			"clk_apu_core0_apu_cg",
			"clk_apu_core1_jtag_cg",
			"clk_apu_core1_axi_m_cg",
			"clk_apu_core1_apu_cg",
			"clk_apu_core2_jtag_cg",
			"clk_apu_core2_axi_m_cg",
			"clk_apu_core2_apu_cg",
			"clk_apu_mdla0_cg_b0",
			"clk_apu_mdla0_cg_b1",
			"clk_apu_mdla0_cg_b2",
			"clk_apu_mdla0_cg_b3",
			"clk_apu_mdla0_cg_b4",
			"clk_apu_mdla0_cg_b5",
			"clk_apu_mdla0_cg_b6",
			"clk_apu_mdla0_cg_b7",
			"clk_apu_mdla0_cg_b8",
			"clk_apu_mdla0_cg_b9",
			"clk_apu_mdla0_cg_b10",
			"clk_apu_mdla0_cg_b11",
			"clk_apu_mdla0_cg_b12",
			"clk_apu_mdla0_apb_cg",
			"clk_apu_mdla0_axi_m_cg",
			"clk_apu_mdla1_cg_b0",
			"clk_apu_mdla1_cg_b1",
			"clk_apu_mdla1_cg_b2",
			"clk_apu_mdla1_cg_b3",
			"clk_apu_mdla1_cg_b4",
			"clk_apu_mdla1_cg_b5",
			"clk_apu_mdla1_cg_b6",
			"clk_apu_mdla1_cg_b7",
			"clk_apu_mdla1_cg_b8",
			"clk_apu_mdla1_cg_b9",
			"clk_apu_mdla1_cg_b10",
			"clk_apu_mdla1_cg_b11",
			"clk_apu_mdla1_cg_b12",
			"clk_apu_mdla1_apb_cg",
			"clk_apu_mdla1_axi_m_cg",
			"clk_apu_conn_ahb_cg",
			"clk_apu_conn_axi_cg",
			"clk_apu_conn_isp_cg",
			"clk_apu_conn_cam_adl_cg",
			"clk_apu_conn_img_adl_cg",
			"clk_apu_conn_emi_26m_cg",
			"clk_apu_conn_vpu_udi_cg",
			"clk_apu_conn_edma_0_cg",
			"clk_apu_conn_edma_1_cg",
			"clk_apu_conn_edmal_0_cg",
			"clk_apu_conn_edmal_1_cg",
			"clk_apu_conn_mnoc_cg",
			"clk_apu_conn_tcm_cg",
			"clk_apu_conn_md32_cg",
			"clk_apu_conn_iommu_0_cg",
			"clk_apu_conn_iommu_1_cg",
			"clk_apu_conn_md32_32k_cg",
			"clk_apusys_vcore_ahb_cg",
			"clk_apusys_vcore_axi_cg",
			"clk_apusys_vcore_adl_cg",
			"clk_apusys_vcore_qos_cg",
			"clk_top_clk26m",
			"clk_top_mainpll_d4_d2",
			"clk_top_mainpll_d4_d4",
			"clk_top_univpll_d4_d2",
			"clk_top_univpll_d6_d2",
			"clk_top_univpll_d6_d4",
			"clk_top_mmpll_d7",
			"clk_top_mmpll_d6",
			"clk_top_mmpll_d5",
			"clk_top_mmpll_d4",
			"clk_top_univpll_d6",
			"clk_top_univpll_d5",
			"clk_top_univpll_d4",
			"clk_top_univpll_d3",
			"clk_top_mainpll_d6",
			"clk_top_mainpll_d4",
			"clk_top_mainpll_d3",
			"clk_top_tvdpll_ck",
			"clk_top_tvdpll_mainpll_d2_ck",
			"clk_top_apupll_ck",
			"clk_apmixed_apupll_rate",
			"mtcmos_scp_sys_vpu";
	};

	edma0: edma0@19027000 {
		compatible = "mtk,edma-sub";
		reg = <0x0 0x19027000 0x0 0x1000>;
		interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>;
	};

	edma1: edma1@19028000 {
		compatible = "mtk,edma-sub";
		reg = <0x0 0x19028000 0x0 0x1000>;
		interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>;
	};

	edma: edma {
		compatible = "mtk,edma";
		sub_nr = <2>;
		mediatek,edma-sub = <&edma0>, <&edma1>;
	};

	vpu_core0: vpu_core0@19030000 {
		compatible = "mediatek,vpu_core0";
		reg = <0 0x19030000 0 0x1000>,
			<0 0x1d100000 0 0x40000>,
			<0 0x1d140000 0 0x30000>,
			<0 0x0d190000 0 0x4000>;
		interrupts = <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>;
		id = <0>;
		reset-vector = <0x7da00000 0x00100000 0x0>;
		main-prog = <0x7db00000 0x00300000 0x100000>;
		kernel-lib = <0x7de00000 0x00500000 0xffffffff>;
		work-buf = <0x0 0x12000 0xffffffff>;
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu2 M4U_PORT_L21_APU_FAKE_CODE>;
#endif
	};

	vpu_core1: vpu_core1@19031000 {
		compatible = "mediatek,vpu_core1";
		reg = <0 0x19031000 0 0x1000>,
			<0 0x1d200000 0 0x40000>,
			<0 0x1d240000 0 0x30000>,
			<0 0x0d194000 0 0x4000>;
		interrupts = <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
		id = <1>;
		reset-vector = <0x7e300000 0x00100000 0x400000>;
		main-prog = <0x7e400000 0x00300000 0x500000>;
		kernel-lib = <0x7e700000 0x00500000 0xffffffff>;
		work-buf = <0x0 0x12000 0xffffffff>;
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu2 M4U_PORT_L21_APU_FAKE_CODE>;
#endif
	};

	vpu_core2: vpu_core2@19032000 {
		compatible = "mediatek,vpu_core2";
		reg = <0 0x19032000 0 0x1000>,
			<0 0x1d300000 0 0x40000>,
			<0 0x1d340000 0 0x30000>,
			<0 0x0d198000 0 0x4000>;
		interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
		id = <2>;
		reset-vector = <0x7ec00000 0x00100000 0x800000>;
		main-prog = <0x7ed00000 0x00300000 0x900000>;
		kernel-lib = <0x7f000000 0x00500000 0xffffffff>;
		work-buf = <0x0 0x12000 0xffffffff>;
#ifdef CONFIG_MTK_IOMMU_V2
		iommus = <&iommu2 M4U_PORT_L21_APU_FAKE_CODE>;
#endif
	};

#ifdef CONFIG_MTK_IOMMU_V2
	ion: iommu {
		compatible = "mediatek,ion";
		iommus = <&iommu0 M4U_PORT_L0_DISP_FAKE0>;
	};

	pseudo_m4u {
		compatible = "mediatek,mt-pseudo_m4u";
		iommus = <&iommu0 M4U_PORT_L0_DISP_FAKE0>;
	};

	pseudo_m4u-larb0 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <0>;
		iommus = <&iommu0 M4U_PORT_L0_DISP_POSTMASK0>,
			 <&iommu0 M4U_PORT_L0_MDP_RDMA4>,
			 <&iommu0 M4U_PORT_L0_OVL_RDMA0_HDR>,
			 <&iommu0 M4U_PORT_L0_OVL_2L_RDMA1_HDR>,
			 <&iommu0 M4U_PORT_L0_OVL_2L_RDMA3_HDR>,
			 <&iommu0 M4U_PORT_L0_OVL_RDMA0>,
			 <&iommu0 M4U_PORT_L0_OVL_2L_RDMA1>,
			 <&iommu0 M4U_PORT_L0_OVL_2L_RDMA3>,
			 <&iommu0 M4U_PORT_L0_OVL_RDMA1_SYSRAM>,
			 <&iommu0 M4U_PORT_L0_OVL_2L_RDMA0_SYSRAM>,
			 <&iommu0 M4U_PORT_L0_OVL_2L_RDMA2_SYSRAM>,
			 <&iommu0 M4U_PORT_L0_DISP_WDMA0>,
			 <&iommu0 M4U_PORT_L0_DISP_RDMA0>,
			 <&iommu0 M4U_PORT_L0_DISP_UFBC_WDMA0>,
			 <&iommu0 M4U_PORT_L0_DISP_FAKE0>;
	};

	pseudo_m4u-larb1 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <1>;
		iommus = <&iommu0 M4U_PORT_L1_DISP_POSTMASK1>,
			 <&iommu0 M4U_PORT_L1_MDP_RDMA5>,
			 <&iommu0 M4U_PORT_L1_OVL_RDMA1_HDR>,
			 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0_HDR>,
			 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2_HDR>,
			 <&iommu0 M4U_PORT_L1_OVL_RDMA1>,
			 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA0>,
			 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA2>,
			 <&iommu0 M4U_PORT_L1_OVL_RDMA0_SYSRAM>,
			 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA1_SYSRAM>,
			 <&iommu0 M4U_PORT_L1_OVL_2L_RDMA3_SYSRAM>,
			 <&iommu0 M4U_PORT_L1_DISP_WDMA1>,
			 <&iommu0 M4U_PORT_L1_DISP_RDMA1>,
			 <&iommu0 M4U_PORT_L1_DISP_UFBC_WDMA1>,
			 <&iommu0 M4U_PORT_L1_DISP_FAKE1>;
	};

	pseudo_m4u-larb2 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <2>;
		iommus = <&iommu1 M4U_PORT_L2_MDP_RDMA0>,
			 <&iommu1 M4U_PORT_L2_MDP_RDMA2>,
			 <&iommu1 M4U_PORT_L2_MDP_WROT0>,
			 <&iommu1 M4U_PORT_L2_MDP_WROT2>,
			 <&iommu1 M4U_PORT_L2_MDP_FILMGRAIN0>,
			 <&iommu1 M4U_PORT_L2_MDP_FAKE0>;
	};

	pseudo_m4u-larb3 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <3>;
		iommus = <&iommu1 M4U_PORT_L3_MDP_RDMA1>,
			<&iommu1 M4U_PORT_L3_MDP_RDMA3>,
			<&iommu1 M4U_PORT_L3_MDP_WROT1>,
			<&iommu1 M4U_PORT_L3_MDP_WROT3>,
			<&iommu1 M4U_PORT_L3_MDP_FILMGRAIN1>,
			<&iommu1 M4U_PORT_L3_MDP_FAKE1>;
	};

	pseudo_m4u-larb4 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <4>;
		iommus = <&iommu1 M4U_PORT_L4_VDEC_MC_EXT_MDP>,
			<&iommu1 M4U_PORT_L4_VDEC_UFO_EXT_MDP>,
			<&iommu1 M4U_PORT_L4_VDEC_PP_EXT_MDP>,
			<&iommu1 M4U_PORT_L4_VDEC_PRED_RD_EXT_MDP>,
			<&iommu1 M4U_PORT_L4_VDEC_PRED_WR_EXT_MDP>,
			<&iommu1 M4U_PORT_L4_VDEC_PPWRAP_EXT_MDP>,
			<&iommu1 M4U_PORT_L4_VDEC_TILE_EXT_MDP>,
			<&iommu1 M4U_PORT_L4_VDEC_VLD_EXT_MDP>,
			<&iommu1 M4U_PORT_L4_VDEC_VLD2_EXT_MDP>,
			<&iommu1 M4U_PORT_L4_VDEC_AVC_MV_EXT_MDP>,
			<&iommu1 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT_MDP>;
	};

	pseudo_m4u-larb5 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <5>;
		iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT_DISP>,
			<&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT_DISP>,
			<&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT_DISP>,
			<&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT_DISP>,
			<&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT_DISP>,
			<&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT_DISP>,
			<&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT_DISP>,
			<&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT_DISP>;
	};

	pseudo_m4u-larb7 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <7>;
		iommus = <&iommu0 M4U_PORT_L7_VENC_RCPU_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_REC_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_BSDMA_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_SV_COMV_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_RD_COMV_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_NBM_RDMA_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_NBM_RDMA_LITE_DISP>,
			<&iommu0 M4U_PORT_L7_JPGENC_Y_RDMA_DISP>,
			<&iommu0 M4U_PORT_L7_JPGENC_C_RDMA_DISP>,
			<&iommu0 M4U_PORT_L7_JPGENC_Q_TABLE_DISP>,
			<&iommu0 M4U_PORT_L7_JPGENC_BSDMA_DISP>,
			<&iommu0 M4U_PORT_L7_JPGENC_WDMA0_DISP>,
			<&iommu0 M4U_PORT_L7_JPGENC_BSDMA0_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_NBM_WDMA_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_NBM_WDMA_LITE_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_CUR_LUMA_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_CUR_CHROMA_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_REF_LUMA_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_REF_CHROMA_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_SUB_R_LUMA_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_SUB_W_LUMA_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_FCS_NBM_RDMA_DISP>,
			<&iommu0 M4U_PORT_L7_VENC_FCS_NBM_WDMA_DISP>,
			<&iommu0 M4U_PORT_L7_JPGENC_WDMA1_DISP>,
			<&iommu0 M4U_PORT_L7_JPGENC_BSDMA1_DISP>,
			<&iommu0 M4U_PORT_L7_JPGENC_HUFF_OFFSET1_DISP>,
			<&iommu0 M4U_PORT_L7_JPGENC_HUFF_OFFSET0_DISP>;
	};

	pseudo_m4u-larb8 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <8>;
		iommus = <&iommu1 M4U_PORT_L8_VENC_RCPU_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_REC_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_BSDMA_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_SV_COMV_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_RD_COMV_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_NBM_RDMA_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_NBM_RDMA_LITE_MDP>,
			<&iommu1 M4U_PORT_L8_JPGENC_Y_RDMA_MDP>,
			<&iommu1 M4U_PORT_L8_JPGENC_C_RDMA_MDP>,
			<&iommu1 M4U_PORT_L8_JPGENC_Q_TABLE_MDP>,
			<&iommu1 M4U_PORT_L8_JPGENC_BSDMA_MDP>,
			<&iommu1 M4U_PORT_L8_JPGENC_WDMA0_MDP>,
			<&iommu1 M4U_PORT_L8_JPGENC_BSDMA0_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_NBM_WDMA_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_NBM_WDMA_LITE_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_CUR_LUMA_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_CUR_CHROMA_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_REF_LUMA_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_REF_CHROMA_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_SUB_R_LUMA_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_SUB_W_LUMA_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_FCS_NBM_RDMA_MDP>,
			<&iommu1 M4U_PORT_L8_VENC_FCS_NBM_WDMA_MDP>,
			<&iommu1 M4U_PORT_L8_JPGENC_WDMA1_MDP>,
			<&iommu1 M4U_PORT_L8_JPGENC_BSDMA1_MDP>,
			<&iommu1 M4U_PORT_L8_JPGENC_HUFF_OFFSET1_MDP>,
			<&iommu1 M4U_PORT_L8_JPGENC_HUFF_OFFSET0_MDP>;
	};

	pseudo_m4u-larb9 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <9>;
		iommus = <&iommu1 M4U_PORT_L9_IMG_IMGI_D1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_IMGBI_D1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_DMGI_D1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_DEPI_D1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_ICE_D1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_SMTI_D1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_SMTO_D2_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_SMTO_D1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_CRZO_D1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_IMG3O_D1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_VIPI_D1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_SMTI_D5_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_TIMGO_D1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_UFBC_W0_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_UFBC_R0_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_WPE_RDMA1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_WPE_RDMA0_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_WPE_WDMA_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_MFB_RDMA0_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_MFB_RDMA1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_MFB_RDMA2_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_MFB_RDMA3_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_MFB_RDMA4_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_MFB_RDMA5_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_MFB_WDMA0_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_MFB_WDMA1_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_RESERVE6_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_RESERVE7_MDP>,
			<&iommu1 M4U_PORT_L9_IMG_RESERVE8_MDP>;
	};

	pseudo_m4u-larb11 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <11>;
		iommus = <&iommu0 M4U_PORT_L11_IMG_IMGI_D1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_IMGBI_D1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_DMGI_D1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_DEPI_D1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_ICE_D1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_SMTI_D1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_SMTO_D2_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_SMTO_D1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_CRZO_D1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_IMG3O_D1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_VIPI_D1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_SMTI_D5_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_TIMGO_D1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_UFBC_W0_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_UFBC_R0_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_WPE_RDMA1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_WPE_RDMA0_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_WPE_WDMA_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA0_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA2_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA3_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA4_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_MFB_RDMA5_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_MFB_WDMA0_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_MFB_WDMA1_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_RESERVE6_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_RESERVE7_DISP>,
			<&iommu0 M4U_PORT_L11_IMG_RESERVE8_DISP>;
	};

	pseudo_m4u-larb13 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <13>;
		iommus = <&iommu1 M4U_PORT_L13_CAM_MRAWI_MDP>,
			<&iommu1 M4U_PORT_L13_CAM_MRAWO0_MDP>,
			<&iommu1 M4U_PORT_L13_CAM_MRAWO1_MDP>,
			<&iommu1 M4U_PORT_L13_CAM_CAMSV1_MDP>,
			<&iommu1 M4U_PORT_L13_CAM_CAMSV2_MDP>,
			<&iommu1 M4U_PORT_L13_CAM_CAMSV3_MDP>,
			<&iommu1 M4U_PORT_L13_CAM_CAMSV4_MDP>,
			<&iommu1 M4U_PORT_L13_CAM_CAMSV5_MDP>,
			<&iommu1 M4U_PORT_L13_CAM_CAMSV6_MDP>,
			<&iommu1 M4U_PORT_L13_CAM_CCUI_MDP>,
			<&iommu1 M4U_PORT_L13_CAM_CCUO_MDP>,
			<&iommu1 M4U_PORT_L13_CAM_FAKE_MDP>;
	};

	pseudo_m4u-larb14 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <14>;
		iommus = <&iommu0 M4U_PORT_L14_CAM_MRAWI_DISP>,
			<&iommu0 M4U_PORT_L14_CAM_MRAWO0_DISP>,
			<&iommu0 M4U_PORT_L14_CAM_MRAWO1_DISP>,
			<&iommu0 M4U_PORT_L14_CAM_CAMSV0_DISP>,
			<&iommu0 M4U_PORT_L14_CAM_CCUI_DISP>,
			<&iommu0 M4U_PORT_L14_CAM_CCUO_DISP>;
	};

	pseudo_m4u-larb16 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <16>;
		iommus = <&iommu1 M4U_PORT_L16_CAM_IMGO_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_RRZO_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_CQI_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_BPCI_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_YUVO_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_UFDI_R2_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_RAWI_R2_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_RAWI_R3_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_AAO_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_AFO_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_FLKO_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_LCESO_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_CRZO_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_LTMSO_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_RSSO_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_AAHO_R1_A_MDP>,
			<&iommu1 M4U_PORT_L16_CAM_LSCI_R1_A_MDP>;
	};

	pseudo_m4u-larb17 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <17>;
		iommus = <&iommu0 M4U_PORT_L17_CAM_IMGO_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_RRZO_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_CQI_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_BPCI_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_YUVO_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_UFDI_R2_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_RAWI_R2_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_RAWI_R3_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_AAO_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_AFO_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_FLKO_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_LCESO_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_CRZO_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_LTMSO_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_RSSO_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_AAHO_R1_B_DISP>,
			<&iommu0 M4U_PORT_L17_CAM_LSCI_R1_B_DISP>;
	};

	pseudo_m4u-larb18 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <18>;
		iommus = <&iommu1 M4U_PORT_L18_CAM_IMGO_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_RRZO_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_CQI_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_BPCI_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_YUVO_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_UFDI_R2_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_RAWI_R2_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_RAWI_R3_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_AAO_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_AFO_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_FLKO_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_LCESO_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_CRZO_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_LTMSO_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_RSSO_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_AAHO_R1_C_MDP>,
			<&iommu1 M4U_PORT_L18_CAM_LSCI_R1_C_MDP>;
	};

	pseudo_m4u-larb19 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <19>;
		iommus = <&iommu0 M4U_PORT_L19_IPE_DVS_RDMA_DISP>,
			<&iommu0 M4U_PORT_L19_IPE_DVS_WDMA_DISP>,
			<&iommu0 M4U_PORT_L19_IPE_DVP_RDMA_DISP>,
			<&iommu0 M4U_PORT_L19_IPE_DVP_WDMA_DISP>;
	};

	pseudo_m4u-larb20 {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <20>;
		iommus = <&iommu0 M4U_PORT_L20_IPE_FDVT_RDA_DISP>,
			<&iommu0 M4U_PORT_L20_IPE_FDVT_RDB_DISP>,
			<&iommu0 M4U_PORT_L20_IPE_FDVT_WRA_DISP>,
			<&iommu0 M4U_PORT_L20_IPE_FDVT_WRB_DISP>,
			<&iommu0 M4U_PORT_L20_IPE_RSC_RDMA0_DISP>,
			<&iommu0 M4U_PORT_L20_IPE_RSC_WDMA_DISP>;
	};

	pseudo_m4u-ccu-node {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <CCU_PSEUDO_LARBID_NODE>;
		iommus = <&iommu1 M4U_PORT_L23_CCU_MDP>;
	};

	pseudo_m4u-ccu-larb {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <CCU_PSEUDO_LARBID_LARB>;
		iommus = <&iommu1 M4U_PORT_L22_CCU_DISP>;
	};

	pseudo_m4u-vpu-code {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <APU_PSEUDO_LARBID_CODE>;
		iommus = <&iommu2 M4U_PORT_L21_APU_FAKE_CODE>;
	};

	pseudo_m4u-vpu-data {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <APU_PSEUDO_LARBID_DATA>;
		iommus = <&iommu3 M4U_PORT_L21_APU_FAKE_DATA>;
	};

	pseudo_m4u-vpu-vlm {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <APU_PSEUDO_LARBID_VLM>;
		iommus = <&iommu2 M4U_PORT_L21_APU_FAKE_VLM>;
	};

	pseudo_m4u-misc-disp {
		compatible = "mediatek,mt-pseudo_m4u-port";
		mediatek,larbid = <MISC_PSEUDO_LARBID_DISP>;
		iommus = <&iommu0 M4U_PORT_L0_DISP_FAKE0>;
	};

#endif

	audio: audio@11210000 {
		compatible = "mediatek,audio", "syscon";
		reg = <0 0x11210000 0 0x2000>;
		#clock-cells = <1>;
		mediatek,btcvsd_snd = <&btcvsd_snd>;
	};

	afe: mt6885-afe-pcm@11210000 {
		compatible = "mediatek,mt6885-sound";
		reg = <0 0x11210000 0 0x2000>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
		topckgen = <&topckgen>;
		apmixed = <&apmixed>;
		infracfg_ao = <&infracfg_ao>;
		clocks = <&audio AUDIO_PDN_AFE>,
			<&audio AUDIO_PDN_DAC>,
			<&audio AUDIO_PDN_DAC_PREDIS>,
			<&audio AUDIO_PDN_ADC>,
			<&audio AUDIO_PDN_ADDA6_ADC>,
			<&audio AUDIO_PDN_22M>,
			<&audio AUDIO_PDN_24M>,
			<&audio AUDIO_PDN_APLL_TUNER>,
			<&audio AUDIO_PDN_APLL2_TUNER>,
			<&audio AUDIO_PDN_TDM_CK>,
			<&audio AUDIO_PDN_TML>,
			<&audio AUDIO_PDN_NLE>,
			<&audio AUDIO_PDN_DAC_HIRES>,
			<&audio AUDIO_PDN_ADC_HIRES>,
			<&audio AUDIO_PDN_ADC_HIRES_TML>,
			<&audio AUDIO_PDN_ADDA6_ADC_HIRES>,
			<&audio AUDIO_PDN_3RD_DAC>,
			<&audio AUDIO_PDN_3RD_DAC_PREDIS>,
			<&audio AUDIO_PDN_3RD_DAC_TML>,
			<&audio AUDIO_PDN_3RD_DAC_HIRES>,
			<&scpsys SCP_SYS_AUDIO>,
			<&infracfg_ao INFRACFG_AO_AUDIO_CG>,
			<&infracfg_ao INFRACFG_AO_AUDIO_26M_BCLK_CK>,
			<&topckgen TOP_MUX_AUDIO>,
			<&topckgen TOP_MUX_AUD_INTBUS>,
			<&topckgen TOP_MAINPLL_D4_D4>,
			<&topckgen TOP_MUX_AUD_1>,
			<&topckgen TOP_APLL1_CK>,
			<&topckgen TOP_MUX_AUD_2>,
			<&topckgen TOP_APLL2_CK>,
			<&topckgen TOP_MUX_AUD_ENGEN1>,
			<&topckgen TOP_APLL1_D4>,
			<&topckgen TOP_MUX_AUD_ENGEN2>,
			<&topckgen TOP_APLL2_D4>,
			<&topckgen TOP_I2S0_M_SEL>,
			<&topckgen TOP_I2S1_M_SEL>,
			<&topckgen TOP_I2S2_M_SEL>,
			<&topckgen TOP_I2S3_M_SEL>,
			<&topckgen TOP_I2S4_M_SEL>,
			<&topckgen TOP_I2S5_M_SEL>,
			<&topckgen TOP_I2S6_M_SEL>,
			<&topckgen TOP_I2S7_M_SEL>,
			<&topckgen TOP_I2S8_M_SEL>,
			<&topckgen TOP_I2S9_M_SEL>,
			<&topckgen TOP_APLL12_DIV0>,
			<&topckgen TOP_APLL12_DIV1>,
			<&topckgen TOP_APLL12_DIV2>,
			<&topckgen TOP_APLL12_DIV3>,
			<&topckgen TOP_APLL12_DIV4>,
			<&topckgen TOP_APLL12_DIVB>,
			<&topckgen TOP_APLL12_DIV5>,
			<&topckgen TOP_APLL12_DIV6>,
			<&topckgen TOP_APLL12_DIV7>,
			<&topckgen TOP_APLL12_DIV8>,
			<&topckgen TOP_APLL12_DIV9>,
			<&topckgen TOP_MUX_AUDIO_H>,
			<&clk26m>;

		clock-names = "aud_afe_clk",
			"aud_dac_clk",
			"aud_dac_predis_clk",
			"aud_adc_clk",
			"aud_adda6_adc_clk",
			"aud_apll22m_clk",
			"aud_apll24m_clk",
			"aud_apll1_tuner_clk",
			"aud_apll2_tuner_clk",
			"aud_tdm_clk",
			"aud_tml_clk",
			"aud_nle",
			"aud_dac_hires_clk",
			"aud_adc_hires_clk",
			"aud_adc_hires_tml",
			"aud_adda6_adc_hires_clk",
			"aud_3rd_dac_clk",
			"aud_3rd_dac_predis_clk",
			"aud_3rd_dac_tml",
			"aud_3rd_dac_hires_clk",
			"scp_sys_audio",
			"aud_infra_clk",
			"aud_infra_26m_clk",
			"top_mux_audio",
			"top_mux_audio_int",
			"top_mainpll_d4_d4",
			"top_mux_aud_1",
			"top_apll1_ck",
			"top_mux_aud_2",
			"top_apll2_ck",
			"top_mux_aud_eng1",
			"top_apll1_d4",
			"top_mux_aud_eng2",
			"top_apll2_d4",
			"top_i2s0_m_sel",
			"top_i2s1_m_sel",
			"top_i2s2_m_sel",
			"top_i2s3_m_sel",
			"top_i2s4_m_sel",
			"top_i2s5_m_sel",
			"top_i2s6_m_sel",
			"top_i2s7_m_sel",
			"top_i2s8_m_sel",
			"top_i2s9_m_sel",
			"top_apll12_div0",
			"top_apll12_div1",
			"top_apll12_div2",
			"top_apll12_div3",
			"top_apll12_div4",
			"top_apll12_divb",
			"top_apll12_div5",
			"top_apll12_div6",
			"top_apll12_div7",
			"top_apll12_div8",
			"top_apll12_div9",
			"top_mux_audio_h",
			"top_clk26m_clk";

		pinctrl-names = "aud_clk_mosi_off",
				"aud_clk_mosi_on",
				"aud_dat_mosi_off",
				"aud_dat_mosi_on",
				"aud_dat_miso_off",
				"aud_dat_miso_on",
				"vow_dat_miso_off",
				"vow_dat_miso_on",
				"vow_clk_miso_off",
				"vow_clk_miso_on",
				"aud_nle_mosi_off",
				"aud_nle_mosi_on",
				"aud_dat_miso2_off",
				"aud_dat_miso2_on",
				"aud_gpio_i2s0_off",
				"aud_gpio_i2s0_on",
				"aud_gpio_i2s1_off",
				"aud_gpio_i2s1_on",
				"aud_gpio_i2s2_off",
				"aud_gpio_i2s2_on",
				"aud_gpio_i2s3_off",
				"aud_gpio_i2s3_on",
				"aud_gpio_i2s5_off",
				"aud_gpio_i2s5_on",
				"aud_gpio_i2s6_off",
				"aud_gpio_i2s6_on",
				"aud_gpio_i2s7_off",
				"aud_gpio_i2s7_on",
				"aud_gpio_i2s8_off",
				"aud_gpio_i2s8_on",
				"aud_gpio_i2s9_off",
				"aud_gpio_i2s9_on",
				"aud_dat_mosi_ch34_off",
				"aud_dat_mosi_ch34_on",
				"aud_dat_miso_ch34_off",
				"aud_dat_miso_ch34_on";
		pinctrl-0 = <&aud_clk_mosi_off>;
		pinctrl-1 = <&aud_clk_mosi_on>;
		pinctrl-2 = <&aud_dat_mosi_off>;
		pinctrl-3 = <&aud_dat_mosi_on>;
		pinctrl-4 = <&aud_dat_miso_off>;
		pinctrl-5 = <&aud_dat_miso_on>;
		pinctrl-6 = <&vow_dat_miso_off>;
		pinctrl-7 = <&vow_dat_miso_on>;
		pinctrl-8 = <&vow_clk_miso_off>;
		pinctrl-9 = <&vow_clk_miso_on>;
		pinctrl-10 = <&aud_nle_mosi_off>;
		pinctrl-11 = <&aud_nle_mosi_on>;
		pinctrl-12 = <&aud_dat_miso2_off>;
		pinctrl-13 = <&aud_dat_miso2_on>;
		pinctrl-14 = <&aud_gpio_i2s0_off>;
		pinctrl-15 = <&aud_gpio_i2s0_on>;
		pinctrl-16 = <&aud_gpio_i2s1_off>;
		pinctrl-17 = <&aud_gpio_i2s1_on>;
		pinctrl-18 = <&aud_gpio_i2s2_off>;
		pinctrl-19 = <&aud_gpio_i2s2_on>;
		pinctrl-20 = <&aud_gpio_i2s3_off>;
		pinctrl-21 = <&aud_gpio_i2s3_on>;
		pinctrl-22 = <&aud_gpio_i2s5_off>;
		pinctrl-23 = <&aud_gpio_i2s5_on>;
		pinctrl-24 = <&aud_gpio_i2s6_off>;
		pinctrl-25 = <&aud_gpio_i2s6_on>;
		pinctrl-26 = <&aud_gpio_i2s7_off>;
		pinctrl-27 = <&aud_gpio_i2s7_on>;
		pinctrl-28 = <&aud_gpio_i2s8_off>;
		pinctrl-29 = <&aud_gpio_i2s8_on>;
		pinctrl-30 = <&aud_gpio_i2s9_off>;
		pinctrl-31 = <&aud_gpio_i2s9_on>;
		pinctrl-32 = <&aud_dat_mosi_ch34_off>;
		pinctrl-33 = <&aud_dat_mosi_ch34_on>;
		pinctrl-34 = <&aud_dat_miso_ch34_off>;
		pinctrl-35 = <&aud_dat_miso_ch34_on>;
	};

	mt6359_snd: mt6359_snd {
		compatible = "mediatek,mt6359-sound";
		mediatek,pwrap-regmap = <&pwrap>;
	};

	sound: sound {
		compatible = "mediatek,mt6885-mt6359-sound";
		mediatek,audio-codec = <&mt6359_snd>;
		mediatek,platform = <&afe>;
		mediatek,snd_audio_dsp = <&snd_audio_dsp>;
		mtk_spk_i2s_out = <3>;
		mtk_spk_i2s_in = <0>;
		/* mtk_spk_i2s_mck = <3>; */
		mediatek,speaker-codec {
			sound-dai = <&speaker_amp>;
		};
	};

	/* feature : $enable $dl_mem $ul_mem $ref_mem $size */
	snd_audio_dsp: snd_audio_dsp {
		compatible = "mediatek,snd_audio_dsp";
		mtk_dsp_voip = <0x1f 0xffffffff 0xffffffff 0xffffffff 0x30000>;
		mtk_dsp_primary = <0x5 0xffffffff 0xffffffff \
				   0xffffffff 0x30000>;
		mtk_dsp_offload = <0x1d 0xffffffff 0xffffffff \
				   0xffffffff 0x400000>;
		mtk_dsp_deep = <0x5 0xffffffff 0xffffffff 0xffffffff 0x30000>;
		mtk_dsp_playback = <0x1 0x4 0xffffffff 0x14 0x30000>;
		mtk_dsp_music = <0x1 0xffffffff 0xffffffff 0xffffffff 0x0>;
		mtk_dsp_capture1 = <0x1 0xffffffff 0xd 0x13 0x20000>;
		mtk_dsp_a2dp = <0x1 0xffffffff 0xffffffff 0xffffffff 0x40000>;
		mtk_dsp_dataprovider = <0x0 0xffffffff 0xf 0xffffffff 0x30000>;
		mtk_dsp_call_final = <0x5 0x4 0x10 0x14 0x18000>;
		mtk_dsp_fast = <0x5 0xffffffff 0xffffffff 0xffffffff 0x5000>;
		mtk_dsp_ktv = <0x1 0x8 0x12 0xffffffff 0x10000>;
		mtk_dsp_ver = <0x1>;
		swdsp_smartpa_process_enable = <0x5>;
		mtk_dsp_mem_afe = <0x1 0x40000>; /* always enable */
	};

	audio_sram@11212000 {
		compatible = "mediatek,audio_sram";
		reg = <0 0x11212000 0 0x18000>;
		prefer_mode = <0>;
		mode_size = <0x12000 0x18000>;
		block_size = <0x1000>;
	};

	btcvsd_snd: mtk-btcvsd-snd@18830000 {
		compatible = "mediatek,mtk-btcvsd-snd";
		reg=<0 0x18830000 0 0x2000>, /*PKV_PHYSICAL_BASE*/
		    <0 0x18840000 0 0x20000>; /*SRAM_BANK2*/
		interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
		mediatek,infracfg = <&infracfg_ao>;
		/*INFRA MISC, conn_bt_cvsd_mask*/
		/*cvsd_mcu_read, write, packet_indicator*/
		mediatek,offset =<0xf00 0x800 0x140 0x144 0x148>;
		disable_write_silence = <1>;
	};

	mt_soc_playback_offload {
		compatible = "mediatek,mt_soc_offload_common";
	};

	slbc: slbc {
		compatible = "mediatek,slbc";
		status = "enable";
	};

	mmsram@1f005000 {
		compatible = "mediatek,mmsram";
		reg = <0 0x1f005000 0 0x1000>,
			<0 0x1e000000 0 0x160000>;
		interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>;
#ifndef CONFIG_FPGA_EARLY_PORTING
		clocks = <&scpsys SCP_SYS_MDP>,
			<&mdpsys_config MDP_APMCU_GALS>,
			<&mdpsys_config MDP_SMI0>, <&mdpsys_config MDP_SMI1>,
			<&mdpsys_config MDP_SMI2>,
			<&mdpsys_config MDP_MMSYSRAM>;
		clock-names = "scp_mdp", "mdp_apmcu_gals",
				"mdp_smi0", "mdp_smi1",
				"mdp_smi2", "mdp_mmsysram";
#endif
	};

	irtx_pwm:irtx_pwm {
		compatible = "mediatek,irtx-pwm";
		pwm_ch = <3>;
		pwm_data_invert = <0>;
	};

	mt_charger: mt_charger {
		compatible = "mediatek,mt-charger";
	};

	lk_charger: lk_charger {
		compatible = "mediatek,lk_charger";
		enable_anime;
		/* enable_pe_plus; */
		enable_pd20_reset;
		power_path_support;
		max_charger_voltage = <6500000>;
		fast_charge_voltage = <3000000>;

		/* charging current */
		usb_charger_current = <500000>;
		ac_charger_current = <2050000>;
		ac_charger_input_current = <3200000>;
		non_std_ac_charger_current = <500000>;
		charging_host_charger_current = <1500000>;
		ta_ac_charger_current = <3000000>;
		pd_charger_current = <500000>;

		/* battery temperature protection */
		temp_t4_threshold = <50>;
		temp_t3_threshold = <45>;
		temp_t1_threshold = <0>;
	};

	charger: charger {
		compatible = "mediatek,charger";
		algorithm_name = "SwitchCharging2";
		/* enable_sw_jeita; */
		/* enable_pe_plus; */
		/* enable_pe_2; */
		/* enable_pe_3; */
		/* enable_pe_4; */
		enable_type_c;
		power_path_support;
		enable_dynamic_mivr;

		/* common */
		battery_cv = <4350000>;
		max_charger_voltage = <6500000>;
		min_charger_voltage = <4600000>;

		/* dynamic mivr */
		min_charger_voltage_1 = <4400000>;
		min_charger_voltage_2 = <4200000>;
		max_dmivr_charger_current = <1400000>;

		/* charging current */
		usb_charger_current_suspend = <0>;
		usb_charger_current_unconfigured = <70000>;
		usb_charger_current_configured = <500000>;
		usb_charger_current = <500000>;
		ac_charger_current = <2050000>;
		ac_charger_input_current = <3200000>;
		non_std_ac_charger_current = <500000>;
		charging_host_charger_current = <1500000>;
		apple_1_0a_charger_current = <650000>;
		apple_2_1a_charger_current = <800000>;
		ta_ac_charger_current = <3000000>;

		/* sw jeita */
		jeita_temp_above_t4_cv = <4240000>;
		jeita_temp_t3_to_t4_cv = <4240000>;
		jeita_temp_t2_to_t3_cv = <4340000>;
		jeita_temp_t1_to_t2_cv = <4240000>;
		jeita_temp_t0_to_t1_cv = <4040000>;
		jeita_temp_below_t0_cv = <4040000>;
		temp_t4_thres = <50>;
		temp_t4_thres_minus_x_degree = <47>;
		temp_t3_thres = <45>;
		temp_t3_thres_minus_x_degree = <39>;
		temp_t2_thres = <10>;
		temp_t2_thres_plus_x_degree = <16>;
		temp_t1_thres = <0>;
		temp_t1_thres_plus_x_degree = <6>;
		temp_t0_thres = <0>;
		temp_t0_thres_plus_x_degree = <0>;
		temp_neg_10_thres = <0>;

		/* battery temperature protection */
		enable_min_charge_temp;
		min_charge_temp = <0>;
		min_charge_temp_plus_x_degree = <6>;
		max_charge_temp = <50>;
		max_charge_temp_minus_x_degree = <47>;

		/* PE */
		ta_12v_support;
		ta_9v_support;
		pe_ichg_level_threshold = <1000000>; /* uA */
		ta_ac_12v_input_current = <3200000>;
		ta_ac_9v_input_current = <3200000>;
		ta_ac_7v_input_current = <3200000>;

		/* PE 2.0 */
		pe20_ichg_level_threshold = <1000000>; /* uA */
		ta_start_battery_soc = <0>;
		ta_stop_battery_soc = <85>;

		/* PE 4.0 */
		high_temp_to_leave_pe40 = <46>;
		high_temp_to_enter_pe40 = <39>;
		low_temp_to_leave_pe40 = <10>;
		low_temp_to_enter_pe40 = <16>;

		/* PE 4.0 single charger*/
		pe40_single_charger_input_current = <3000000>;
		pe40_single_charger_current = <3000000>;

		/* PE 4.0 dual charger*/
		pe40_dual_charger_input_current = <3000000>;
		pe40_dual_charger_chg1_current = <2000000>;
		pe40_dual_charger_chg2_current = <2000000>;
		pe40_stop_battery_soc = <80>;

		/* PE 4.0 cable impedance (mohm) */
		pe40_r_cable_1a_lower = <576>;
		pe40_r_cable_2a_lower = <435>;
		pe40_r_cable_3a_lower = <293>;

		/* dual charger */
		chg1_ta_ac_charger_current = <1500000>;
		chg2_ta_ac_charger_current = <1500000>;
		slave_mivr_diff = <100000>;
		dual_polling_ieoc = <750000>;

		/* cable measurement impedance */
		cable_imp_threshold = <699>;
		vbat_cable_imp_threshold = <3900000>; /* uV */

		/* bif */
		bif_threshold1 = <4250000>;
		bif_threshold2 = <4300000>;
		bif_cv_under_threshold2 = <4450000>;

		/* PD */
		pd_vbus_low_bound = <5000000>;
		pd_vbus_upper_bound = <5000000>;
		pd_ichg_level_threshold = <1000000>; /* uA */
		pd_stop_battery_soc = <80>;

		ibus_err = <14>;
		vsys_watt = <5000000>;
	};

	pd_adapter: pd_adapter {
		compatible = "mediatek,pd_adapter";
		adapter_name = "pd_adapter";
	};

	rt-pd-manager {
		compatible = "mediatek,rt-pd-manager";
	};

	subpmic_pmu_eint: mt6360_pmu_eint {
	};

	pmic_clock_buffer_ctrl: pmic_clock_buffer_ctrl {
		compatible = "mediatek,pmic_clock_buffer";
		mediatek,clkbuf-quantity = <7>;
		mediatek,clkbuf-config = <2 1 1 2 0 0 1>;
		mediatek,clkbuf-output-impedance = <6 6 4 6 0 0 4>;
		mediatek,clkbuf-controls-for-desense = <0 4 0 4 0 0 0>;
	};

	mrdump_ext_rst: mrdump_ext_rst {
		compatible = "mediatek, mrdump_ext_rst-eint";
		mode = "IRQ";
		status = "okay";
	};

	touch: touch {
		compatible = "mediatek,touch";
	};

	tcpc_pd: tcpc_pd {
	};

	smart_pa: smart_pa {
	};

	md1_sim1_hot_plug_eint: md1_sim1_hot_plug_eint {
	};

	md1_sim2_hot_plug_eint: md1_sim2_hot_plug_eint {
	};

	drcc: drcc {
		compatible = "mediatek,drcc";
		state = <0>;
		drcc0_Vref = <255>;
		drcc1_Vref = <255>;
		drcc2_Vref = <255>;
		drcc3_Vref = <255>;
		drcc4_Vref = <255>;
		drcc5_Vref = <255>;
		drcc6_Vref = <255>;
		drcc7_Vref = <255>;
		drcc0_Hwgatepct = <255>;
		drcc1_Hwgatepct = <255>;
		drcc2_Hwgatepct = <255>;
		drcc3_Hwgatepct = <255>;
		drcc4_Hwgatepct = <255>;
		drcc5_Hwgatepct = <255>;
		drcc6_Hwgatepct = <255>;
		drcc7_Hwgatepct = <255>;
		drcc0_Code = <255>;
		drcc1_Code = <255>;
		drcc2_Code = <255>;
		drcc3_Code = <255>;
		drcc4_Code = <255>;
		drcc5_Code = <255>;
		drcc6_Code = <255>;
		drcc7_Code = <255>;
	};

#ifdef CONFIG_MTK_SCHED_MONITOR
	sched_mon: sched_mon {
		compatible = "mediatek,sched_mon";

		/* irq time tracer */
#ifdef CONFIG_MTK_ENG_BUILD
		irq_time_tracer = <1>;
		irq_time_th1_ms = <100>;
		irq_time_th2_ms = <500>;
		irq_time_aee_limit = <0>;
#else
		irq_time_tracer = <0>;
		irq_time_th1_ms = <5>;
		irq_time_th2_ms = <5>;
		irq_time_aee_limit = <0>;
#endif
		/* irq count tracer */
#ifdef CONFIG_MTK_IRQ_COUNT_TRACER
#ifdef CONFIG_MTK_ENG_BUILD
		irq_count_tracer = <1>;
		irq_period_th1_ns = <200000>;
		irq_period_th2_ns = <200000>;
		irq_count_aee_limit = <1>;
#else
		irq_count_tracer = <0>;
		irq_period_th1_ns = <200000>;
		irq_period_th2_ns = <200000>;
		irq_count_aee_limit = <0>;
#endif
#endif
		/* irq off tracer */
#ifdef CONFIG_MTK_IRQ_OFF_TRACER
#ifdef CONFIG_MTK_ENG_BUILD
		irq_off_tracer = <1>;
		irq_off_tracer_trace = <1>;
		irq_off_th1_ms = <50>;
		irq_off_th2_ms = <500>;
		irq_off_th3_ms = <500>;
		irq_off_aee_limit = <0>;
		irq_off_aee_debounce_ms = <60000>;
#else
		irq_off_tracer = <0>;
		irq_off_tracer_trace = <1>;
		irq_off_th1_ms = <5>;
		irq_off_th2_ms = <5>;
		irq_off_th3_ms = <5>;
		irq_off_aee_limit = <0>;
		irq_off_aee_debounce_ms = <30000>;
#endif
#endif
		/* preempt off tracer */
#ifdef CONFIG_MTK_PREEMPT_TRACER
#ifdef CONFIG_MTK_ENG_BUILD
		preempt_tracer = <0>;
		preempt_tracer_trace = <0>;
		preempt_th1_ms = <60000>;
		preempt_th2_ms = <180000>;
		preempt_th3_ms = <180000>;
		preempt_aee_limit = <0>;
#else
		preempt_tracer = <0>;
		preempt_tracer_trace = <0>;
		preempt_th1_ms = <30000>;
		preempt_th2_ms = <90000>;
		preempt_th3_ms = <90000>;
		preempt_aee_limit = <0>;
#endif
#endif
	};
#endif

	ssusb_ip_sleep: ssusb_ip_sleep {
		compatible = "mediatek,usb_ipsleep";
		interrupt-parent = <&pio>;
		interrupts = <219 IRQ_TYPE_LEVEL_LOW 223 0>;
	};
};

&spmi_bus {
#ifdef CONFIG_FPGA_EARLY_PORTING
	grpid = <8>;
	mt6315_10: mt6315@10 {
		compatible = "mediatek,mt6315", "mtk,spmi-pmic";
		reg = <0xa SPMI_USID 0x8 SPMI_GSID>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
	mt6315_11: mt6315@11 {
		compatible = "mediatek,mt6315", "mtk,spmi-pmic";
		reg = <0xb SPMI_USID 0x8 SPMI_GSID>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
	mt6315_12: mt6315@12 {
		compatible = "mediatek,mt6315", "mtk,spmi-pmic";
		reg = <0xc SPMI_USID 0x8 SPMI_GSID>;
		#address-cells = <1>;
		#size-cells = <0>;
	};
#else
	grpid = <11>;
	mt6315_6: mt6315@6 {
		compatible = "mediatek,mt6315", "mtk,spmi-pmic";
		reg = <0x6 SPMI_USID 0xb SPMI_GSID>;
		#address-cells = <1>;
		#size-cells = <0>;
		mt6315_6_regulator: mt6315_6_regulator {
			compatible = "mediatek,mt6315_6-regulator";
			interrupt-parent = <&pio>;
			interrupts = <1 IRQ_TYPE_LEVEL_HIGH 1 0>;
		};
	};
	mt6315_7: mt6315@7 {
		compatible = "mediatek,mt6315", "mtk,spmi-pmic";
		reg = <0x7 SPMI_USID 0xb SPMI_GSID>;
		#address-cells = <1>;
		#size-cells = <0>;
		mt6315_7_regulator: mt6315_7_regulator {
			compatible = "mediatek,mt6315_7-regulator";
			interrupt-parent = <&pio>;
			interrupts = <167 IRQ_TYPE_LEVEL_HIGH 167 0>;
		};
	};
	mt6315_3: mt6315@3 {
		compatible = "mediatek,mt6315", "mtk,spmi-pmic";
		reg = <0x3 SPMI_USID 0xb SPMI_GSID>;
		#address-cells = <1>;
		#size-cells = <0>;
		mt6315_3_regulator: mt6315_3_regulator {
			compatible = "mediatek,mt6315_3-regulator";
			interrupt-parent = <&pio>;
			interrupts = <2 IRQ_TYPE_LEVEL_HIGH 2 0>;
		};
	};
#endif
};

&mt6360_pmic {
	ldo6 {
		/delete-property/ regulator-always-on;
	};
};

&i2c6 {
	speaker_amp: speaker_amp@34 {
		compatible = "mediatek,speaker_amp";
		#sound-dai-cells = <0>;
		reg = <0x34>;
		status = "okay";
	};
};

&pio {
	aud_clk_mosi_off: aud_clk_mosi_off {
		pins_cmd0_dat {
			pinmux = <PINMUX_GPIO214__FUNC_GPIO214>;
			input-enable;
			bias-pull-down;
		};
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO215__FUNC_GPIO215>;
			input-enable;
			bias-pull-down;
		};
	};
	aud_clk_mosi_on: aud_clk_mosi_on {
		pins_cmd0_dat {
			pinmux = <PINMUX_GPIO214__FUNC_AUD_CLK_MOSI>;
			input-schmitt-enable;
			bias-disable;
		};
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO215__FUNC_AUD_SYNC_MOSI>;
			input-schmitt-enable;
			bias-disable;
		};
	};
	aud_dat_mosi_off: aud_dat_mosi_off {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO216__FUNC_GPIO216>;
			input-enable;
			bias-pull-down;
		};
		pins_cmd2_dat {
			pinmux = <PINMUX_GPIO217__FUNC_GPIO217>;
			input-enable;
			bias-pull-down;
		};
	};
	aud_dat_mosi_on: aud_dat_mosi_on {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO216__FUNC_AUD_DAT_MOSI0>;
			input-schmitt-enable;
			bias-disable;
		};
		pins_cmd2_dat {
			pinmux = <PINMUX_GPIO217__FUNC_AUD_DAT_MOSI1>;
			input-schmitt-enable;
			bias-disable;
		};
	};
	aud_dat_mosi_ch34_off: aud_dat_mosi_ch34_off {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO196__FUNC_GPIO196>;
			input-enable;
			bias-pull-down;
		};
	};
	aud_dat_mosi_ch34_on: aud_dat_mosi_ch34_on {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO196__FUNC_AUD_DAT_MOSI2>;
			input-schmitt-enable;
			bias-disable;
		};
	};
	aud_dat_miso_off: aud_dat_miso_off {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO218__FUNC_GPIO218>;
			input-enable;
			bias-pull-down;
		};
		pins_cmd2_dat {
			pinmux = <PINMUX_GPIO219__FUNC_GPIO219>;
			input-enable;
			bias-disable;
		};
	};
	aud_dat_miso_on: aud_dat_miso_on {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO218__FUNC_AUD_DAT_MISO0>;
			input-schmitt-enable;
			bias-disable;
		};
		pins_cmd2_dat {
			pinmux = <PINMUX_GPIO219__FUNC_AUD_DAT_MISO1>;
			input-schmitt-enable;
			bias-disable;
		};
	};
	aud_dat_miso_ch34_off: aud_dat_miso_ch34_off {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO199__FUNC_GPIO199>;
			input-enable;
			bias-pull-down;
		};
	};
	aud_dat_miso_ch34_on: aud_dat_miso_ch34_on {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>;
			input-schmitt-enable;
			bias-disable;
		};
	};
	vow_dat_miso_off: vow_dat_miso_off {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO218__FUNC_GPIO218>;
			input-enable;
			bias-pull-down;
		};
	};
	vow_dat_miso_on: vow_dat_miso_on {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO218__FUNC_VOW_DAT_MISO>;
			input-schmitt-enable;
			bias-disable;
		};
	};
	vow_clk_miso_off: vow_clk_miso_off {
		pins_cmd3_dat {
			pinmux = <PINMUX_GPIO219__FUNC_GPIO219>;
			input-enable;
			bias-pull-down;
		};
	};
	vow_clk_miso_on: vow_clk_miso_on {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO219__FUNC_VOW_CLK_MISO>;
			input-schmitt-enable;
			bias-disable;
		};
	};
	aud_nle_mosi_off: aud_nle_mosi_off {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO197__FUNC_GPIO197>;
			input-enable;
			bias-pull-down;
		};
		pins_cmd2_dat {
			pinmux = <PINMUX_GPIO198__FUNC_GPIO198>;
			input-enable;
			bias-pull-down;
		};
	};
	aud_nle_mosi_on: aud_nle_mosi_on {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO197__FUNC_AUD_NLE_MOSI1>;
			input-schmitt-enable;
			bias-disable;
		};
		pins_cmd2_dat {
			pinmux = <PINMUX_GPIO198__FUNC_AUD_NLE_MOSI0>;
			input-schmitt-enable;
			bias-disable;
		};
	};
	aud_dat_miso2_off: aud_dat_miso2_off {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO199__FUNC_GPIO199>;
			input-enable;
			bias-pull-down;
		};
	};
	aud_dat_miso2_on: aud_dat_miso2_on {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO199__FUNC_AUD_DAT_MISO2>;
			input-schmitt-enable;
			bias-disable;
		};
	};
	aud_gpio_i2s0_off: aud_gpio_i2s0_off {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO34__FUNC_GPIO34>;
			input-enable;
			bias-pull-down;
		};
	};
	aud_gpio_i2s0_on: aud_gpio_i2s0_on {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO34__FUNC_I2S0_DI>;
			input-schmitt-enable;
			bias-disable;
		};
	};
	aud_gpio_i2s1_off: aud_gpio_i2s1_off {
	};
	aud_gpio_i2s1_on: aud_gpio_i2s1_on {
	};
	aud_gpio_i2s2_off: aud_gpio_i2s2_off {
	};
	aud_gpio_i2s2_on: aud_gpio_i2s2_on {
	};
	aud_gpio_i2s3_off: aud_gpio_i2s3_off {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO32__FUNC_GPIO32>;
			input-enable;
			bias-pull-down;
		};
		pins_cmd2_dat {
			pinmux = <PINMUX_GPIO33__FUNC_GPIO33>;
			input-enable;
			bias-pull-down;
		};
		pins_cmd3_dat {
			pinmux = <PINMUX_GPIO35__FUNC_GPIO35>;
			input-enable;
			bias-pull-down;
		};
	};
	aud_gpio_i2s3_on: aud_gpio_i2s3_on {
		pins_cmd1_dat {
			pinmux = <PINMUX_GPIO32__FUNC_I2S3_BCK>;
			input-schmitt-enable;
			bias-disable;
		};
		pins_cmd2_dat {
			pinmux = <PINMUX_GPIO33__FUNC_I2S3_LRCK>;
			input-schmitt-enable;
			bias-disable;
		};
		pins_cmd3_dat {
			pinmux = <PINMUX_GPIO35__FUNC_I2S3_DO>;
			input-schmitt-enable;
			bias-disable;
		};
	};
	aud_gpio_i2s5_off: aud_gpio_i2s5_off {
	};
	aud_gpio_i2s5_on: aud_gpio_i2s5_on {
	};
	aud_gpio_i2s6_off: aud_gpio_i2s6_off {
	};
	aud_gpio_i2s6_on: aud_gpio_i2s6_on {
	};
	aud_gpio_i2s7_off: aud_gpio_i2s7_off {
	};
	aud_gpio_i2s7_on: aud_gpio_i2s7_on {
	};
	aud_gpio_i2s8_off: aud_gpio_i2s8_off {
	};
	aud_gpio_i2s8_on: aud_gpio_i2s8_on {
	};
	aud_gpio_i2s9_off: aud_gpio_i2s9_off {
	};
	aud_gpio_i2s9_on: aud_gpio_i2s9_on {
	};
};

#include "mediatek/mt6315_s6.dtsi"
#include "mediatek/mt6315_s7.dtsi"
#include "mediatek/mt6315_s3.dtsi"
#include "mediatek/mt6359p.dtsi"
#include "mediatek/cust_mt6885_msdc.dtsi"
#include "mediatek/mt6360_pd.dtsi"
#ifdef CONFIG_MTK_ENABLE_GENIEZONE
#include "mediatek/trusty.dtsi"
#endif