/* SPDX-License-Identifier: GPL-2.0 */ /* * Copyright (c) 2019 MediaTek Inc. */ #include #include #include #include #include #include #include #include #include #include "mtk_drm_ddp.h" #include "mtk_drm_crtc.h" #include "mtk_drm_drv.h" #include "mtk_drm_ddp_comp.h" #include "mtk_dump.h" #include "mtk_drm_mmp.h" #include "mtk_disp_aal.h" #ifdef CONFIG_MTK_SMI_EXT #include "smi_public.h" #endif #define DISP_REG_OVL0_MOUT_EN(data) (data->ovl0_mout_en) #define DISP_REG_DPI0_SEL_IN(data) (data->dpi0_sel_in) #define DISP_REG_DPI0_SEL_IN_RDMA1(data) (data->dpi0_sel_in_rdma1) #define DISP_REG_RDMA0_SOUT_SEL_IN(data) (data->rdma0_sout_sel_in) #define DISP_REG_RDMA0_SOUT_COLOR0(data) (data->rdma0_sout_color0) #define DISP_REG_RDMA0_SOUT_DSI0 0x0 #define DISP_REG_RDMA1_SOUT_SEL_IN(data) (data->rdma1_sout_sel_in) #define DISP_REG_RDMA1_SOUT_DPI0(data) (data->rdma1_sout_dpi0) #define DISP_REG_RDMA1_SOUT_DSI0(data) (data->rdma1_sout_dsi0) #define MT2701_DISP_OVL0_MOUT_EN 0x030 #define MT2712_DISP_OVL0_MOUT_EN 0x030 #define MT8173_DISP_OVL0_MOUT_EN 0x040 #define MT6779_DISP_OVL0_MOUT_EN 0xf08 #define MT6885_DISP_OVL0_MOUT_EN 0xf10 #define DISP_OVL1_2L_MOUT_EN 0xf0c // for MT6779 #define DISP_REG_CONFIG_DISP_OVL0_2L_MOUT_EN 0xf04 #define DISP_REG_CONFIG_DISP_RSZ_SEL_IN 0xf7C #define DISP_REG_CONFIG_DISP_RSZ_MOUT_EN 0xf10 #define DISP_REG_CONFIG_DISP_RDMA0_RSZ_IN_SOUT_SEL_IN 0xf40 #define DISP_REG_CONFIG_DISP_RDMA0_RSZ_OUT_SEL_IN 0xf78 #define DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN 0xf44 #define DISP_REG_CONFIG_DISP_COLOR0_OUT_SEL_IN 0xf68 #define DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xf00 #define DISP_REG_CONFIG_DISP_DSI0_SEL_IN 0xf8c #define DISP_REG_CONFIG_DISP_PATH0_SEL_IN 0xf74 #define DISP_REG_CONFIG_DISP_OVL0_2L_WCG_MOUT_EN 0xf38 #define DISP_REG_CONFIG_DISP_OVL0_WCG_SEL_IN 0xfc8 #define OVL0_2L_MOUT_EN_RSZ_SEL BIT(4) #define RSZ_SEL_IN_RDMA0_RSZ_IN_SOUT 0x3 #define RSZ_SEL_IN_OVL0_MOUT 0x4 #define RSZ_SEL_IN_OVL0_2L_MOUT 0x5 #define RSZ_MOUT_EN_OVL0 BIT(0) #define RSZ_MOUT_EN_DISP_PATH0_SEL BIT(3) #define RSZ_MOUT_EN_RDMA0_RSZ_OUT_SEL BIT(5) #define RDMA0_RSZ_IN_SOUT_RDMA0_RSZ_OUT_SEL 0x0 #define RDMA0_RSZ_IN_SOUT_RSZ_SEL 0x1 #define RDMA0_RSZ_OUT_SEL_IN_RDMA0 0x0 #define RDMA0_RSZ_OUT_SEL_IN_RSZ 0x1 #define RDMA0_SOUT_COLOR0 0x1 #define COLOR0_OUT_SEL_IN_COLOR0 0x0 #define DITHER0_MOUT_EN_DSI0 BIT(0) #define DSI0_SEL_IN_DITHER0 0x0 #define DSI0_SEL_IN_RDMA0 0x1 #define PATH0_SEL_IN_OVL0 0x0 #define PATH0_SEL_IN_RSZ 0x3 #define OVL0_2L_WCG_MOUT_EN_OVL0 BIT(0) #define OVL0_WCG_SEL_IN_EN_OVL0_2L 0x0 #define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN 0x044 #define DISP_REG_CONFIG_DISP_OD_MOUT_EN 0x048 #define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN 0x04c #define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN 0x050 #define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN 0x084 #define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN 0x088 #define DISP_REG_CONFIG_DSI1_SEL_IN 0x0a8 #define DISP_REG_CONFIG_DISP_DPI0_SEL_IN 0x0ac #define DISP_REG_CONFIG_DISP_PATH1_SOUT_SEL_IN 0x0c8 #define DISP_REG_CONFIG_DISP_WDMA0_SEL_IN 0x098 #define DISP_REG_CONFIG_DISP_WDMA1_SEL_IN 0x09c #define DISP_REG_CONFIG_DISP_WDMA0_PRE_SEL_IN 0xF80 #define DISP_REG_CONFIG_DISP_WDMA0_SEL_IN2 0xF84 #define DISP_REG_CONFIG_DISP_OVL_TO_WDMA_SEL_IN 0xFC0 #define DISP_REG_CONFIG_OUT_SEL 0x04c #define DISP_REG_CONFIG_DSI_SEL 0x050 #define MT2701_DISP_MUTEX0_MOD0 0x2C #define MT2701_DISP_MUTEX0_SOF 0x30 #define MT2712_DISP_MUTEX0_MOD0 0x2C #define MT2712_DISP_MUTEX0_SOF 0x30 #define MT8173_DISP_MUTEX0_MOD0 0x2C #define MT8173_DISP_MUTEX0_SOF 0x30 #define MT6779_DISP_MUTEX0_MOD0 0x30 #define MT6779_DISP_MUTEX0_SOF 0x2C #define DISP_REG_CONFIG_DISP_RDMA0_MOUT_EN 0x0c4 #define DISP_REG_CONFIG_DISP_RDMA1_MOUT_EN 0x0c8 #define DISP_REG_CONFIG_MMSYS_MISC 0x0F0 #define FLD_SHARE_WROT_SEL REG_FLD_MSB_LSB(6, 6) #define FLD_OVL0_ULTRA_SEL REG_FLD_MSB_LSB(5, 2) #define FLD_OVL0_2L_ULTRA_SEL REG_FLD_MSB_LSB(9, 6) #define FLD_OVL1_ULTRA_SEL REG_FLD_MSB_LSB(13, 10) #define FLD_OVL1_2L_ULTRA_SEL REG_FLD_MSB_LSB(17, 14) #define FLD_OVL2_2L_ULTRA_SEL REG_FLD_MSB_LSB(21, 18) #define FLD_OVL3_2L_ULTRA_SEL REG_FLD_MSB_LSB(25, 22) #define DISP_REG_CONFIG_MMSYS_SODI_REQ_MASK 0x0F4 #define FLD_SODI_REQ_SEL REG_FLD_MSB_LSB(11, 8) #define FLD_SODI_REQ_VAL REG_FLD_MSB_LSB(15, 12) #define FLD_SODI_POSTMASK_EN REG_FLD_MSB_LSB(31, 31) #define DISP_REG_CONFIG_MMSYS_CG_CON0 0x100 #define DISP_REG_CONFIG_MMSYS_CG_CON1 0x110 #define DISP_REG_CONFIG_DISP_DL_VALID_0 0x8cc #define DISP_REG_CONFIG_DISP_DL_VALID_1 0x8d0 #define DISP_REG_CONFIG_DISP_DL_VALID_2 0x8d4 #define DISP_REG_CONFIG_DISP_DL_VALID_3 0x8d8 #define DISP_REG_CONFIG_DISP_DL_VALID_4 0x8dc #define DISP_REG_CONFIG_DISP_DL_READY_0 0x8e0 #define DISP_REG_CONFIG_DISP_DL_READY_1 0x8e4 #define DISP_REG_CONFIG_DISP_DL_READY_2 0x8e8 #define DISP_REG_CONFIG_DISP_DL_READY_3 0x8ec #define DISP_REG_CONFIG_DISP_DL_READY_4 0x8f0 #define DISP_REG_CONFIG_SMI_LARB_GREQ 0x8f4 #define DISP_REG_MUTEX_INTEN 0x00 #define DISP_REG_MUTEX_INTSTA 0x04 #define DISP_REG_MUTEX_CFG 0x08 #define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n)) #define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n)) #define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n)) #define DISP_REG_MUTEX_SOF(data, n) (data->mutex_sof_reg + 0x20 * (n)) #define DISP_REG_MUTEX_MOD(data, n) (data->mutex_mod_reg + 0x20 * (n)) #define DISP_REG_MUTEX_MOD2(n) (0x34 + 0x20 * (n)) #define SOF_FLD_MUTEX0_SOF REG_FLD(3, 0) #define SOF_FLD_MUTEX0_SOF_TIMING REG_FLD(2, 3) #define SOF_FLD_MUTEX0_SOF_WAIT REG_FLD(1, 5) #define SOF_FLD_MUTEX0_EOF REG_FLD(3, 6) #define SOF_FLD_MUTEX0_FOF_TIMING REG_FLD(2, 9) #define SOF_FLD_MUTEX0_EOF_WAIT REG_FLD(1, 11) #define INT_MUTEX BIT(1) #define MT8173_MUTEX_MOD_DISP_OVL0 BIT(11) #define MT8173_MUTEX_MOD_DISP_OVL1 BIT(12) #define MT8173_MUTEX_MOD_DISP_RDMA0 BIT(13) #define MT8173_MUTEX_MOD_DISP_RDMA1 BIT(14) #define MT8173_MUTEX_MOD_DISP_RDMA2 BIT(15) #define MT8173_MUTEX_MOD_DISP_WDMA0 BIT(16) #define MT8173_MUTEX_MOD_DISP_WDMA1 BIT(17) #define MT8173_MUTEX_MOD_DISP_COLOR0 BIT(18) #define MT8173_MUTEX_MOD_DISP_COLOR1 BIT(19) #define MT8173_MUTEX_MOD_DISP_AAL BIT(20) #define MT8173_MUTEX_MOD_DISP_GAMMA BIT(21) #define MT8173_MUTEX_MOD_DISP_UFOE BIT(22) #define MT8173_MUTEX_MOD_DISP_PWM0 BIT(23) #define MT8173_MUTEX_MOD_DISP_PWM1 BIT(24) #define MT8173_MUTEX_MOD_DISP_OD BIT(25) #define MT2712_MUTEX_MOD_DISP_OVL0 BIT(11) #define MT2712_MUTEX_MOD_DISP_OVL1 BIT(12) #define MT2712_MUTEX_MOD_DISP_RDMA0 BIT(13) #define MT2712_MUTEX_MOD_DISP_RDMA1 BIT(14) #define MT2712_MUTEX_MOD_DISP_RDMA2 BIT(15) #define MT2712_MUTEX_MOD_DISP_WDMA0 BIT(16) #define MT2712_MUTEX_MOD_DISP_WDMA1 BIT(17) #define MT2712_MUTEX_MOD_DISP_COLOR0 BIT(18) #define MT2712_MUTEX_MOD_DISP_COLOR1 BIT(19) #define MT2712_MUTEX_MOD_DISP_AAL BIT(20) #define MT2712_MUTEX_MOD_DISP_UFOE BIT(22) #define MT2712_MUTEX_MOD_DISP_PWM0 BIT(23) #define MT2712_MUTEX_MOD_DISP_PWM1 BIT(24) #define MT2712_MUTEX_MOD_DISP_PWM2 BIT(10) #define MT2712_MUTEX_MOD_DISP_OD BIT(25) /* modules more than 32, add BIT(31) when using DISP_REG_MUTEX_MOD2 bit */ #define MT2712_MUTEX_MOD2_DISP_AAL1 (BIT(1) | BIT(31)) #define MT2712_MUTEX_MOD2_DISP_OD1 (BIT(2) | BIT(31)) #define MT2701_MUTEX_MOD_DISP_OVL BIT(3) #define MT2701_MUTEX_MOD_DISP_WDMA BIT(6) #define MT2701_MUTEX_MOD_DISP_COLOR BIT(7) #define MT2701_MUTEX_MOD_DISP_BLS BIT(9) #define MT2701_MUTEX_MOD_DISP_RDMA0 BIT(10) #define MT2701_MUTEX_MOD_DISP_RDMA1 BIT(12) #define MT6779_MUTEX_MOD_DISP_RDMA0 BIT(0) #define MT6779_MUTEX_MOD_DISP_RDMA1 BIT(1) #define MT6779_MUTEX_MOD_DISP_OVL0 BIT(9) #define MT6779_MUTEX_MOD_DISP_OVL0_2L BIT(10) #define MT6779_MUTEX_MOD_DISP_OVL1_2L BIT(11) #define MT6779_MUTEX_MOD_DISP_WDMA0 BIT(12) #define MT6779_MUTEX_MOD_DISP_COLOR0 BIT(13) #define MT6779_MUTEX_MOD_DISP_CCORR BIT(14) #define MT6779_MUTEX_MOD_DISP_AAL BIT(15) #define MT6779_MUTEX_MOD_DISP_GAMMA BIT(16) #define MT6779_MUTEX_MOD_DISP_DITHER BIT(17) #define MT6779_MUTEX_MOD_DISP_PWM0 BIT(18) #define MT6779_MUTEX_MOD_DISP_DSI0 BIT(19) #define MT6779_MUTEX_MOD_DISP_POSTMASK BIT(21) #define MT6779_MUTEX_MOD_DISP_RSZ BIT(22) #define MUTEX_SOF_SINGLE_MODE 0 #define MUTEX_SOF_DSI0 1 #define MUTEX_SOF_DSI1 2 #define MUTEX_SOF_DPI0 3 #define MUTEX_SOF_DPI1 4 #define MT6779_MUTEX_SOF_SINGLE_MODE 0 #define MT6779_MUTEX_SOF_DSI0 1 #define MT6779_MUTEX_SOF_DPI0 2 #define MT6779_MUTEX_EOF_DSI0 (MT6779_MUTEX_SOF_DSI0 << 6) #define MT6779_MUTEX_EOF_DPI0 (MT6779_MUTEX_SOF_DPI0 << 6) #define OVL0_MOUT_EN_COLOR0 0x1 #define OVL0_MOUT_EN_WDMA0 BIT(2) #define OD_MOUT_EN_RDMA0 0x1 #define OD_MOUT_EN_WDMA0 0x4 #define OD1_MOUT_EN_RDMA1 BIT(16) #define OD1_MOUT_EN_WDMA1 BIT(18) #define UFOE_MOUT_EN_DSI0 0x1 #define COLOR0_SEL_IN_OVL0 0x1 #define OVL1_MOUT_EN_COLOR1 0x1 #define GAMMA_MOUT_EN_RDMA1 0x1 #define RDMA0_MOUT_DPI0 0x2 #define RDMA0_MOUT_DSI2 0x4 #define RDMA0_MOUT_DSI3 0x5 #define RDMA1_MOUT_DSI1 0x1 #define RDMA1_MOUT_DPI0 0x2 #define RDMA1_MOUT_DPI1 0x3 #define DPI0_SEL_IN_RDMA1 0x1 #define DPI1_SEL_IN_RDMA1 BIT(8) #define DSI1_SEL_IN_RDMA1 0x1 #define COLOR1_SEL_IN_OVL1 0x1 #define WDMA0_SEL_IN_OD0 0x0 #define WDMA1_SEL_IN_OD1 0x0 #define WDMA0_SEL_IN_WDMA0_PRE 0x3 #define WDMA0_PRE_SEL_IN_OVL_TO_WDMA 0x0 #define OVL_TO_WDMA_SEL_IN_OVL0 0x0 #define OVL_TO_WDMA_SEL_IN_OVL1_2L 0x2 #define PATH1_SOUT_DSI0 0x0 #define PATH1_SOUT_DSI1 0x1 #define PATH1_SOUT_DPI0 0x2 #define PATH1_SOUT_DPI1 0x3 #define DPI0_SEL_IN_PATH1 0x1 #define OVL_MOUT_EN_RDMA 0x1 #define OVL_MOUT_EN_RSZ_SEL BIT(4) #define BLS_TO_DSI_RDMA1_TO_DPI1 0x8 #define DSI_SEL_IN_BLS 0x0 #define MT6885_DISP_AAL0_SEL_IN 0x650 #define DISP_AAL0_SEL_IN_FROM_DISP_MDP_AAL4_SOUT 0x0 #define DISP_AAL0_SEL_IN_FROM_DISP_CCORR0_SOUT 0x1 #define MT6885_DISP_COLOR0_OUT_SEL_IN 0x658 #define DISP_COLOR0_OUT_SEL_IN_FROM_DISP_COLOR0 0x0 #define MT6885_DISP_COLOR1_OUT_SEL_IN 0x65C #define DISP_COLOR1_OUT_SEL_IN_FROM_DISP_COLOR1 0x0 #define MT6885_DISP_CCORR0_SOUT_SEL 0xEB4 #define DISP_CCORR0_SOUT_SEL_TO_DMDP_AAL0_SEL 0x0 #define DISP_CCORR0_SOUT_SEL_TO_DISP_AAL0_SEL 0x1 #define MT6885_DISP_MDP_AAL4_SEL_IN 0xEB8 #define DISP_MDP_AAL4_SEL_IN_FROM_DISP_CCORR0_SOUT 0x0 #define MT6885_DISP_MDP_AAL5_SEL_IN 0xEBC #define DISP_MDP_AAL5_SEL_IN_FROM_DISP_CCORR1_SOUT 0x0 #define MT6885_DISP_MDP_AAL4_SOUT_SEL 0xEC0 #define DISP_MDP_AAL4_SOUT_SEL_TO_DISP_AAL0_SEL 0x0 #define MT6885_DISP_MDP_AAL5_SOUT_SEL 0xEC4 #define DISP_MDP_AAL5_SOUT_SEL_TO_DISP_AAL1_SEL 0x0 #define MT6885_DISP_RDMA1_RSZ1_SEL_IN 0xF0C #define DISP_RDMA1_RSZ1_SEL_IN_FROM_DISP_RDMA1_SOUT 0x0 #define MT6885_DISP_TOVL0_OUT0_MOUT_EN 0xF10 #define DISP_TOVL0_OUT0_MOUT_TO_DISP_RSZ0_SEL BIT(1) #define MT6885_DISP_RDMA2_RSZ0_RSZ1_SEL_IN 0xF18 #define DISP_RDMA2_RSZ0_RSZ1_SEL_IN_FROM_DISP_RSZ0_MOUT 0x0 #define DISP_RDMA2_RSZ0_RSZ1_SEL_IN_FROM_DISP_RSZ1_MOUT 0x1 #define MT6885_DISP_RDMA4_SOUT 0xF24 #define DISP_RDMA4_TO_DISP_MERGE1 0x0 #define DISP_RDMA4_TO_DISP_RDMA4_PQ0_MERGE0_SEL 0x1 #define DISP_RDMA4_TO_DISP_DP_WRAP_SEL 0x2 #define MT6885_DISP_RDMA5_SOUT 0xF28 #define DISP_RDMA5_TO_DISP_MERGE1 0x0 #define DISP_RDMA5_TO_DISP_RDMA5_PQ1_SEL 0x1 #define MT6885_DISP_OVL0_2L_BLENDOUT_SOUT_SEL 0xF2C #define DISP_OVL0_2L_BLENDOUT_SOUT_SEL_TO_DISP_TOVL0_OUT0_SEL 0x0 #define MT6885_DISP_TOVL0_OUT0_SEL_IN 0xF30 #define DISP_TOVL0_OUT0_SEL_IN_FROM_DISP_OVL0_2L_BLENDOUT_SOUT 0x0 #define MT6885_DISP_RDMA0_SEL_IN 0xF34 #define DISP_RDMA0_SEL_IN_FROM_DISP_TOVL0_OUT1_MOUT 0x0 #define MT6885_DISP_RDMA0_SOUT_SEL 0xF38 #define DISP_RDMA0_SOUT_SEL_TO_DISP_RDMA0_RSZ0_SEL 0x0 #define MT6885_DISP_RDMA0_RSZ0_SEL_IN 0xF3C #define DISP_RDMA0_RSZ0_SEL_IN_FROM_DISP_RDMA0_SOUT 0x0 #define MT6885_DISP_RDMA0_RSZ0_SOUT_SEL 0xF40 #define DISP_RDMA0_RSZ0_SOUT_SEL_TO_DSI0_SEL_IN 0x0 #define DISP_RDMA0_RSZ0_SOUT_SEL_TO_DISP_COLOR0 0x1 #define MT6885_DISP_OVL2_2L_OUT0_MOUT 0xF44 #define DISP_OVL2_2L_OUT0_MOUT_TO_DISP_RDMA4 0x1 #define DISP_OVL2_2L_OUT0_MOUT_TO_DISP_WDMA0 0x2 #define MT6885_DISP_DSC_WRAP_SOUT_SEL 0xF48 #define DISP_DSC_WRAP_SOUT_TO_DISP_DP_WRAP_SEL 0x1 #define MT6885_MMSYS_OVL_CON 0xF4C #define DISP_OVL0_TO_DISP_OVL0_BLENDOUT_SOUT BIT(0) #define DISP_OVL0_2L_TO_DISP_OVL0_2L_BLENDOUT_SOUT BIT(2) #define DISP_OVL0_2L_TO_DISP_OVL0_2L_OVL1_OVL1_2L_BGOUT_SEL BIT(3) #define DISP_OVL1_TO_DISP_OVL1_BLENDOUT_SOUT BIT(4) #define DISP_OVL1_2L_TO_DISP_OVL1_2L_BLENDOUT_SOUT BIT(6) #define DISP_OVL0_2L_TO_DISP_OVL1_2L_OVL1_OVL1_2L_BGOUT_SEL BIT(7) #define DISP_OVL3_2L_TO_DISP_RDMA5 BIT(8) #define DISP_OVL3_2L_TO_DISP_OVL2_2L BIT(9) #define MT6885_DISP_DITHER0_MOUT_EN 0xF50 #define DISP_DITHER0_MOUT_EN_TO_DSI0_SEL BIT(0) #define DISP_DITHER0_MOUT_EN_TO_WDMA0_SEL BIT(1) #define DISP_DITHER0_MOUT_EN_TO_PQ0_SOUT BIT(3) #define MT6885_DSI0_SEL_IN 0xF54 #define DSI0_SEL_IN_FROM_DISP_DITHER0_MOUT 0x1 #define MT6885_DISP_WDMA0_SEL_IN 0xF58 #define MT6885_WDMA0_SEL_IN_FROM_DISP_DITHER0_MOUT 0x0 #define MT6885_WDMA0_SEL_IN_FROM_DISP_RSZ0_MOUT 0x1 #define MT6885_WDMA0_SEL_IN_FROM_DISP_TOVL0_OUT0_MOUT 0x2 #define MT6885_WDMA0_SEL_IN_FROM_DISP_TOVL0_OUT1_MOUT 0x3 #define MT6885_WDMA0_SEL_IN_FROM_DISP_TOVL2_2L_OUT0_MOUT 0x4 #define MT6885_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL 0xF64 #define DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL_TO_DISP_OVL0 0x1 #define MT6885_DISP_OVL0_2L_OVL1_OVL1_2L_BGOUT_SEL 0xF68 #define DISP_OVL0_2L_OVL1_OVL1_2L_BGOUT_SEL_FROM_DISP_OVL0_2L 0x1 #define MT6885_DISP_OVL0_BLENDOUT_SOUT_SEL 0xF6C #define DISP_OVL0_BLENDOUT_SOUT_SEL_TO_DISP_TOVL0_OUT1_SEL 0x1 #define MT6885_DISP_TOVL0_OUT1_SEL_IN 0xF70 #define DISP_TOVL0_OUT1_SEL_IN_FROM_DISP_OVL0_BLENDOUT_SOUT 0x1 #define MT6885_DISP_TOVL0_OUT1_MOUT_EN 0xF74 #define DISP_TOVL0_OUT1_MOUT_EN_TO_DISP_RDMA0_SEL BIT(0) #define DISP_TOVL0_OUT1_MOUT_EN_TO_DISP_WDMA0_SEL BIT(2) #define MT6885_DISP_RSZ0_SEL_IN 0xF78 #define DISP_RSZ0_SEL_IN_FROM_DISP_TOVL0_OUT0_MOUT 0x0 #define MT6885_DISP_RSZ0_MOUT_EN 0xF7C #define DISP_RSZ0_MOUT_EN_TO_DISP_RDMA2_RSZ0_RSZ1_SEL BIT(3) #define MT6885_DISP_DSI0_DSC_WRAP_SOUT_SEL 0xF80 #define MT6885_DISP_DSI0_DSC_WRAP_SOUT_TO_DISP_DSC_WRAP0 0x1 #define MT6885_DISP_DP_WRAP_SEL_IN 0xF84 #define DISP_DSC_WRAP_SOUT_TO_DISP_DP_INTF0 0x0 #define DISP_MERGE1_TO_DISP_DP_INTF0 0x1 #define DISP_DISP_RDMA4_SOUT_TO_DISP_DP_INTF0 0x2 #define MT6885_DISP_RDMA4_PQ0_MERGE0_SEL_IN 0xF88 #define DISP_RDMA4_SOUT_TO_DISP_RDMA4_PQ0_MERGE0_SEL 0x0 #define MT6885_DISP_RDMA5_PQ1_SEL_IN 0xF8C #define MT6885_DISP_RDMA5_PQ1_SEL_IN_FROM_RDMA5_SOUT 0x0 #define MT6885_DISP_RDMA5_PQ1_SEL_IN_FROM_PQ1_SOUT 0x1 #define MT6885_DISP_RSZ1_MOUT_EN 0xF90 #define DISP_RSZ1_MOUT_EN_TO_DISP_RDMA2_RSZ0_RSZ1_SEL BIT(3) #define DISP_RSZ1_MOUT_EN_TO_DISP_RDMA3_SOUT BIT(4) #define MT6885_DISP_RDMA3_SOUT_SEL 0xF98 #define DISP_RDMA3_SOUT_SEL_TO_DISP_OVL1 0x1 #define MT6885_DISP_OVL1_2L_BLENDOUT_SOUT_SEL 0xFA0 #define DISP_OVL1_2L_BLENDOUT_SOUT_SEL_TO_DISP_TOVL1_OUT0_SEL 0x0 #define MT6885_DISP_OVL1_2L_BGOUT_SOUT_SEL 0xFA4 #define DISP_OVL1_2L_BGOUT_SOUT_SEL_TO_DISP_OVL1 0x0 #define MT6885_DISP_OVL1_BLENDOUT_SOUT_SEL 0xFA8 #define DISP_OVL1_BLENDOUT_SOUT_SEL_TO_DISP_TOVL1_OUT1_SEL 0x1 #define MT6885_DISP_TOVL1_OUT0_SEL_IN 0xFB0 #define DISP_TOVL1_OUT0_SEL_IN_FROM_DISP_OVL1_2L_BLENDOUT_SOUT 0x0 #define MT6885_DISP_TOVL1_OUT1_SEL_IN 0xFB4 #define DISP_TOVL1_OUT1_SEL_IN_FROM_DISP_OVL1_BLENDOUT_SOUT 0x1 #define MT6885_DISP_TOVL1_OUT1_MOUT_EN 0xFBC #define DISP_TOVL1_OUT1_MOUT_EN_TO_DISP_RDMA1_SEL BIT(0) #define DISP_TOVL1_OUT1_MOUT_EN_TO_DISP_WDMA1_SEL BIT(2) #define MT6885_DISP_TOVL1_OUT0_MOUT_EN 0xFC0 #define DISP_TOVL1_OUT0_MOUT_TO_DISP_WDMA1_SEL BIT(0) #define DISP_TOVL1_OUT0_MOUT_TO_DISP_RSZ1_SEL BIT(1) #define MT6885_DISP_RDMA1_SEL_IN 0xFC4 #define DISP_RDMA1_SEL_IN_FROM_DISP_TOVL1_OUT1_MOUT 0x0 #define MT6885_DISP_RSZ1_SEL_IN 0xFC8 #define DISP_RSZ1_SEL_IN_FROM_DISP_TOVL1_OUT0_MOUT 0x0 #define MT6885_DISP_RDMA1_SOUT_SEL 0xFCC #define DISP_RDMA1_SOUT_SEL_TO_DISP_RDMA1_RSZ1_SEL 0x0 #define MT6885_DISP_CCORR1_SOUT_SEL 0xFD4 #define DISP_CCORR1_SOUT_SEL_TO_DISP_MDP_AAL5_SEL 0x0 #define DISP_CCORR1_SOUT_SEL_TO_DISP_AAL1_SEL 0x1 #define MT6885_DISP_AAL1_SEL_IN 0xFD8 #define DISP_AAL1_SEL_IN_FROM_DISP_MDP_AAL5_SOUT 0x0 #define DISP_AAL1_SEL_IN_FROM_DISP_CCORR1_SOUT 0x1 #define MT6885_DISP_RDMA1_RSZ1_SOUT_SEL 0xFDC #define DISP_RDMA1_RSZ1_SOUT_SEL_TO_DSI1_SEL_IN 0x0 #define DISP_RDMA1_RSZ1_SOUT_SEL_TO_DISP_COLOR1 0x1 #define MT6885_DISP_DITHER1_MOUT_EN 0xFE4 #define DISP_DITHER1_MOUT_EN_TO_DSI1_SEL BIT(0) #define DISP_DITHER1_MOUT_EN_TO_WDMA1_SEL BIT(1) #define DISP_DITHER1_MOUT_EN_TO_PQ1_SOUT BIT(2) #define MT6885_DISP_PQ1_SOUT_SEL 0xFE8 #define DISP_PQ1_SOUT_SEL_TO_DISP_MERGE0 0x0 #define DISP_PQ1_SOUT_SEL_TO_DISP_RDMA5_PQ1_SEL 0x1 #define MT6885_DISP_OVL3_2L_OUT0_MOUT 0xFEC #define DISP_OVL3_2L_OUT0_MOUT_TO_DISP_RDMA5 0x1 #define DISP_OVL3_2L_OUT0_MOUT_TO_DISP_WDMA1 0x2 #define MT6885_DSI1_SEL_IN 0xFF0 #define DSI1_SEL_IN_FROM_DISP_DITHER1_MOUT 0x1 #define DSI1_SEL_IN_FROM_DSC_WRAP0 0x3 #define MT6885_DISP_WDMA1_SEL_IN 0xFF4 #define MT6885_WDMA1_SEL_IN_FROM_DISP_DITHER1_MOUT 0x0 #define MT6885_WDMA1_SEL_IN_FROM_DISP_TOVL1_OUT0_MOUT 0x2 #define MT6885_WDMA1_SEL_IN_FROM_DISP_TOVL1_OUT1_MOUT 0x3 #define MT6885_WDMA1_SEL_IN_FROM_DISP_TOVL3_2L_OUT0_MOUT 0x4 #define MT6885_DISP_PQ0_SOUT_SEL 0xFF8 #define MT6885_DISP_MUTEX0_MOD0 0x30 #define MT6885_DISP_MUTEX0_SOF 0x2C #define MT6885_MUTEX_MOD0_DISP_OVL0 BIT(0) #define MT6885_MUTEX_MOD0_DISP_OVL0_2L BIT(1) #define MT6885_MUTEX_MOD0_DISP_RDMA0 BIT(2) #define MT6885_MUTEX_MOD0_DISP_WDMA0 BIT(3) #define MT6885_MUTEX_MOD0_DISP_COLOR0 BIT(4) #define MT6885_MUTEX_MOD0_DISP_CCORR0 BIT(5) #define MT6885_MUTEX_MOD0_DISP_AAL0 BIT(6) #define MT6885_MUTEX_MOD0_DISP_GAMMA0 BIT(7) #define MT6885_MUTEX_MOD0_DISP_DITHER0 BIT(8) #define MT6885_MUTEX_MOD0_DISP_DSI0 BIT(9) #define MT6885_MUTEX_MOD0_DISP_RSZ0 BIT(10) #define MT6885_MUTEX_MOD0_DISP_PWM0 BIT(11) #define MT6885_MUTEX_MOD0_DISP_OVL1 BIT(12) #define MT6885_MUTEX_MOD0_DISP_OVL1_2L BIT(13) #define MT6885_MUTEX_MOD0_DISP_RDMA1 BIT(14) #define MT6885_MUTEX_MOD0_DISP_WDMA1 BIT(15) #define MT6885_MUTEX_MOD0_DISP_COLOR1 BIT(16) #define MT6885_MUTEX_MOD0_DISP_CCORR1 BIT(17) #define MT6885_MUTEX_MOD0_DISP_AAL1 BIT(18) #define MT6885_MUTEX_MOD0_DISP_GAMMA1 BIT(19) #define MT6885_MUTEX_MOD0_DISP_DITHER1 BIT(20) #define MT6885_MUTEX_MOD0_DISP_DSI1 BIT(21) #define MT6885_MUTEX_MOD0_DISP_RSZ1 BIT(22) #define MT6885_MUTEX_MOD0_DISP_OVL2 BIT(23) #define MT6885_MUTEX_MOD0_DISP_OVL3 BIT(24) #define MT6885_MUTEX_MOD0_DISP_POSTMASK0 BIT(25) #define MT6885_MUTEX_MOD0_DISP_POSTMASK1 BIT(26) #define MT6885_MUTEX_MOD0_DISP_MERGE0 BIT(27) #define MT6885_MUTEX_MOD0_DISP_MERGE1 BIT(28) #define MT6885_MUTEX_MOD0_DISP_DSC0 BIT(29) #define MT6885_MUTEX_MOD0_DISP_DSC1 BIT(30) #define MT6885_MUTEX_MOD0_DISP_DP BIT(31) #define MT6885_MUTEX_MOD1_MDP_AAL4 (BIT(0) | BIT(31)) #define MT6885_MUTEX_MOD1_MDP_AAL5 (BIT(1) | BIT(31)) #define MT6885_MUTEX_MOD1_MDP_RDMA4 (BIT(2) | BIT(31)) #define MT6885_MUTEX_MOD1_MDP_RDMA5 (BIT(3) | BIT(31)) #define MT6885_MUTEX_MOD1_MDP_HDR4 (BIT(4) | BIT(31)) #define MT6885_MUTEX_MOD1_MDP_HDR5 (BIT(5) | BIT(31)) #define MT6885_MUTEX_MOD1_MDP_RSZ4 (BIT(6) | BIT(31)) #define MT6885_MUTEX_MOD1_MDP_RSZ5 (BIT(7) | BIT(31)) #define MT6885_MUTEX_MOD1_MDP_TDSHP4 (BIT(8) | BIT(31)) #define MT6885_MUTEX_MOD1_MDP_TDSHP5 (BIT(9) | BIT(31)) #define MT6885_MUTEX_MOD1_DISP_RDMA4 (BIT(10) | BIT(31)) #define MT6885_MUTEX_MOD1_DISP_RDMA5 (BIT(11) | BIT(31)) #define MT6885_MUTEX_SOF_SINGLE_MODE 0 #define MT6885_MUTEX_SOF_DSI0 1 #define MT6885_MUTEX_SOF_DPI0 3 #define MT6885_MUTEX_EOF_DSI0 (MT6885_MUTEX_SOF_DSI0 << 6) #define MT6885_MUTEX_EOF_DPI0 (MT6885_MUTEX_SOF_DPI0 << 6) #define DISP_REG_CONFIG_MMSYS_CG_CON0_MT6885 0x100 #define DISP_REG_CONFIG_MMSYS_CG_CON1_MT6885 0x110 #define MT6885_DISP_REG_CONFIG_DL_VALID_0 0xe9c #define MT6885_DISP_REG_CONFIG_DL_VALID_1 0xea0 #define MT6885_DISP_REG_CONFIG_DL_VALID_2 0xea4 #define MT6885_DISP_REG_CONFIG_DL_VALID_3 0xe80 #define MT6885_DISP_REG_CONFIG_DL_VALID_4 0xe84 #define MT6885_DISP_REG_CONFIG_DL_VALID_5 0xe88 #define MT6885_DISP_REG_CONFIG_DL_READY_0 0xea8 #define MT6885_DISP_REG_CONFIG_DL_READY_1 0xeac #define MT6885_DISP_REG_CONFIG_DL_READY_2 0xeb0 #define MT6885_DISP_REG_CONFIG_DL_READY_3 0xe70 #define MT6885_DISP_REG_CONFIG_DL_READY_4 0xe74 #define MT6885_DISP_REG_CONFIG_DL_READY_5 0xe78 #define MT6885_DISP_REG_CONFIG_SMI_LARB_GREQ 0x8dc /*For MT6873*/ #define MT6873_DISP_OVL0_MOUT_EN 0xf04 #define MT6873_MMSYS_OVL_CON 0xF04 #define DISP_OVL0_GO_BG BIT(1) #define DISP_OVL0_GO_BLEND BIT(0) #define DISP_OVL0_2L_GO_BG BIT(3) #define DISP_OVL0_2L_GO_BLEND BIT(2) #define MT6873_DISP_REG_CONFIG_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL 0xF08 #define SOUT_TO_DISP_OVL0_2L (0) #define SOUT_TO_DISP_OVL0 (1) #define MT6873_DISP_REG_CONFIG_DISP_MDP_TDSHP4_SOUT_SEL 0xF0C #define MT6873_DISP_REG_CONFIG_DISP_OVL0_2L_UFOD_SEL_IN 0xF10 #define MT6873_DISP_REG_CONFIG_DISP_OVL0_UFOD_SEL_IN 0xF14 #define SEL_IN_FROM_DISP_RDMA2_RSZ0_RSZ1_SOUT (0) #define SEL_IN_FROM_DISP_MDP_TDSHP4_SOUT (1) #define MT6873_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN 0xF18 #define MT6873_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN 0xF1C #define MOUT_TO_DISP_RDMA0_SEL BIT(0) #define MOUT_TO_DISP_RSZ0_SEL BIT(1) #define MOUT_TO_DISP_WDMA0_SEL BIT(2) #define MOUT_TO_DISP_UFBC_WDMA0_SEL BIT(3) #define MOUT_TO_DISP_OVL0_OVL0_2L_PQOUT_SEL BIT(4) #define MT6873_DISP_REG_CONFIG_DISP_OVL0_OVL0_2L_PQOUT_SEL_IN 0xF20 #define SEL_IN_PQ_FROM_DISP_OVL0_2L (0) #define SEL_IN_PQ_FROM_DISP_OVL0 (1) #define MT6873_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN 0xF24 #define SEL_IN_RSZ0_FROM_DISP_OVL0_2L (0) #define SEL_IN_RSZ0_FROM_DISP_OVL0 (1) #define MT6873_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN 0xF28 #define MOUT_RSZ0_TO_DISP_RDMA0_SEL BIT(0) #define MOUT_RSZ0_TO_DISP_WDMA0_SEL BIT(1) #define MOUT_RSZ0_TO_DISP_UFBC_WDMA0_SEL BIT(2) #define MOUT_RSZ0_TO_DISP_RDMA2_RSZ0_RSZ1_SOUT BIT(3) #define MOUT_RSZ0_TO_DISP_TOVL0_PQOUT_MDP_RDMA4_SEL BIT(4) #define MT6873_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN 0xF2C #define SEL_IN_FROM_DISP_OVL0 (0) #define SEL_IN_FROM_DISP_RSZ0 (1) #define SEL_IN_FROM_DISP_Y2R0 (2) #define SEL_IN_FROM_DISP_OVL0_2L (3) #define MT6873_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL 0xF30 #define SOUT_TO_DISP_DSI0 (0) #define SOUT_TO_DISP_COLOR0 (1) #define MT6873_DISP_REG_CONFIG_DISP_CCORR0_SOUT_SEL 0xF34 #define SOUT_TO_MDP_AAL4 (0) #define SOUT_TO_DISP_AAL0 (1) #define MT6873_DISP_REG_CONFIG_DISP_AAL0_SEL_IN 0xF38 #define SEL_IN_FROM_MDP_AAL4 (0) #define SEL_IN_FROM_DISP_CCORR0 (1) #define MT6873_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xF3C #define MOUT_DITHER0_TO_DISP_DSI0_SEL BIT(0) #define MOUT_DITHER0_TO_DISP_DSC_WRAP0 BIT(1) #define MOUT_DITHER0_TO_DISP_WDMA0_SEL BIT(2) #define MOUT_DITHER0_TO_DISP_UFBC_WDMA0_SEL BIT(3) #define MT6873_DISP_REG_CONFIG_DSI0_SEL_IN 0xF40 #define SEL_IN_FROM_DISP_RDMA0 (0) #define SEL_IN_FROM_DISP_DITHER0 (1) #define SEL_IN_FROM_DISP_DSC0 (2) #define MT6873_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN 0xF44 #define MT6873_DISP_REG_CONFIG_UFBC_WDMA0_SEL_IN 0xF48 #define SEL_IN_WDMA_FROM_DISP_DITHER0 (0) #define SEL_IN_WDMA_FROM_DISP_RSZ0 (1) #define SEL_IN_WDMA_FROM_DISP_OVL0_2L (2) #define SEL_IN_WDMA_FROM_DISP_OVL0 (3) #define SEL_IN_WDMA_FROM_DISP_OVL2_2L (4) #define MT6873_DISP_REG_CONFIG_DISP_OVL2_2L_OUT0_MOUT_EN 0xF4C #define MOUT_OVL2_2L_TO_DISP_RDMA4 BIT(0) #define MOUT_OVL2_2L_TO_DISP_WDMA0_SEL BIT(1) #define MOUT_OVL2_2L_TO_DISP_UFBC_WDMA0_SEL BIT(2) #define MT6873_DISP_REG_CONFIG_DISP_TOVL0_PQOUT_MDP_RDMA4_SEL_IN 0xF50 #define SEL_IN_PQ_FROM_MDP_RDMA4 (0) #define SEL_IN_PQ_FROM_DISP_OVL0_OVL0_2L_PQOUT_SEL (1) #define SEL_IN_PQ_FROM_DISP_RSZ0 (2) #define MT6873_DISP_REG_CONFIG_MDP_AAL4_SOUT_SEL 0xF54 #define SOUT_MDP_HDR4_TO_MDP_RSZ4 (0) #define SOUT_MDP_HDR4_TO_MDP_AAL4 (1) #define MT6873_DISP_REG_CONFIG_DISP_MDP_AAL4_MDP_HDR4_SEL_IN 0xF58 #define SEL_IN_PQ_FROM_MDP_HDR4 (0) #define SEL_IN_PQ_FROM_MDP_AAL4 (1) #define MT6873_DISP_REG_CONFIG_DISP_MDP_AAL4_SEL_IN 0xF5C #define SEL_IN_PQ_AAL_FROM_DISP_CCORR0 (0) #define SEL_IN_PQ_AAL_FROM_MDP_HDR4 (1) #define MT6873_DISP_REG_CONFIG_DISP_MDP_AAL4_SOUT_SEL 0xF60 #define SOUT_MDP_AAL4_TO_DISP_AAL0 (0) #define SOUT_MDP_AAL4_TO_MDP_RSZ4 (1) #define MT6873_DISP_REG_CONFIG_DISP_Y2R0_SOUT_SEL 0xF64 #define SOUT_TO_DISP_RDMA2_RSZ0_RSZ1_SOUT (0) #define SOUT_TO_DISP_RDMA0 (1) #define MT6873_DISP_MUTEX0_MOD0 0x30 #define MT6873_DISP_MUTEX0_SOF 0x2C #define MT6873_MUTEX_MOD_DISP_OVL0 BIT(0) #define MT6873_MUTEX_MOD_DISP_OVL0_2L BIT(1) #define MT6873_MUTEX_MOD_DISP_RDMA0 BIT(2) #define MT6873_MUTEX_MOD_DISP_RSZ0 BIT(3) #define MT6873_MUTEX_MOD_DISP_COLOR0 BIT(4) #define MT6873_MUTEX_MOD_DISP_CCORR0 BIT(5) #define MT6873_MUTEX_MOD_DISP_AAL0 BIT(6) #define MT6873_MUTEX_MOD_DISP_GAMMA0 BIT(7) #define MT6873_MUTEX_MOD_DISP_POSTMASK0 BIT(8) #define MT6873_MUTEX_MOD_DISP_DITHER0 BIT(9) #define MT6873_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(10) #define MT6873_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 BIT(11) #define MT6873_MUTEX_MOD_DISP_DSI0 BIT(12) #define MT6873_MUTEX_MOD_DISP_WDMA0 BIT(13) #define MT6873_MUTEX_MOD_DISP_UFBC_WDMA0 BIT(14) #define MT6873_MUTEX_MOD_DISP_PWM0 BIT(15) #define MT6873_MUTEX_MOD_DISP_OVL2_2L BIT(16) #define MT6873_MUTEX_MOD_DISP_RDMA4 BIT(17) #define MT6873_MUTEX_MOD_DISP_DPI BIT(18) #define MT6873_MUTEX_MOD_DISP_MDP_RDMA4 BIT(19) #define MT6873_MUTEX_MOD_DISP_MDP_HDR4 BIT(20) #define MT6873_MUTEX_MOD_DISP_MDP_RSZ4 BIT(21) #define MT6873_MUTEX_MOD_DISP_MDP_AAL4 BIT(22) #define MT6873_MUTEX_MOD_DISP_MDP_TDSHP4 BIT(23) #define MT6873_MUTEX_MOD_DISP_MDP_COLOR4 BIT(24) #define MT6873_MUTEX_MOD_DISP_Y2R0 BIT(25) #define MT6873_MUTEX_SOF_SINGLE_MODE 0 #define MT6873_MUTEX_SOF_DSI0 1 #define MT6873_MUTEX_SOF_DPI0 2 #define MT6873_MUTEX_EOF_DSI0 (MT6873_MUTEX_SOF_DSI0 << 6) #define MT6873_MUTEX_EOF_DPI0 (MT6873_MUTEX_SOF_DPI0 << 6) #define DISP_REG_CONFIG_MMSYS_CG_CON0_MT6873 0x100 #define DISP_REG_CONFIG_MMSYS_CG_CON1_MT6873 0x110 #define MT6873_DISP_REG_CONFIG_DL_VALID_0 0xe9c #define MT6873_DISP_REG_CONFIG_DL_VALID_1 0xea0 #define MT6873_DISP_REG_CONFIG_DL_VALID_2 0xea4 #define MT6873_DISP_REG_CONFIG_DL_VALID_3 0xe80 #define MT6873_DISP_REG_CONFIG_DL_VALID_4 0xe84 #define MT6873_DISP_REG_CONFIG_DL_VALID_5 0xe88 #define MT6873_DISP_REG_CONFIG_DL_READY_0 0xea8 #define MT6873_DISP_REG_CONFIG_DL_READY_1 0xeac #define MT6873_DISP_REG_CONFIG_DL_READY_2 0xeb0 #define MT6873_DISP_REG_CONFIG_DL_READY_3 0xe70 #define MT6873_DISP_REG_CONFIG_DL_READY_4 0xe74 #define MT6873_DISP_REG_CONFIG_DL_READY_5 0xe78 #define MT6873_DISP_REG_CONFIG_SMI_LARB0_GREQ 0x8dc #define MT6873_DISP_REG_CONFIG_SMI_LARB1_GREQ 0x8e0 struct mtk_disp_mutex { int id; bool claimed; }; /*For MT6853*/ #define MT6853_DISP_OVL0_MOUT_EN 0xf04 #define MT6853_MMSYS_OVL_CON 0xF04 #if 0 same with 6873 #define DISP_OVL0_GO_BLEND BIT(0) #define DISP_OVL0_GO_BG BIT(1) #define DISP_OVL0_2L_GO_BLEND BIT(2) #define DISP_OVL0_2L_GO_BG BIT(3) #endif #define MT6853_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL 0xF08 #define RSZ0_SOUT_TO_DISP_OVL0_2L (0) #define RSZ0_SOUT_TO_DISP_OVL0 (1) #define MT6853_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL 0xF0C #define SOUT_TO_DISP_DSI0_SEL (0) #define RDMA0_SOUT_TO_DISP_COLOR0 (1) #define MT6853_DISP_REG_CONFIG_DISP_SPR0_MOUT_EN 0xF10 #define SPR0_MOUT_TO_DISP_DSI0_SEL BIT(0) #define SPR0_MOUT_TO_DISP_WDMA0_SEL BIT(1) #define SPR0_MOUT_TO_DISP_DSC0_SEL BIT(2) #define MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN 0xF14 #define OVL0_2L_MOUT_TO_DISP_RDMA0_SEL BIT(0) #define OVL0_2L_MOUT_TO_DISP_RSZ0_SEL BIT(1) #define OVL0_2L_MOUT_TO_DISP_WDMA0_SEL BIT(2) #define MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN 0xF18 #define OVL0_MOUT_TO_DISP_RDMA0_SEL BIT(0) #define OVL0_MOUT_TO_DISP_RSZ0_SEL BIT(1) #define OVL0_MOUT_TO_DISP_WDMA0_SEL BIT(2) #define MT6853_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN 0xF1C #define RSZ0_MOUT_TO_DISP_RDMA0_SEL BIT(0) #define RSZ0_MOUT_TO_DISP_WDMA0_SEL BIT(1) #define RSZ0_MOUT_TO_DISP_RDMA2_RSZ0_RSZ1_SOUT BIT(2) #define MT6853_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xF20 #define DITHER0_MOUT_TO_DISP_DISP_BYPASS_SPR0_SEL BIT(0) #define DITHER0_MOUT_TO_DISP_DISP_CM0 BIT(1) #define DITHER0_MOUT_TO_DISP_DISP_WDMA0 BIT(2) #define MT6853_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN 0xF24 #define RSZ0_FROM_DISP_OVL0_2L (0) #define RSZ0_FROM_DISP_OVL0 (1) #define MT6853_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN 0xF28 #define SEL_IN_RDMA0_FROM_DISP_OVL0 0 #define SEL_IN_RDMA0_FROM_DISP_OVL0_2L 2 #define MT6853_DISP_REG_CONFIG_DISP_BYPASS_SPR0_SEL_IN 0xF2C #define SEL_IN_FROM_DISP_DITHER0_MOUT (0) #define SEL_IN_FROM_DISP_SPR0 (1) #define MT6853_DISP_REG_CONFIG_DSI0_SEL_IN 0xF30 #define SEL_IN_FROM_DISP_RDMA0_RSZ0_SOUT (0) #define SEL_IN_FROM_DISP_SPR0_MOUT (1) #define SEL_IN_FROM_DISP_DSC_WRAP0 (2) #define MT6853_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN 0xF34 #define WDMA0_SEL_IN_FROM_DISP_SPR0_MOUT (0) #define SEL_IN_FROM_DISP_RSZ0 (1) #define WDMA0_SEL_IN_FROM_DISP_OVL0_2L (2) #define WDMA0_SEL_IN_FROM_DISP_OVL0 (3) #define MT6877_WDMA0_SEL_IN_FROM_DISP_OVL1_2L (5) #define MT6853_WDMA0_SEL_IN_FROM_DISP_DITHER0_MOUT (4) #define MT6853_DISP_MUTEX0_MOD0 0x30 #define MT6853_DISP_MUTEX0_SOF 0x2C #define MT6853_MUTEX_MOD_DISP_OVL0 BIT(0) #define MT6853_MUTEX_MOD_DISP_OVL0_2L BIT(1) #define MT6853_MUTEX_MOD_DISP_RDMA0 BIT(2) #define MT6853_MUTEX_MOD_DISP_RSZ0 BIT(3) #define MT6853_MUTEX_MOD_DISP_COLOR0 BIT(4) #define MT6853_MUTEX_MOD_DISP_CCORR0 BIT(5) #define MT6853_MUTEX_MOD_DISP_CCORR1 BIT(6) #define MT6853_MUTEX_MOD_DISP_AAL0 BIT(7) #define MT6853_MUTEX_MOD_DISP_GAMMA0 BIT(8) #define MT6853_MUTEX_MOD_DISP_POSTMASK0 BIT(9) #define MT6853_MUTEX_MOD_DISP_DITHER0 BIT(10) #define MT6853_MUTEX_MOD_DISP_CM0 BIT(11) #define MT6853_MUTEX_MOD_DISP_SPR0 BIT(12) #define MT6853_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(13) #define MT6853_MUTEX_MOD_DISP_DSI0 BIT(14) #define MT6853_MUTEX_MOD_DISP_WDMA0 BIT(15) #define MT6853_MUTEX_MOD_DISP_PWM0 BIT(16) #define MT6853_MUTEX_SOF_SINGLE_MODE 0 #define MT6853_MUTEX_SOF_DSI0 1 #define MT6853_MUTEX_EOF_DSI0 (MT6853_MUTEX_SOF_DSI0 << 6) #define MT6877_DISP_MUTEX0_MOD0 0x30 #define MT6877_DISP_MUTEX0_SOF 0x2C #define MT6877_MUTEX_MOD_DISP_OVL0 BIT(0) #define MT6877_MUTEX_MOD_DISP_OVL0_2L BIT(1) #define MT6877_MUTEX_MOD_DISP_RDMA0 BIT(2) #define MT6877_MUTEX_MOD_DISP_RSZ0 BIT(3) #define MT6877_MUTEX_MOD_DISP_COLOR0 BIT(4) #define MT6877_MUTEX_MOD_DISP_CCORR0 BIT(5) #define MT6877_MUTEX_MOD_DISP_CCORR1 BIT(6) #define MT6877_MUTEX_MOD_DISP_AAL0 BIT(7) #define MT6877_MUTEX_MOD_DISP_GAMMA0 BIT(8) #define MT6877_MUTEX_MOD_DISP_POSTMASK0 BIT(9) #define MT6877_MUTEX_MOD_DISP_DITHER0 BIT(10) #define MT6877_MUTEX_MOD_DISP_CM0 BIT(11) #define MT6877_MUTEX_MOD_DISP_SPR0 BIT(12) #define MT6877_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(13) #define MT6877_MUTEX_MOD_DISP_DSI0 BIT(14) #define MT6877_MUTEX_MOD_DISP_WDMA0 BIT(15) #define MT6877_MUTEX_MOD_DISP_PWM0 BIT(16) #define MT6877_MUTEX_MOD_DISP_OVL1_2L BIT(17) #define MT6877_MUTEX_MOD_DISP_UFBC_WDMA0 BIT(18) #define MT6877_MUTEX_SOF_SINGLE_MODE 0 #define MT6877_MUTEX_SOF_DSI0 1 #define MT6877_MUTEX_EOF_DSI0 (MT6853_MUTEX_SOF_DSI0 << 6) /*For MT6833*/ #define MT6833_DISP_OVL0_MOUT_EN 0xf04 #define MT6833_MMSYS_OVL_CON 0xF04 #define MT6833_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL 0xF08 #define MT6833_RSZ0_SOUT_TO_DISP_OVL0_2L (0) #define MT6833_RSZ0_SOUT_TO_DISP_OVL0 (1) #define MT6833_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL 0xF0C #define MT6833_RDMA0_SOUT_TO_DISP_DSI0_SEL (0) #define MT6833_RDMA0_SOUT_TO_DISP_COLOR0 (1) #define MT6833_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN 0xF14 #define MT6833_OVL0_2L_MOUT_TO_DISP_RDMA0_SEL BIT(0) #define MT6833_OVL0_2L_MOUT_TO_DISP_RSZ0_SEL BIT(1) #define MT6833_OVL0_2L_MOUT_TO_DISP_WDMA0_SEL BIT(2) #define MT6833_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN 0xF18 #define MT6833_OVL0_MOUT_TO_DISP_RDMA0_SEL BIT(0) #define MT6833_OVL0_MOUT_TO_DISP_RSZ0_SEL BIT(1) #define MT6833_OVL0_MOUT_TO_DISP_WDMA0_SEL BIT(2) #define MT6833_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN 0xF1C #define MT6833_RSZ0_MOUT_TO_DISP_RDMA0_SEL BIT(0) #define MT6833_RSZ0_MOUT_TO_DISP_WDMA0_SEL BIT(1) #define MT6833_RSZ0_MOUT_TO_DISP_RDMA2_RSZ0_RSZ1_SOUT BIT(2) #define MT6833_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xF20 #define MT6833_DITHER0_MOUT_TO_DISP_DSI0_SEL BIT(0) #define MT6833_DITHER0_MOUT_TO_DISP_DISP_WDMA0 BIT(1) #define MT6833_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN 0xF24 #define MT6833_RSZ0_SEL_IN_FROM_DISP_OVL0_2L (0) #define MT6833_RSZ0_SEL_IN_FROM_DISP_OVL0 (1) #define MT6833_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN 0xF28 #define MT6833_RDMA0_SEL_IN_FROM_DISP_OVL0 0 #define MT6833_RDMA0_SEL_IN_FROM_DISP_OVL0_2L 2 #define MT6833_DISP_REG_CONFIG_DSI0_SEL_IN 0xF30 #define MT6833_DSI0_SEL_IN_FROM_DISP_RDMA0_RSZ0_SOUT (0) #define MT6833_DSI0_SEL_IN_FROM_DISP_DITHER0 (1) #define MT6833_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN 0xF34 #define MT6833_WDMA0_SEL_IN_FROM_DISP_DITHER0 (0) #define MT6833_WDMA0_SEL_IN_FROM_DISP_RSZ0 (1) #define MT6833_WDMA0_SEL_IN_FROM_DISP_OVL0_2L (2) #define MT6833_WDMA0_SEL_IN_FROM_DISP_OVL0 (3) #define MT6833_DISP_MUTEX0_MOD0 0x30 #define MT6833_DISP_MUTEX0_SOF 0x2C #define MT6833_MUTEX_MOD_DISP_OVL0 BIT(0) #define MT6833_MUTEX_MOD_DISP_OVL0_2L BIT(1) #define MT6833_MUTEX_MOD_DISP_RDMA0 BIT(2) #define MT6833_MUTEX_MOD_DISP_RSZ0 BIT(3) #define MT6833_MUTEX_MOD_DISP_COLOR0 BIT(4) #define MT6833_MUTEX_MOD_DISP_CCORR0 BIT(5) #define MT6833_MUTEX_MOD_DISP_AAL0 BIT(7) #define MT6833_MUTEX_MOD_DISP_GAMMA0 BIT(8) #define MT6833_MUTEX_MOD_DISP_POSTMASK0 BIT(9) #define MT6833_MUTEX_MOD_DISP_DITHER0 BIT(10) #define MT6833_MUTEX_MOD_DISP_DSI0 BIT(14) #define MT6833_MUTEX_MOD_DISP_WDMA0 BIT(15) #define MT6833_MUTEX_MOD_DISP_PWM0 BIT(16) #define MT6833_MUTEX_SOF_SINGLE_MODE 0 #define MT6833_MUTEX_SOF_DSI0 1 #define MT6833_MUTEX_EOF_DSI0 (MT6833_MUTEX_SOF_DSI0 << 6) /*For MT6781*/ #define MT6781_DISP_OVL0_MOUT_EN 0xf04 #define MT6781_MMSYS_OVL_CON 0xF04 #define MT6781_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL 0xF08 #define MT6781_RSZ0_SOUT_TO_DISP_OVL0_2L (0) #define MT6781_RSZ0_SOUT_TO_DISP_OVL0 (1) #define MT6781_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL 0xF0C #define MT6781_SOUT_TO_DISP_DSI0_SEL (0) #define MT6781_RDMA0_SOUT_TO_DISP_COLOR0 (1) #define MT6781_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN 0xF14 #define MT6781_OVL0_2L_MOUT_TO_DISP_RDMA0_SEL BIT(0) #define MT6781_OVL0_2L_MOUT_TO_DISP_RSZ0_SEL BIT(1) #define MT6781_OVL0_2L_MOUT_TO_DISP_WDMA0_SEL BIT(2) #define MT6781_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN 0xF18 #define MT6781_OVL0_MOUT_TO_DISP_RDMA0_SEL BIT(0) #define MT6781_OVL0_MOUT_TO_DISP_RSZ0_SEL BIT(1) #define MT6781_OVL0_MOUT_TO_DISP_WDMA0_SEL BIT(2) #define MT6781_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN 0xF1C #define MT6781_RSZ0_MOUT_TO_DISP_RDMA0_SEL BIT(0) #define MT6781_RSZ0_MOUT_TO_DISP_WDMA0_SEL BIT(1) #define MT6781_RSZ0_MOUT_TO_DISP_RDMA2_RSZ0_RSZ1_SOUT BIT(2) #define MT6781_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN 0xF20 #define MT6781_DITHER0_MOUT_TO_DISP_DSI0_SEL BIT(0) #define MT6781_DITHER0_MOUT_TO_DISP_DISP_WDMA0 BIT(1) #define MT6781_DITHER0_MOUT_TO_DISP_DISP_DSC_WRAP0 BIT(2) #define MT6781_DISP_REG_CONFIG_DISP_DSC_WRAP0_MOUT_EN 0xF38 #define MT6781_DISP_DSC_WRAP0_TO_DISP_WDMA0_SEL BIT(0) #define MT6781_DISP_DSC_WRAP0_TO_DISP_DSI0_SEL BIT(1) #define MT6781_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN 0xF24 #define MT6781_RSZ0_FROM_DISP_OVL0_2L (0) #define MT6781_RSZ0_FROM_DISP_OVL0 (1) #define MT6781_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN 0xF28 #define MT6781_SEL_IN_RDMA0_FROM_DISP_OVL0 0 #define MT6781_SEL_IN_RDMA0_FROM_DISP_RSZ0 1 #define MT6781_SEL_IN_RDMA0_FROM_DISP_OVL0_2L 2 #if 0 #define MT6781_DISP_REG_CONFIG_DISP_BYPASS_SPR0_SEL_IN 0xF2C #define SEL_IN_FROM_DISP_DITHER0_MOUT (0) #define SEL_IN_FROM_DISP_SPR0 (1) #endif #define MT6781_DISP_REG_CONFIG_DSI0_SEL_IN 0xF30 #define MT6781_SEL_IN_FROM_DISP_RDMA0_RSZ0_SOUT (0) #define MT6781_SEL_IN_FROM_DISP_DITHERR0 (1) #define MT6781_SEL_IN_FROM_DISP_DSC_WRAP0 (2) #define MT6781_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN 0xF34 #define MT6781_WDMA0_SEL_IN_FROM_DISP_DITHER0_MOUT (0) #define MT6781_SEL_IN_FROM_DISP_RSZ0 (1) #define MT6781_WDMA0_SEL_IN_FROM_DISP_OVL0_2L (2) #define MT6781_WDMA0_SEL_IN_FROM_DISP_OVL0 (3) #define MT6781_WDMA0_SEL_IN_FROM_DISP_DSC_MOUT (4) #define MT6781_DISP_MUTEX0_MOD0 0x30 #define MT6781_DISP_MUTEX0_SOF 0x2C #define MT6781_MUTEX_MOD_DISP_OVL0 BIT(0) #define MT6781_MUTEX_MOD_DISP_OVL0_2L BIT(1) #define MT6781_MUTEX_MOD_DISP_RDMA0 BIT(2) #define MT6781_MUTEX_MOD_DISP_RSZ0 BIT(3) #define MT6781_MUTEX_MOD_DISP_COLOR0 BIT(4) #define MT6781_MUTEX_MOD_DISP_CCORR0 BIT(5) #define MT6781_MUTEX_MOD_DISP_AAL0 BIT(7) #define MT6781_MUTEX_MOD_DISP_GAMMA0 BIT(8) #define MT6781_MUTEX_MOD_DISP_POSTMASK0 BIT(9) #define MT6781_MUTEX_MOD_DISP_DITHER0 BIT(10) #define MT6781_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 BIT(13) #define MT6781_MUTEX_MOD_DISP_DSI0 BIT(14) #define MT6781_MUTEX_MOD_DISP_WDMA0 BIT(15) #define MT6781_MUTEX_MOD_DISP_PWM0 BIT(16) #define MT6781_MUTEX_SOF_SINGLE_MODE 0 #define MT6781_MUTEX_SOF_DSI0 1 #define MT6781_MUTEX_EOF_DSI0 (MT6781_MUTEX_SOF_DSI0 << 6) enum mtk_ddp_mutex_sof_id { DDP_MUTEX_SOF_SINGLE_MODE, DDP_MUTEX_SOF_DSI0, DDP_MUTEX_SOF_DSI1, DDP_MUTEX_SOF_DPI0, DDP_MUTEX_SOF_DPI1, DDP_MUTEX_SOF_DSI2, DDP_MUTEX_SOF_DSI3, DDP_MUTEX_SOF_MAX, }; struct mtk_disp_ddp_data { const unsigned int *mutex_mod; const unsigned int *mutex_sof; unsigned int mutex_mod_reg; unsigned int mutex_sof_reg; }; struct mtk_ddp { struct device *dev; struct clk *clk; void __iomem *regs; resource_size_t regs_pa; struct mtk_disp_mutex mutex[10]; const struct mtk_disp_ddp_data *data; struct cmdq_base *cmdq_base; }; struct mtk_mmsys_reg_data { unsigned int ovl0_mout_en; unsigned int rdma0_sout_sel_in; unsigned int rdma0_sout_color0; unsigned int rdma1_sout_sel_in; unsigned int rdma1_sout_dpi0; unsigned int rdma1_sout_dsi0; unsigned int dpi0_sel_in; unsigned int dpi0_sel_in_rdma1; unsigned int *path_sel; unsigned int path_sel_size; }; static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_BLS] = MT2701_MUTEX_MOD_DISP_BLS, [DDP_COMPONENT_COLOR0] = MT2701_MUTEX_MOD_DISP_COLOR, [DDP_COMPONENT_OVL0] = MT2701_MUTEX_MOD_DISP_OVL, [DDP_COMPONENT_RDMA0] = MT2701_MUTEX_MOD_DISP_RDMA0, [DDP_COMPONENT_RDMA1] = MT2701_MUTEX_MOD_DISP_RDMA1, [DDP_COMPONENT_WDMA0] = MT2701_MUTEX_MOD_DISP_WDMA, }; static const unsigned int mt2712_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT2712_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_AAL1] = MT2712_MUTEX_MOD2_DISP_AAL1, [DDP_COMPONENT_COLOR0] = MT2712_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_COLOR1] = MT2712_MUTEX_MOD_DISP_COLOR1, [DDP_COMPONENT_OD] = MT2712_MUTEX_MOD_DISP_OD, [DDP_COMPONENT_OD1] = MT2712_MUTEX_MOD2_DISP_OD1, [DDP_COMPONENT_OVL0] = MT2712_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL1] = MT2712_MUTEX_MOD_DISP_OVL1, [DDP_COMPONENT_PWM0] = MT2712_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_PWM1] = MT2712_MUTEX_MOD_DISP_PWM1, [DDP_COMPONENT_RDMA0] = MT2712_MUTEX_MOD_DISP_RDMA0, [DDP_COMPONENT_RDMA1] = MT2712_MUTEX_MOD_DISP_RDMA1, [DDP_COMPONENT_RDMA2] = MT2712_MUTEX_MOD_DISP_RDMA2, [DDP_COMPONENT_UFOE] = MT2712_MUTEX_MOD_DISP_UFOE, [DDP_COMPONENT_WDMA0] = MT2712_MUTEX_MOD_DISP_WDMA0, [DDP_COMPONENT_WDMA1] = MT2712_MUTEX_MOD_DISP_WDMA1, }; static const unsigned int mt6779_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT6779_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT6779_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_CCORR0] = MT6779_MUTEX_MOD_DISP_CCORR, [DDP_COMPONENT_DITHER0] = MT6779_MUTEX_MOD_DISP_DITHER, [DDP_COMPONENT_DSI0] = MT6779_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_GAMMA0] = MT6779_MUTEX_MOD_DISP_GAMMA, [DDP_COMPONENT_OVL0] = MT6779_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL0_2L] = MT6779_MUTEX_MOD_DISP_OVL0_2L, [DDP_COMPONENT_OVL1_2L] = MT6779_MUTEX_MOD_DISP_OVL1_2L, [DDP_COMPONENT_PWM0] = MT6779_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_RDMA0] = MT6779_MUTEX_MOD_DISP_RDMA0, [DDP_COMPONENT_RDMA1] = MT6779_MUTEX_MOD_DISP_RDMA1, [DDP_COMPONENT_WDMA0] = MT6779_MUTEX_MOD_DISP_WDMA0, [DDP_COMPONENT_RSZ0] = MT6779_MUTEX_MOD_DISP_RSZ, [DDP_COMPONENT_POSTMASK0] = MT6779_MUTEX_MOD_DISP_POSTMASK, }; static const unsigned int mt6885_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT6885_MUTEX_MOD0_DISP_AAL0, [DDP_COMPONENT_AAL1] = MT6885_MUTEX_MOD0_DISP_AAL1, [DDP_COMPONENT_COLOR0] = MT6885_MUTEX_MOD0_DISP_COLOR0, [DDP_COMPONENT_COLOR1] = MT6885_MUTEX_MOD0_DISP_COLOR1, [DDP_COMPONENT_CCORR0] = MT6885_MUTEX_MOD0_DISP_CCORR0, [DDP_COMPONENT_CCORR1] = MT6885_MUTEX_MOD0_DISP_CCORR1, [DDP_COMPONENT_DITHER0] = MT6885_MUTEX_MOD0_DISP_DITHER0, [DDP_COMPONENT_DITHER1] = MT6885_MUTEX_MOD0_DISP_DITHER1, [DDP_COMPONENT_DSI0] = MT6885_MUTEX_MOD0_DISP_DSI0, [DDP_COMPONENT_DSI1] = MT6885_MUTEX_MOD0_DISP_DSI1, [DDP_COMPONENT_GAMMA0] = MT6885_MUTEX_MOD0_DISP_GAMMA0, [DDP_COMPONENT_GAMMA1] = MT6885_MUTEX_MOD0_DISP_GAMMA1, [DDP_COMPONENT_OVL0] = MT6885_MUTEX_MOD0_DISP_OVL0, [DDP_COMPONENT_OVL1] = MT6885_MUTEX_MOD0_DISP_OVL1, [DDP_COMPONENT_OVL0_2L] = MT6885_MUTEX_MOD0_DISP_OVL0_2L, [DDP_COMPONENT_OVL1_2L] = MT6885_MUTEX_MOD0_DISP_OVL1_2L, [DDP_COMPONENT_OVL2_2L] = MT6885_MUTEX_MOD0_DISP_OVL2, [DDP_COMPONENT_OVL3_2L] = MT6885_MUTEX_MOD0_DISP_OVL3, [DDP_COMPONENT_PWM0] = MT6885_MUTEX_MOD0_DISP_PWM0, [DDP_COMPONENT_RDMA0] = MT6885_MUTEX_MOD0_DISP_RDMA0, [DDP_COMPONENT_RDMA1] = MT6885_MUTEX_MOD0_DISP_RDMA1, [DDP_COMPONENT_RDMA4] = MT6885_MUTEX_MOD1_DISP_RDMA4, [DDP_COMPONENT_RDMA5] = MT6885_MUTEX_MOD1_DISP_RDMA5, [DDP_COMPONENT_WDMA0] = MT6885_MUTEX_MOD0_DISP_WDMA0, [DDP_COMPONENT_WDMA1] = MT6885_MUTEX_MOD0_DISP_WDMA1, [DDP_COMPONENT_RSZ0] = MT6885_MUTEX_MOD0_DISP_RSZ0, [DDP_COMPONENT_RSZ1] = MT6885_MUTEX_MOD0_DISP_RSZ1, [DDP_COMPONENT_POSTMASK0] = MT6885_MUTEX_MOD0_DISP_POSTMASK0, [DDP_COMPONENT_POSTMASK1] = MT6885_MUTEX_MOD0_DISP_POSTMASK1, [DDP_COMPONENT_DSC0] = MT6885_MUTEX_MOD0_DISP_DSC0, [DDP_COMPONENT_DP_INTF0] = MT6885_MUTEX_MOD0_DISP_DP, [DDP_COMPONENT_MERGE1] = MT6885_MUTEX_MOD0_DISP_MERGE1, [DDP_COMPONENT_DMDP_AAL0] = MT6885_MUTEX_MOD1_MDP_AAL4, [DDP_COMPONENT_DMDP_AAL1] = MT6885_MUTEX_MOD1_MDP_AAL5, }; static const unsigned int mt8173_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_AAL0] = MT8173_MUTEX_MOD_DISP_AAL, [DDP_COMPONENT_COLOR0] = MT8173_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_COLOR1] = MT8173_MUTEX_MOD_DISP_COLOR1, [DDP_COMPONENT_GAMMA0] = MT8173_MUTEX_MOD_DISP_GAMMA, [DDP_COMPONENT_OD] = MT8173_MUTEX_MOD_DISP_OD, [DDP_COMPONENT_OVL0] = MT8173_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL1] = MT8173_MUTEX_MOD_DISP_OVL1, [DDP_COMPONENT_PWM0] = MT8173_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_PWM1] = MT8173_MUTEX_MOD_DISP_PWM1, [DDP_COMPONENT_RDMA0] = MT8173_MUTEX_MOD_DISP_RDMA0, [DDP_COMPONENT_RDMA1] = MT8173_MUTEX_MOD_DISP_RDMA1, [DDP_COMPONENT_RDMA2] = MT8173_MUTEX_MOD_DISP_RDMA2, [DDP_COMPONENT_UFOE] = MT8173_MUTEX_MOD_DISP_UFOE, [DDP_COMPONENT_WDMA0] = MT8173_MUTEX_MOD_DISP_WDMA0, [DDP_COMPONENT_WDMA1] = MT8173_MUTEX_MOD_DISP_WDMA1, }; static const unsigned int mt6873_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL0] = MT6873_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL0_2L] = MT6873_MUTEX_MOD_DISP_OVL0_2L, [DDP_COMPONENT_RDMA0] = MT6873_MUTEX_MOD_DISP_RDMA0, [DDP_COMPONENT_RSZ0] = MT6873_MUTEX_MOD_DISP_RSZ0, [DDP_COMPONENT_COLOR0] = MT6873_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_CCORR0] = MT6873_MUTEX_MOD_DISP_CCORR0, [DDP_COMPONENT_AAL0] = MT6873_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_GAMMA0] = MT6873_MUTEX_MOD_DISP_GAMMA0, [DDP_COMPONENT_POSTMASK0] = MT6873_MUTEX_MOD_DISP_POSTMASK0, [DDP_COMPONENT_DITHER0] = MT6873_MUTEX_MOD_DISP_DITHER0, [DDP_COMPONENT_DSC0] = MT6873_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, [DDP_COMPONENT_DSI0] = MT6873_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_WDMA0] = MT6873_MUTEX_MOD_DISP_WDMA0, [DDP_COMPONENT_UFBC_WDMA0] = MT6873_MUTEX_MOD_DISP_UFBC_WDMA0, [DDP_COMPONENT_PWM0] = MT6873_MUTEX_MOD_DISP_PWM0, [DDP_COMPONENT_OVL2_2L] = MT6873_MUTEX_MOD_DISP_OVL2_2L, [DDP_COMPONENT_RDMA4] = MT6873_MUTEX_MOD_DISP_RDMA4, [DDP_COMPONENT_DPI0] = MT6873_MUTEX_MOD_DISP_DPI, [DDP_COMPONENT_DMDP_AAL0] = MT6873_MUTEX_MOD_DISP_MDP_AAL4, }; static const unsigned int mt6853_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL0] = MT6853_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL0_2L] = MT6853_MUTEX_MOD_DISP_OVL0_2L, [DDP_COMPONENT_RDMA0] = MT6853_MUTEX_MOD_DISP_RDMA0, [DDP_COMPONENT_RSZ0] = MT6853_MUTEX_MOD_DISP_RSZ0, [DDP_COMPONENT_COLOR0] = MT6853_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_CCORR0] = MT6853_MUTEX_MOD_DISP_CCORR0, [DDP_COMPONENT_CCORR1] = MT6853_MUTEX_MOD_DISP_CCORR1, [DDP_COMPONENT_AAL0] = MT6853_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_GAMMA0] = MT6853_MUTEX_MOD_DISP_GAMMA0, [DDP_COMPONENT_POSTMASK0] = MT6853_MUTEX_MOD_DISP_POSTMASK0, [DDP_COMPONENT_DITHER0] = MT6853_MUTEX_MOD_DISP_DITHER0, [DDP_COMPONENT_CM0] = MT6853_MUTEX_MOD_DISP_CM0, [DDP_COMPONENT_SPR0] = MT6853_MUTEX_MOD_DISP_SPR0, [DDP_COMPONENT_DSC0] = MT6853_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, [DDP_COMPONENT_DSI0] = MT6853_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_WDMA0] = MT6853_MUTEX_MOD_DISP_WDMA0, [DDP_COMPONENT_PWM0] = MT6853_MUTEX_MOD_DISP_PWM0, }; static const unsigned int mt6877_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL0] = MT6877_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL0_2L] = MT6877_MUTEX_MOD_DISP_OVL0_2L, [DDP_COMPONENT_OVL1_2L] = MT6877_MUTEX_MOD_DISP_OVL1_2L, [DDP_COMPONENT_RDMA0] = MT6877_MUTEX_MOD_DISP_RDMA0, [DDP_COMPONENT_RSZ0] = MT6877_MUTEX_MOD_DISP_RSZ0, [DDP_COMPONENT_COLOR0] = MT6877_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_CCORR0] = MT6877_MUTEX_MOD_DISP_CCORR0, [DDP_COMPONENT_CCORR1] = MT6877_MUTEX_MOD_DISP_CCORR1, [DDP_COMPONENT_AAL0] = MT6877_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_GAMMA0] = MT6877_MUTEX_MOD_DISP_GAMMA0, [DDP_COMPONENT_POSTMASK0] = MT6877_MUTEX_MOD_DISP_POSTMASK0, [DDP_COMPONENT_DITHER0] = MT6877_MUTEX_MOD_DISP_DITHER0, [DDP_COMPONENT_CM0] = MT6877_MUTEX_MOD_DISP_CM0, [DDP_COMPONENT_SPR0] = MT6877_MUTEX_MOD_DISP_SPR0, [DDP_COMPONENT_DSC0] = MT6877_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, [DDP_COMPONENT_DSI0] = MT6877_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_WDMA0] = MT6877_MUTEX_MOD_DISP_WDMA0, [DDP_COMPONENT_PWM0] = MT6877_MUTEX_MOD_DISP_PWM0, }; static const unsigned int mt6833_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL0] = MT6833_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL0_2L] = MT6833_MUTEX_MOD_DISP_OVL0_2L, [DDP_COMPONENT_RDMA0] = MT6833_MUTEX_MOD_DISP_RDMA0, [DDP_COMPONENT_RSZ0] = MT6833_MUTEX_MOD_DISP_RSZ0, [DDP_COMPONENT_COLOR0] = MT6833_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_CCORR0] = MT6833_MUTEX_MOD_DISP_CCORR0, [DDP_COMPONENT_AAL0] = MT6833_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_GAMMA0] = MT6833_MUTEX_MOD_DISP_GAMMA0, [DDP_COMPONENT_POSTMASK0] = MT6833_MUTEX_MOD_DISP_POSTMASK0, [DDP_COMPONENT_DITHER0] = MT6833_MUTEX_MOD_DISP_DITHER0, [DDP_COMPONENT_DSI0] = MT6833_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_WDMA0] = MT6833_MUTEX_MOD_DISP_WDMA0, [DDP_COMPONENT_PWM0] = MT6833_MUTEX_MOD_DISP_PWM0, }; static const unsigned int mt6781_mutex_mod[DDP_COMPONENT_ID_MAX] = { [DDP_COMPONENT_OVL0] = MT6781_MUTEX_MOD_DISP_OVL0, [DDP_COMPONENT_OVL0_2L] = MT6781_MUTEX_MOD_DISP_OVL0_2L, [DDP_COMPONENT_RDMA0] = MT6781_MUTEX_MOD_DISP_RDMA0, [DDP_COMPONENT_RSZ0] = MT6781_MUTEX_MOD_DISP_RSZ0, [DDP_COMPONENT_COLOR0] = MT6781_MUTEX_MOD_DISP_COLOR0, [DDP_COMPONENT_CCORR0] = MT6781_MUTEX_MOD_DISP_CCORR0, [DDP_COMPONENT_AAL0] = MT6781_MUTEX_MOD_DISP_AAL0, [DDP_COMPONENT_GAMMA0] = MT6781_MUTEX_MOD_DISP_GAMMA0, [DDP_COMPONENT_POSTMASK0] = MT6781_MUTEX_MOD_DISP_POSTMASK0, [DDP_COMPONENT_DITHER0] = MT6781_MUTEX_MOD_DISP_DITHER0, [DDP_COMPONENT_DSC0] = MT6781_MUTEX_MOD_DISP_DSC_WRAP0_CORE0, [DDP_COMPONENT_DSI0] = MT6781_MUTEX_MOD_DISP_DSI0, [DDP_COMPONENT_WDMA0] = MT6781_MUTEX_MOD_DISP_WDMA0, [DDP_COMPONENT_PWM0] = MT6781_MUTEX_MOD_DISP_PWM0, }; /* TODO-check : mutex sof */ static const unsigned int mt2701_mutex_sof[DDP_MUTEX_SOF_MAX] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, [DDP_MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, [DDP_MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, }; static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, [DDP_MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, [DDP_MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, }; static const unsigned int mt8173_mutex_sof[DDP_MUTEX_SOF_MAX] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0, [DDP_MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1, [DDP_MUTEX_SOF_DPI0] = MUTEX_SOF_DPI0, }; static const unsigned int mt6779_mutex_sof[DDP_MUTEX_SOF_MAX] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MT6779_MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MT6779_MUTEX_SOF_DSI0 | MT6779_MUTEX_EOF_DSI0, [DDP_MUTEX_SOF_DPI0] = MT6779_MUTEX_SOF_DPI0 | MT6779_MUTEX_EOF_DPI0, }; static const unsigned int mt6885_mutex_sof[DDP_MUTEX_SOF_MAX] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MT6885_MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MT6885_MUTEX_SOF_DSI0 | MT6885_MUTEX_EOF_DSI0, [DDP_MUTEX_SOF_DPI0] = MT6885_MUTEX_SOF_DPI0 | MT6885_MUTEX_EOF_DPI0, }; static const unsigned int mt6873_mutex_sof[DDP_MUTEX_SOF_MAX] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MT6873_MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MT6873_MUTEX_SOF_DSI0 | MT6873_MUTEX_EOF_DSI0, [DDP_MUTEX_SOF_DPI0] = MT6873_MUTEX_SOF_DPI0 | MT6873_MUTEX_EOF_DPI0, }; static const unsigned int mt6853_mutex_sof[DDP_MUTEX_SOF_MAX] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MT6853_MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MT6873_MUTEX_SOF_DSI0 | MT6853_MUTEX_EOF_DSI0, }; static const unsigned int mt6877_mutex_sof[DDP_MUTEX_SOF_MAX] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MT6877_MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MT6873_MUTEX_SOF_DSI0 | MT6877_MUTEX_EOF_DSI0, }; static const unsigned int mt6833_mutex_sof[DDP_MUTEX_SOF_MAX] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MT6833_MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MT6873_MUTEX_SOF_DSI0 | MT6833_MUTEX_EOF_DSI0, }; static const unsigned int mt6781_mutex_sof[DDP_MUTEX_SOF_MAX] = { [DDP_MUTEX_SOF_SINGLE_MODE] = MT6781_MUTEX_SOF_SINGLE_MODE, [DDP_MUTEX_SOF_DSI0] = MT6781_MUTEX_SOF_DSI0 | MT6781_MUTEX_EOF_DSI0, }; static const struct mtk_disp_ddp_data mt2701_ddp_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2701_mutex_sof, .mutex_mod_reg = MT2701_DISP_MUTEX0_MOD0, .mutex_sof_reg = MT2701_DISP_MUTEX0_SOF, }; static const struct mtk_disp_ddp_data mt2712_ddp_driver_data = { .mutex_mod = mt2712_mutex_mod, .mutex_sof = mt2712_mutex_sof, .mutex_mod_reg = MT2712_DISP_MUTEX0_MOD0, .mutex_sof_reg = MT2712_DISP_MUTEX0_SOF, }; static const struct mtk_disp_ddp_data mt8173_ddp_driver_data = { .mutex_mod = mt8173_mutex_mod, .mutex_sof = mt8173_mutex_sof, .mutex_mod_reg = MT8173_DISP_MUTEX0_MOD0, .mutex_sof_reg = MT8173_DISP_MUTEX0_SOF, }; static const struct mtk_disp_ddp_data mt6779_ddp_driver_data = { .mutex_mod = mt6779_mutex_mod, .mutex_sof = mt6779_mutex_sof, .mutex_mod_reg = MT6779_DISP_MUTEX0_MOD0, .mutex_sof_reg = MT6779_DISP_MUTEX0_SOF, }; static const struct mtk_disp_ddp_data mt6885_ddp_driver_data = { .mutex_mod = mt6885_mutex_mod, .mutex_sof = mt6885_mutex_sof, .mutex_mod_reg = MT6885_DISP_MUTEX0_MOD0, .mutex_sof_reg = MT6885_DISP_MUTEX0_SOF, }; static const struct mtk_disp_ddp_data mt6873_ddp_driver_data = { .mutex_mod = mt6873_mutex_mod, .mutex_sof = mt6873_mutex_sof, .mutex_mod_reg = MT6873_DISP_MUTEX0_MOD0, .mutex_sof_reg = MT6873_DISP_MUTEX0_SOF, }; static const struct mtk_disp_ddp_data mt6853_ddp_driver_data = { .mutex_mod = mt6853_mutex_mod, .mutex_sof = mt6853_mutex_sof, .mutex_mod_reg = MT6853_DISP_MUTEX0_MOD0, .mutex_sof_reg = MT6853_DISP_MUTEX0_SOF, }; static const struct mtk_disp_ddp_data mt6877_ddp_driver_data = { .mutex_mod = mt6877_mutex_mod, .mutex_sof = mt6877_mutex_sof, .mutex_mod_reg = MT6877_DISP_MUTEX0_MOD0, .mutex_sof_reg = MT6877_DISP_MUTEX0_SOF, }; static const struct mtk_disp_ddp_data mt6833_ddp_driver_data = { .mutex_mod = mt6833_mutex_mod, .mutex_sof = mt6833_mutex_sof, .mutex_mod_reg = MT6833_DISP_MUTEX0_MOD0, .mutex_sof_reg = MT6833_DISP_MUTEX0_SOF, }; static const struct mtk_disp_ddp_data mt6781_ddp_driver_data = { .mutex_mod = mt6781_mutex_mod, .mutex_sof = mt6781_mutex_sof, .mutex_mod_reg = MT6781_DISP_MUTEX0_MOD0, .mutex_sof_reg = MT6781_DISP_MUTEX0_SOF, }; const struct mtk_mmsys_reg_data mt2701_mmsys_reg_data = { .ovl0_mout_en = MT2701_DISP_OVL0_MOUT_EN, }; const struct mtk_mmsys_reg_data mt2712_mmsys_reg_data = { .ovl0_mout_en = MT2712_DISP_OVL0_MOUT_EN, .rdma1_sout_sel_in = DISP_REG_CONFIG_DISP_PATH1_SOUT_SEL_IN, .rdma1_sout_dpi0 = PATH1_SOUT_DPI0, .rdma1_sout_dsi0 = PATH1_SOUT_DSI0, .dpi0_sel_in = DISP_REG_CONFIG_DISP_DPI0_SEL_IN, .dpi0_sel_in_rdma1 = DPI0_SEL_IN_PATH1, }; const struct mtk_mmsys_reg_data mt8173_mmsys_reg_data = { .ovl0_mout_en = MT8173_DISP_OVL0_MOUT_EN, .rdma1_sout_sel_in = DISP_REG_CONFIG_DISP_PATH1_SOUT_SEL_IN, .rdma1_sout_dpi0 = PATH1_SOUT_DPI0, .rdma1_sout_dsi0 = PATH1_SOUT_DSI0, .dpi0_sel_in = DISP_REG_CONFIG_DISP_DPI0_SEL_IN, .dpi0_sel_in_rdma1 = DPI0_SEL_IN_PATH1, }; const struct mtk_mmsys_reg_data mt6779_mmsys_reg_data = { // To-Do .ovl0_mout_en = MT6779_DISP_OVL0_MOUT_EN, .rdma0_sout_sel_in = DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, .rdma0_sout_color0 = RDMA0_SOUT_COLOR0, }; const struct mtk_mmsys_reg_data mt6885_mmsys_reg_data = { // To-Do .ovl0_mout_en = MT6885_DISP_OVL0_MOUT_EN, .rdma0_sout_sel_in = MT6885_DISP_RDMA0_SEL_IN, .rdma0_sout_color0 = RDMA0_SOUT_COLOR0, }; const struct mtk_mmsys_reg_data mt6873_mmsys_reg_data = { // To-Do .ovl0_mout_en = MT6873_DISP_OVL0_MOUT_EN, .rdma0_sout_sel_in = MT6873_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL, .rdma0_sout_color0 = RDMA0_SOUT_COLOR0, }; const struct mtk_mmsys_reg_data mt6853_mmsys_reg_data = { .ovl0_mout_en = MT6853_DISP_OVL0_MOUT_EN, .rdma0_sout_sel_in = MT6853_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL, .rdma0_sout_color0 = RDMA0_SOUT_COLOR0, }; const struct mtk_mmsys_reg_data mt6833_mmsys_reg_data = { .ovl0_mout_en = MT6833_DISP_OVL0_MOUT_EN, .rdma0_sout_sel_in = MT6833_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL, .rdma0_sout_color0 = RDMA0_SOUT_COLOR0, }; const struct mtk_mmsys_reg_data mt6781_mmsys_reg_data = { .ovl0_mout_en = MT6781_DISP_OVL0_MOUT_EN, .rdma0_sout_sel_in = MT6781_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL, .rdma0_sout_color0 = RDMA0_SOUT_COLOR0, }; static char *ddp_signal_0_mt6885(int bit) { switch (bit) { case 0: return "AFBC_WDMA0_SEL__TO__D_UFBC_WDMA0"; case 1: return "AFBC_WDMA1_SEL__TO__D_UFBC_WDMA1"; case 2: return "D_AAL0__TO__D_GAMMA0"; case 3: return "D_AAL0_SEL__TO__D_AAL0"; case 4: return "D_AAL1__TO__D_GAMMA1"; case 5: return "D_CCORR0__TO__D_CCORR0_SOUT"; case 6: return "D_CCORR0_SOUT0__TO__MDP_AAL4_SEL0"; case 7: return "D_CCORR0_SOUT1__TO__D_AAL0_SEL1"; case 8: return "D_CCORR1__TO__D_CCORR1_SOUT"; case 9: return "D_CCORR1_SOUT0__TO__MDP_AAL5_SEL0"; case 10: return "D_CCORR1_SOUT1__TO__MDP_AAL1_SEL1"; case 11: return "D_COLOR0__TO__D_COLOR0_OUT_SEL0"; case 12: return "D_COLOR0_OUT_SEL__TO__D_CCORR0"; case 13: return "D_COLOR1__TO__D_COLOR1_OUT_SEL0"; case 14: return "D_COLOR1_OUT_SEL__TO__D_CCORR1"; case 15: return "D_DITHER0__TO__D_DITHER0_MOUT"; case 16: return "D_DITHER0_MOUT_OUT0__TO__DSI0_SEL1"; case 17: return "D_DITHER0_MOUT_OUT1__to__D_WDMA0_SEL0"; case 18: return "D_DITHER0_MOUT_OUT2__TO__DSI1_SEL2"; case 19: return "D_DITHER0_MOUT_OUT3__TO__D_PQ0_SOUT"; case 20: return "D_DITHER1__TO__D_DITHER1_MOUT"; case 21: return "D_DITHER1_MOUT_OUT0__TO__DSI1_SEL1"; case 22: return "D_DITHER1_MOUT_OUT1__TO__D_WDMA1_SEL0"; case 23: return "D_DITHER1_MOUT_OUT2__TO__D_PQ1_SOUT"; case 24: return "D_DP_WRAP_SEL__TO__DP_INTD0"; case 25: return "D_DSC_WRAP0_OUT0__TO__D_DSC_WRAP_SOUT"; case 26: return "D_DSC_WRAP0_OUT1__TO__DSI1_SEL3"; case 27: return "D_DSC_WRAP_SOUT0__TO__DSI0_SEL3"; case 28: return "D_DSC_WRAP_SOUT1__TO__D_DP_WRAP_SEL0"; case 29: return "D_DSI0_DSC_WRAP_SOUT0__TO__DSI0_SEL2"; case 30: return "D_DSI0_DSC_WRAP_SOUT1__TO__D_DSC_WRAP0_IN0"; case 31: return "D_GAMMA0__TO__D_POSTMASK0"; default: return NULL; } } static char *ddp_signal_1_mt6885(int bit) { switch (bit) { case 0: return "D_GAMMA1__TO__D_POSTMASK1"; case 1: return "MDP_AAL4_MDP_HDR4_SEL__TO__MDP_RSZ4"; case 2: return "MDP_AAL4_SEL__TO__MDP_AAL4"; case 3: return "MDP_AAL4_SOUT0__TO__D_AAL0_SEL0"; case 4: return "MDP_AAL4_SOUT1__TO__MDP_AAL4_MDP_HDR4_SEL1"; case 5: return "MDP_AAL5_MDP_HDR5_SEL__TO__MDP_RSZ5"; case 6: return "MDP_AAL5_SEL__TO__MDP_AAL5"; case 7: return "MDP_AAL5_SOUT0__TO__MDP_AAL1_SEL0"; case 8: return "MDP_AAL5_SOUT1__TO__MDP_AAL5_MDP_HDR5_SEL1"; case 9: return "MDP_TDSHP4_SOUT0__TO__D_OVL0_2L_IN1"; case 10: return "MDP_TDSHP4_SOUT1__TO__D_OVL0_IN1"; case 11: return "MDP_TDSHP5_SOUT0__TO__D_OVL1_2L_IN1"; case 12: return "MDP_TDSHP5_SOUT1__TO__D_OVL1_IN1"; case 13: return "D_MERGE0__TO__D_RDMA4_PQ0_MERGE0_SEL2"; case 14: return "D_MERGE1__TO__D_DP_WRAP_SEL1"; case 15: return "D_OVL0_2L_BLENDOUT_SOUT0__TO__D_TOVL0_OUT0_SEL0"; case 16: return "D_OVL0_2L_BLENDOUT_SOUT1__TO__D_TOVL0_OUT1_SEL0"; case 17: return "D_OVL0_2L_OUT0__TO__D_OVL0_2L_BLENDOUT_SOUT"; case 18: return "D_OVL0_2L_OUT1__TO__D_OVL0_2L_OVL1_2L_BG_SEL1"; case 19: return "D_OVL0_2L_OUT2__TO__D_OVL0_2L_PG_SEL1"; case 20: return "D_OVL0_2L_OVL1_2L_BG_SEL__TO__D_OVL0_IN0"; case 21: return "D_OVL0_BLENDOUT_SOUT0__TO__D_TOVL0_OUT0_SEL1"; case 22: return "D_OVL0_BLENDOUT_SOUT1__TO__D_TOVL0_OUT1_SEL1"; case 23: return "D_OVL0_OUT0__TO__D_OVL0_BLENDOUT_SOUT"; case 24: return "D_OVL0_OUT1__TO__D_OVL1_2L_BG_SEL1"; case 25: return "D_OVL0_OUT2__TO__D_OVL0_2L_PG_SEL0"; case 26: return "D_OVL0_2L_PG_SEL__TO__D_TOVL0_PQOUT_MDP_RDMA4_SEL1"; case 27: return "D_OVL1_2L_BG_SEL__TO__D_OVL0_2L_IN0"; case 28: return "D_OVL1_2L_BG_SOUT0__TO__D_OVL1_IN0"; case 29: return "D_OVL1_2L_BG_SOUT1__TO__D_OVL1_2L_BG_SEL0"; case 30: return "D_OVL1_2L_BLENDOUT_SOUT0__TO_D_TOVL1_OUT0_SEL0"; case 31: return "D_OVL1_2L_BLENDOUT_SOUT1__TO__D_OVL1_2L_BG_SEL0"; default: return NULL; } } static char *ddp_signal_2_mt6885(int bit) { switch (bit) { case 0: return "D_OVL1_2L_OUT0__TO__D_OVL1_2L_BLENDOUT_SOUT"; case 1: return "D_OVL1_2L_OUT1__TO__D_OVL1_2L_BG_SOUT"; case 2: return "D_OVL1_2L_OUT2__TO__D_OVL1_2L_PQOUT_SEL1"; case 3: return "D_OVL1_BG_SOUT0__TO__D_OVL1_2L_IN0"; case 4: return "D_OVL1_BG_SOUT1__TO__D_OVL1_2L_BG_SEL1"; case 5: return "D_OVL1_BLENDOUT_SOUT0__TO__D_TOVL1_OUT0_SEL1"; case 6: return "D_OVL1_BLENDOUT_SOUT1__TO__D_TOVL1_OUT1_SEL1"; case 7: return "D_OVL1_OUT0__TO__D_OVL1_BLENDOUT_SOUT"; case 8: return "D_OVL1_OUT1__TO__D_OVL1_BG_SOUT"; case 9: return "D_OVL1_OUT2__TO__D_OVL1_OUT1_2L_PQOUT_SEL0"; case 10: return "D_OVL1_2L_BG_SEL__TO__D_OVL1_2L_BG_SOUT"; case 11: return "D_OVL1_2L_BG_SOUT0__TO__D_OVL1_2L_BG_SEL"; case 12: return "D_OVL1_2L_BG_SOUT1__TO__D_OVL0_2L_OUT1_OVL1_2L_BG_SEL"; case 13: return "D_OVL1_2L_PQOUT_SEL__TO__D_TOVL1_PQOUT_MDP_RDMA5_SEL1"; case 14: return "D_OVL2_2L__TO__D_OVL2_2L_OUT0_MOUT"; case 15: return "D_OVL2_2L_OUT0_MOUT_OUT0__TO__D_RDMA4"; case 16: return "D_OVL2_2L_OUT0_MOUT_OUT1__TO__D_WDMA0_SEL4"; case 17: return "D_OVL3_2L_OUT0__TO__D_OVL3_2L_OUT0_MOUT"; case 18: return "D_OVL3_2L_OUT0_MOUT_OUT0__TO__D_RDMA5"; case 19: return "D_OVL3_2L_OUT0_MOUT_OUT1__TO__D_WDMA1_SEL4"; case 20: return "D_OVL3_2L_OUT1__TO__D_OVL2_2L"; case 21: return "D_POSTMASK0__TO__D_DITHER0"; case 22: return "D_POSTMASK1__TO__D_DITHER1"; case 23: return "D_PQ0_SOUT0__TO__D_MERGE0_IN0"; case 24: return "D_PQ0_SOUT1__TO__D_RDMA4_PQ0_MERGE0_SEL1"; case 25: return "D_PQ1_SOUT0__TO__D_MERGE0_IN0"; case 26: return "D_PQ1_SOUT1__TO__D_RDMA5_PQ1_SEL1"; case 27: return "D_RDMA0__TO__D_RDMA0_SOUT"; case 28: return "D_RDMA0_RSZ0_SEL__TO__D_RDMA0_RSZ0_SOUT"; case 29: return "D_RDMA0_RSZ0_SOUT0__TO__DSI0_SEL0"; case 30: return "D_RDMA0_RSZ0_SOUT1__TO__D_COLOR0"; case 31: return "D_RDMA0_RSZ0_SOUT2__TO_D_COLOR0_OUT_SEL1"; default: return NULL; } } static char *ddp_signal_3_mt6885(int bit) { switch (bit) { case 0: return "D_RDMA0_SEL__TO__D_RDMA0"; case 1: return "D_RDMA0_SOUT0__TO__D_RDMA0_RSZ0_SEL0"; case 2: return "D_RDMA0_SOUT1__TO__D_RSZ0_SEL2"; case 3: return "D_RDMA1__TO__D_RDMA1_SOUT"; case 4: return "D_RDMA1_TSZ1_SEL__TO__D_RDMA1_RSZ1_SOUT"; case 5: return "D_RDMA1_RSZ1_SOUT0__TO__DSI1_SEL0"; case 6: return "D_RDMA1_RSZ1_SOUT1__TO__D_COLOR1"; case 7: return "D_RDMA1_RSZ1_SOUT2__TO__D_COLOR1_OUT_SEL1"; case 8: return "D_RDMA1_SEL__TO__D_RDMA1"; case 9: return "D_RDMA1_SOUT0__TO__D_RDMA1_RSZ1_SEL0"; case 10: return "D_RDMA1_SOUT1__TO__D_RSZ1_SEL2"; case 11: return "D_RDMA2_RSZ0_RSZ1_SEL__TO__D_RDMA2_RSZ0_RSZ1_SOUT"; case 12: return "D_RDMA2_RSZ0_RSZ1_SOUT0__TO__D_OVL0_2L_IN2"; case 13: return "D_RDMA2_RSZ0_RSZ1_SOUT1__TO__D_OVL0_IN2"; case 14: return "D_RDMA3_SOUT0__TO__D_OVL1_2L_IN2"; case 15: return "D_RDMA3_SOUT1__TO__D_OVL1_IN2"; case 16: return "D_RDMA4__TO__D_RDMA4_SOUT"; case 17: return "D_RDMA4_PQ0_MERGE0_SEL__TO__D_DSI0_DSC_WRAP_SOUT"; case 18: return "D_RDMA4_SOUT0__TO__D_MERGE1_IN0"; case 19: return "D_RDMA4_SOUT1__TO__D_RDMA4_PQ0_MERGE0_SEL0"; case 20: return "D_RDMA4_SOUT2__TO__D_DP_WRAP_SEL2"; case 21: return "D_RDMA5__TO__D_RDMA5_SOUT"; case 22: return "D_RDMA5_PQ1_SEL__TO__D_DSC_WRAP0_IN1"; case 23: return "D_RDMA5_SOUT0__TO__D_MERGE1_IN1"; case 24: return "D_RDMA5_SOUT1__TO__D_RDMA5_PQ1_SEL0"; case 25: return "D_RSZ0__TO__D_RSZ0_MOUT"; case 26: return "D_RSZ0_MOUT_OUT0__TO__D_RDMA0_SEL1"; case 27: return "D_RSZ0_MOUT_OUT1__TO__D_WDMA0_SEL1"; case 28: return "D_RSZ0_MOUT_OUT2__TO__D_RDMA0_RSZ0_SEL1"; case 29: return "D_RSZ0_MOUT_OUT3__TO_D_RDMA2_RSZ0_RSZ1_SEL0"; case 30: return "D_RSZ0_SEL__TO__D_RSZ0"; case 31: return "D_RSZ1__TO__D_RSZ1_MOUT"; default: return NULL; } } static char *ddp_signal_4_mt6885(int bit) { switch (bit) { case 0: return "D_RSZ1_MOUT_OUT0__TO__D_RDMA1_SEL1"; case 1: return "D_RSZ1_MOUT_OUT1__TO__D_WDMA1_SEL1"; case 2: return "D_RSZ1_MOUT_OUT2__TO__D_RDMA1_RSZ1_SEL1"; case 3: return "D_RSZ1_MOUT_OUT3__TO__D_RDMA2_RSZ0_RSZ1_SEL1"; case 4: return "D_RSZ1_MOUT_OUT4__TO__D_RDMA3_SOUT"; case 5: return "D_RSZ1_SEL__TO__D_RSZ1"; case 6: return "D_TOVL0_OUT0_MOUT_OUT0__TO__D_WDMA0_SEL2"; case 7: return "D_TOVL0_OUT0_MOUT_OUT1__TO__D_RSZ0_SEL0"; case 8: return "D_TOVL0_OUT0_MOUT_OUT2__TO__AFBC_WDMA0_SEL0"; case 9: return "D_TOVL0_OUT0_SEL__TO__D_TOVL0_OUT0_MOUT"; case 10: return "D_TOVL0_OUT1_MOUT_OUT0__TO__D_RDMA0_SEL0"; case 11: return "D_TOVL0_OUT1_MOUT_OUT1__TO__D_RSZ0_SEL1"; case 12: return "D_TOVL0_OUT1_MOUT_OUT2__TO__D_WDMA0_SEL3"; case 13: return "D_TOVL0_OUT1_MOUT_OUT3__TO__AFBC_WDMA0_SEL1"; case 14: return "D_TOVL0_OUT1_SEL__TO__D_TOVL0_OUT1_MOUT"; case 15: return "D_TOVL0_PQOUT_MDP_RDMA4_SEL__TO__MDP_HDR4"; case 16: return "D_TOVL1_OUT0_MOUT_OUT0__TO__D_WDMA1_SEL2"; case 17: return "D_TOVL1_OUT0_MOUT_OUT1__TO__D_RSZ1_SEL0"; case 18: return "D_TOVL1_OUT0_MOUT_OUT2__TO__AFBC_WDMA1_SEL0"; case 19: return "D_TOVL1_OUT0_SEL__TO__D_TOVL1_OUT0_MOUT"; case 20: return "D_TOVL1_OUT1_MOUT_OUT0__TO__D_RDMA1_SEL0"; case 21: return "D_TOVL1_OUT1_MOUT_OUT1__TO__D_RSZ1_SEL1"; case 22: return "D_TOVL1_OUT1_MOUT_OUT2__TO__D_WDMA1_SEL3"; case 23: return "D_TOVL1_OUT1_MOUT_OUT3__TO__AFBC_WDMA1_SEL1"; case 24: return "D_TOVL1_OUT1_SEL__TO__D_TOVL1_OUT1_MOUT"; case 25: return "D_TOVL1_PQOUT_MDP_RDMA5_SEL__TO__MDP_HDR5"; case 26: return "D_WDMA0_SEL__TO__D_WDMA0"; case 27: return "D_WDMA1_SEL__TO__D_WDMA1"; case 28: return "DSI0_SEL__TO__THP_LMT_DSI0"; case 29: return "DSI1_SEL__TO__THP_LMT_DSI1"; case 30: return "MDP_AAL1_SEL__TO__D_AAL1"; case 31: return "MDP_AAL4__TO__MDP_AAL4_SOUT"; default: return NULL; } } static char *ddp_signal_5_mt6885(int bit) { switch (bit) { case 0: return "MDP_AAL4_SOUT0__TO__MDP_AAL4_MDP_HDR4_SEL0"; case 1: return "MDP_AAL4_SOUT1__TO__MDP_AAL4_SEL1"; case 2: return "MDP_AAL5__TO__MDP_AAL5_SOUT"; case 3: return "MDP_AAL5_SOUT0__TO__MDP_AAL5_MDP_HDR5_SEL0"; case 4: return "MDP_AAL5_SOUT1__TO__DIS_MDP_AAL5_SEL1"; case 5: return "MDP_HDR4__TO__MDP_AAL4_SOUT"; case 6: return "MDP_HDR5__TO__MDP_AAL5_SOUT"; case 7: return "MDP_RDMA4__TO__D_TOVL0_PQOUT_MDP_RDMA4_SEL0"; case 8: return "MDP_RDMA5__TO__D_TOVL1_PQOUT_MDP_RDMA5_SEL0"; case 9: return "MDP_RSZ4__TO__MDP_TDSHP4"; case 10: return "MDP_RSZ5__TO__MDP_TDSHP5"; case 11: return "MDP_TDSHP4__TO__MDP_TDSHP4_SOUT"; case 12: return "MDP_TDSHP5__TO__MDP_TDSHP5_SOUT"; case 13: return "THP_LMT_DSI0__TO__DSI0"; case 14: return "THP_LMT_DSI1__TO__DSI1"; default: return NULL; } } static char *ddp_signal_mt6885(int idx, int bit) { switch (idx) { case 0: return ddp_signal_0_mt6885(bit); case 1: return ddp_signal_1_mt6885(bit); case 2: return ddp_signal_2_mt6885(bit); case 3: return ddp_signal_3_mt6885(bit); case 4: return ddp_signal_4_mt6885(bit); case 5: return ddp_signal_5_mt6885(bit); default: return NULL; } } /* MMSYS_DL_VALID0/MMSYS_DL_READY0 */ static char *ddp_signal_0_mt6873(int bit) { switch (bit) { case 0: return "afbc_wdma0_sel__to__disp_ufbc_wdma0"; case 1: return "disp_aal0__to__disp_gamma0"; case 2: return "disp_aal0_sel__to__disp_aal0"; case 3: return "disp_ccorr0__to__disp_ccorr0_sout"; case 4: return "disp_ccorr0_sout_out0__to__disp_mdp_aal4_sel_in0"; case 5: return "disp_ccorr0_sout_out1__to__disp_aal0_sel_in1"; case 6: return "disp_color0__to__disp_ccorr0"; case 7: return "disp_dither0__to__disp_dither0_mout"; case 8: return "disp_dither0_mout_out0__to__dsi0_sel_in1"; case 9: return "disp_dither0_mout_out1__to__disp_dsc_wrap0"; case 10: return "disp_dither0_mout_out2__to__disp_wdma0_sel_in0"; case 11: return "disp_dither0_mout_out3__to__afbc_wdma0_sel_in0"; case 12: return "disp_dsc_wrap0__to__dsi0_sel_in2"; case 13: return "disp_gamma0__to__disp_postmask0"; case 14: return "disp_mdp_aal4_mdp_hdr4_sel__to__mdp_rsz4"; case 15: return "disp_mdp_aal4_sel__to__mdp_aal4"; case 16: return "disp_mdp_aal4_sout_out0__to__disp_aal0_sel_in0"; case 17: return "disp_mdp_aal4_sout_out1__to__disp_mdp_aal4_mdp_hdr4_sel_in1"; case 18: return "disp_mdp_tdshp4_sout_out0__to__disp_ovl0_2l_ufod_sel_in1"; case 19: return "disp_mdp_tdshp4_sout_out1__to__disp_ovl0_ufod_sel_in1"; case 20: return "disp_mdp_tdshp4_sout_out2__to__disp_ovl0_2l_in1"; case 21: return "disp_mdp_tdshp4_sout_out3__to__disp_ovl0_in1"; case 22: return "disp_ovl0_2l_out0__to__disp_tovl0_out0_mout"; case 23: return "disp_ovl0_2l_out1__to__disp_ovl0_in0"; case 24: return "disp_ovl0_2l_ufod_sel__to__disp_ovl0_2l_in2"; case 25: return "disp_ovl0_out0__to__disp_tovl0_out1_mout"; case 26: return "disp_ovl0_out1__to__disp_ovl0_2l_in0"; case 27: return "disp_ovl0_ovl0_2l_pqout_sel__to__disp_tovl0_pqout_mdp_rdma4_sel_in1"; case 28: return "disp_ovl0_ufod_sel__to__disp_ovl0_in2"; case 29: return "disp_ovl2_2l__to__disp_ovl2_2l_out0_mout"; case 30: return "disp_ovl2_2l_out0_mout_out0__to__disp_rdma4"; case 31: return "disp_ovl2_2l_out0_mout_out1__to__disp_wdma0_sel_in4"; default: return NULL; } } static char *ddp_signal_1_mt6873(int bit) { switch (bit) { case 0: return "disp_ovl2_2l_out0_mout_out2__to__afbc_wdma0_sel_in4"; case 1: return "disp_postmask0__to__disp_dither0"; case 2: return "disp_rdma0__to__disp_rdma0_rsz0_sout"; case 3: return "disp_rdma0_rsz0_sout_out0__to__dsi0_sel_in0"; case 4: return "disp_rdma0_rsz0_sout_out1__to__disp_color0"; case 5: return "disp_rdma0_sel__to__disp_rdma0"; case 6: return "disp_rdma2_rsz0_rsz1_sout_out0__to__disp_ovl0_2l_ufod_sel_in0"; case 7: return "disp_rdma2_rsz0_rsz1_sout_out1__to__disp_ovl0_ufod_sel_in0"; case 8: return "disp_rdma4__to__disp_dpi0"; case 9: return "disp_rsz0__to__disp_rsz0_mout"; case 10: return "disp_rsz0_mout_out0__to__disp_rdma0_sel_in1"; case 11: return "disp_rsz0_mout_out1__to__disp_wdma0_sel_in1"; case 12: return "disp_rsz0_mout_out2__to__afbc_wdma0_sel_in1"; case 13: return "disp_rsz0_mout_out3__to__disp_rdma2_rsz0_rsz1_sout"; case 14: return "disp_rsz0_mout_out4__to__disp_tovl0_pqout_mdp_rdma4_sel_in2"; case 15: return "disp_rsz0_sel__to__disp_rsz0"; case 16: return "disp_tovl0_out0_mout_out0__to__disp_rdma0_sel_in3"; case 17: return "disp_tovl0_out0_mout_out1__to__disp_rsz0_sel_in0"; case 18: return "disp_tovl0_out0_mout_out2__to__disp_wdma0_sel_in2"; case 19: return "disp_tovl0_out0_mout_out3__to__afbc_wdma0_sel_in2"; case 20: return "disp_tovl0_out0_mout_out4__to__disp_ovl0_ovl0_2l_pqout_sel_in0"; case 21: return "disp_tovl0_out1_mout_out0__to__disp_rdma0_sel_in0"; case 22: return "disp_tovl0_out1_mout_out1__to__disp_rsz0_sel_in1"; case 23: return "disp_tovl0_out1_mout_out2__to__disp_wdma0_sel_in3"; case 24: return "disp_tovl0_out1_mout_out3__to__afbc_wdma0_sel_in3"; case 25: return "disp_tovl0_out1_mout_out4__to__disp__ovl0_ovl0_2l_pqout_sel_in1"; case 26: return "disp_tovl0_pqout_mdp_rdma4_sel__to__mdp_hdr4"; case 27: return "disp_wdma0_sel__to__disp_wdma0"; case 28: return "disp_y2r0__to__disp_y2r0_sout"; case 29: return "disp_y2r0_sout_out0__to__disp_mdp_tdshp4_sout"; case 30: return "disp_y2r0_sout_out1__to__disp_rdma0_sel_in2"; case 31: return "dsi0_sel__to__thp_lmt_dsi0"; default: return NULL; } } static char *ddp_signal_2_mt6873(int bit) { switch (bit) { case 0: return "mdp_aal4__to__disp_mdp_aal4_sout"; case 1: return "mdp_aal4_sout_out0__to__disp_mdp_aal4_mdp_hdr4_sel_in0"; case 2: return "mdp_aal4_sout_out1__to__disp_mdp_aal4_sel_in1"; case 3: return "mdp_color4__to__disp_y2r0"; case 4: return "mdp_hdr4__to__mdp_aal4_sout"; case 5: return "mdp_rmda4__to__disp_tovl0_pqout_mdp_rdma4_sel_in0"; case 6: return "mdp_rsz4__to__mdp_tdshp4"; case 7: return "mdp_tdshp4__to__mdp_color4"; case 8: return "thp_lmt_dsi0__to__dsi0"; default: return NULL; } } /* MMSYS_DL_VALID0/MMSYS_DL_READY0 */ static char *ddp_signal_0_mt6853(int bit) { switch (bit) { case 0: return "DISP_AAL0_TO_DISP_GAMMA0_VALID"; case 1: return "DISP_BYPASS_SPR0_SEL_TO_DISP_SPR0_MOUT_VALID"; case 2: return "DISP_CCORR0_TO_DISP_CCORR1_VALID"; case 3: return "DISP_CCORR1_TO_DISP_AAL0_VALID"; case 4: return "DISP_CM0_TO_DISP_SPR0_VALID"; case 5: return "DISP_COLOR0_TO_DISP_CCORR0_VALID"; case 6: return "DISP_DITHER0_TO_DISP_DITHER0_MOUT_VALID"; case 7: return "DISP_DITHER0_MOUT_OUT0_TO_BYPA_SPR0_SEL_IN0_VALID"; case 8: return "DISP_DITHER0_MOUT_OUT1_TO_DISP_CM0_VALID"; case 9: return "DISP_DITHER0_MOUT_OUT2_TO_DISP_WDMA0_SEL_IN4_VALID"; case 10: return "DISP_DSC_WRAP0_TO_DSI0_SEL_IN2_VALID"; case 11: return "DISP_GAMMA0_TO_DISP_POSTMASK0_VALID"; case 12: return "DISP_OVL0_2L_OUT0_TO_DISP_TOVL0_OUT0_MOUT_VALID"; case 13: return "DISP_OVL0_2L_OUT1_TO_DISP_OVL0_IN0_VALID"; case 14: return "DISP_OVL0_OUT0_TO_DISP_TOVL0_OUT1_MOUT_VALID"; case 15: return "DISP_OVL0_OUT1_TO_DISP_OVL0_2L_IN0_VALID"; case 16: return "DISP_POSTMASK0_TO_DISP_DITHER0_VALID"; case 17: return "DISP_RDMA0_TO_DISP_RDMA0_RSZ0_SOUT_VALID"; case 18: return "DISP_RDMA0_RSZ0_SOUT_OUT0_TO_DSI0_SEL_IN0_VALID"; case 19: return "DISP_RDMA0_RSZ0_SOUT_OUT1_TO_DISP_COLOR0_VALID"; case 20: return "DISP_RDMA0_SEL_TO_DISP_RDMA0_VALID"; case 21: return "DISP_RDMA2_RSZ0_RSZ1_SOUT_OUT0_TO_OVL0_2L_IN2_VALID"; case 22: return "DISP_RDMA2_RSZ0_RSZ1_SOUT_OUT1_TO_OVL0_IN2_VALID"; case 23: return "DISP_RSZ0_TO_DISP_RSZ0_MOUT_VALID"; case 24: return "DISP_RSZ0_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN1_VALID"; case 25: return "DISP_RSZ0_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN1_VALID"; case 26: return "DISP_RSZ0_MOUT_OUT2_TO_RDMA2_RSZ0_RSZ1_SOUT_VALID"; case 27: return "DISP_RSZ0_SEL_TO_DISP_RSZ0_VALID"; case 28: return "DISP_SPR0_TO_DISP_BYPASS_SPR0_SEL_IN1_VALID"; case 29: return "DISP_SPR0_MOUT_OUT0_TO_DSI0_SEL_IN1_VALID"; case 30: return "DISP_SPR0_MOUT_OUT1_TO_DISP_WDMA0_SEL_IN0_VALID"; case 31: return "DISP_SPR0_MOUT_OUT2_TO_DISP_DSC_WRAP0_VALID"; default: return NULL; } } static char *ddp_signal_1_mt6853(int bit) { switch (bit) { case 0: return "DISP_TOVL0_OUT0_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN2_VALID"; case 1: return "DISP_TOVL0_OUT0_MOUT_OUT1_TO_DISP_RSZ0_SEL_IN0_VALID"; case 2: return "TOVL0_OUT0_MOUT_OUT2_TO_DISP_WDMA0_SEL_IN2_VALID"; case 3: return "DISP_TOVL0_OUT1_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN0_VALID"; case 4: return "DISP_TOVL0_OUT1_MOUT_OUT1_TO_DISP_RSZ0_SEL_IN1_VALID"; case 5: return "DISP_TOVL0_OUT1_MOUT_OUT2_TO_DISP_WDMA0_SEL_IN3_VALID"; case 6: return "DISP_WDMA0_SEL_TO_DISP_WDMA0_VALID"; case 7: return "THP_LMT_DSI0_TO_DSI0_VALID"; default: return NULL; } } static char *ddp_signal_0_mt6877(int bit) { switch (bit) { case 0: return "DISP_AAL0_TO_DISP_GAMMA0_VALID"; case 1: return "DISP_BYPASS_SPR0_SEL_TO_DISP_SPR0_MOUT_VALID"; case 2: return "DISP_CCORR0_TO_DISP_CCORR1_VALID"; case 3: return "DISP_CCORR1_TO_DISP_AAL0_VALID"; case 4: return "DISP_CM0_TO_DISP_SPR0_VALID"; case 5: return "DISP_COLOR0_TO_DISP_CCORR0_VALID"; case 6: return "DISP_DITHER0_TO_DISP_DITHER0_MOUT_VALID"; case 7: return "DISP_DITHER0_MOUT_OUT0_TO_BYPA_SPR0_SEL_IN0_VALID"; case 8: return "DISP_DITHER0_MOUT_OUT1_TO_DISP_CM0_VALID"; case 9: return "DISP_DITHER0_MOUT_OUT2_TO_DISP_WDMA0_SEL_IN4_VALID"; case 10: return "DISP_DSC_WRAP0_TO_DSI0_SEL_IN2_VALID"; case 11: return "DISP_GAMMA0_TO_DISP_POSTMASK0_VALID"; case 12: return "DISP_OVL0_2L_OUT0_TO_DISP_TOVL0_OUT0_MOUT_VALID"; case 13: return "DISP_OVL0_2L_OUT1_TO_DISP_OVL0_IN0_VALID"; case 14: return "DISP_OVL0_OUT0_TO_DISP_TOVL0_OUT1_MOUT_VALID"; case 15: return "DISP_OVL0_OUT1_TO_DISP_OVL0_2L_IN0_VALID"; case 16: return "DISP_POSTMASK0_TO_DISP_DITHER0_VALID"; case 17: return "DISP_RDMA0_TO_DISP_RDMA0_RSZ0_SOUT_VALID"; case 18: return "DISP_RDMA0_RSZ0_SOUT_OUT0_TO_DSI0_SEL_IN0_VALID"; case 19: return "DISP_RDMA0_RSZ0_SOUT_OUT1_TO_DISP_COLOR0_VALID"; case 20: return "DISP_RDMA0_SEL_TO_DISP_RDMA0_VALID"; case 21: return "DISP_RDMA2_RSZ0_RSZ1_SOUT_OUT0_TO_OVL0_2L_IN2_VALID"; case 22: return "DISP_RDMA2_RSZ0_RSZ1_SOUT_OUT1_TO_OVL0_IN2_VALID"; case 23: return "DISP_RSZ0_TO_DISP_RSZ0_MOUT_VALID"; case 24: return "DISP_RSZ0_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN1_VALID"; case 25: return "DISP_RSZ0_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN1_VALID"; case 26: return "DISP_RSZ0_MOUT_OUT2_TO_RDMA2_RSZ0_RSZ1_SOUT_VALID"; case 27: return "DISP_RSZ0_SEL_TO_DISP_RSZ0_VALID"; case 28: return "DISP_SPR0_TO_DISP_BYPASS_SPR0_SEL_IN1_VALID"; case 29: return "DISP_SPR0_MOUT_OUT0_TO_DSI0_SEL_IN1_VALID"; case 30: return "DISP_SPR0_MOUT_OUT1_TO_DISP_WDMA0_SEL_IN0_VALID"; case 31: return "DISP_SPR0_MOUT_OUT2_TO_DISP_DSC_WRAP0_VALID"; default: return NULL; } } static char *ddp_signal_1_mt6877(int bit) { switch (bit) { case 0: return "DISP_TOVL0_OUT0_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN2_VALID"; case 1: return "DISP_TOVL0_OUT0_MOUT_OUT1_TO_DISP_RSZ0_SEL_IN0_VALID"; case 2: return "TOVL0_OUT0_MOUT_OUT2_TO_DISP_WDMA0_SEL_IN2_VALID"; case 3: return "DISP_TOVL0_OUT1_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN0_VALID"; case 4: return "DISP_TOVL0_OUT1_MOUT_OUT1_TO_DISP_RSZ0_SEL_IN1_VALID"; case 5: return "DISP_TOVL0_OUT1_MOUT_OUT2_TO_DISP_WDMA0_SEL_IN3_VALID"; case 6: return "DISP_WDMA0_SEL_TO_DISP_WDMA0_VALID"; case 7: return "THP_LMT_DSI0_TO_DSI0_VALID"; default: return NULL; } } /* MMSYS_DL_VALID0/MMSYS_DL_READY0 */ static char *ddp_signal_0_mt6833(int bit) { switch (bit) { case 0: return "DISP_AAL0_TO_DISP_GAMMA0_VALID"; case 1: return "DISP_CCORR0_TO_DISP_AAL0_VALID"; case 2: return "DISP_COLOR0_TO_DISP_CCORR0_VALID"; case 3: return "DISP_DITHER0_TO_DISP_DITHER0_MOUT_VALID"; case 4: return "DISP_DITHER0_MOUT_OUT0_TO_DSI0_SEL_IN1_VALID"; case 5: return "DISP_DITHER0_MOUT_OUT1_TO_DISP_WDMA0_SEL_IN0_VALID"; case 6: return "DISP_GAMMA0_TO_DISP_POSTMASK0_VALID"; case 7: return "DISP_OVL0_2L_OUT0_TO_DISP_TOVL0_OUT0_MOUT_VALID"; case 8: return "DISP_OVL0_2L_OUT1_TO_DISP_OVL0_IN0_VALID"; case 9: return "DISP_OVL0_OUT0_TO_DISP_TOVL0_OUT1_MOUT_VALID"; case 10: return "DISP_OVL0_OUT1_TO_DISP_OVL0_2L_IN0_VALID"; case 11: return "DISP_POSTMASK0_TO_DISP_DITHER0_VALID"; case 12: return "DISP_RDMA0_TO_DISP_RDMA0_RSZ0_SOUT_VALID"; case 13: return "DISP_RDMA0_RSZ0_SOUT_OUT0_TO_DSI0_SEL_IN0_VALID"; case 14: return "DISP_RDMA0_RSZ0_SOUT_OUT1_TO_DISP_COLOR0_VALID"; case 15: return "DISP_RDMA0_SEL_TO_DISP_RDMA0_VALID"; case 16: return "DISP_RDMA2_RSZ0_RSZ1_SOUT_OUT0_TO_OVL0_2L_IN2_VALID"; case 17: return "DISP_RDMA2_RSZ0_RSZ1_SOUT_OUT1_TO_OVL0_IN2_VALID"; case 18: return "DISP_RSZ0_TO_DISP_RSZ0_MOUT_VALID"; case 19: return "DISP_RSZ0_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN1_VALID"; case 20: return "DISP_RSZ0_MOUT_OUT1_TO_DISP_WDMA0_SEL_IN1_VALID"; case 21: return "DISP_RSZ0_MOUT_OUT2_TO_RDMA2_RSZ0_RSZ1_SOUT_VALID"; case 22: return "DISP_RSZ0_SEL_TO_DISP_RSZ0_VALID"; case 23: return "DISP_TOVL0_OUT0_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN2_VALID"; case 24: return "DISP_TOVL0_OUT0_MOUT_OUT1_TO_DISP_RSZ0_SEL_IN0_VALID"; case 25: return "DISP_TOVL0_OUT0_MOUT_OUT2_TO_DISP_WDMA0_SEL_IN2_VALID"; case 26: return "DISP_TOVL0_OUT1_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN0_VALID"; case 27: return "DISP_TOVL0_OUT1_MOUT_OUT1_TO_DISP_RSZ0_SEL_IN1_VALID"; case 28: return "DISP_TOVL0_OUT1_MOUT_OUT2_TO_DISP_WDMA0_SEL_IN3_VALID"; case 29: return "DISP_WDMA0_SEL_TO_DISP_WDMA0_VALID"; case 30: return "DSI0_SEL_TO_THP_LMT_DSI0_VALID"; case 31: return "THP_LMT_DSI0_TO_DSI0_VALID"; default: return NULL; } } static char *ddp_signal_0_mt6781(int bit) { switch (bit) { case 0: return "DISP_AAL0_TO_DISP_GAMMA0"; case 1: return "DISP_CCORR0_TO_DISP_AAL0"; case 2: return "DISP_COLOR0_TO_DISP_CCORR0"; case 3: return "DISP_DITHER0_TO_DISP_DITHER0_MOUT"; case 4: return "DISP_DITHER0_MOUT_OUT0_TO_DSI0_SEL_IN1"; case 5: return "DISP_DITHER0_MOUT_OUT1_TO_DISP_WDMA0_SEL_IN0"; case 6: return "DISP_DITHER0_MOUT_OUT2_TO_DISP_DSC_WRAP0"; case 7: return "DISP_GAMMA0_TO_DISP_POSTMASK0"; case 8: return "DISP_OVL0_2L_OUT0_TO_DISP_TOVL0_OUT0_MOUT"; case 9: return "DISP_OVL0_2L_OUT1_TO_DISP_OVL0_IN0"; case 10: return "DISP_OVL0_OUT0_TO_DISP_TOVL0_OUT1_MOUT"; case 11: return "DISP_OVL0_OUT1_TO_DISP_OVL0_2L_IN0"; case 12: return "DISP_POSTMASK0_TO_DISP_DITHER0"; case 13: return "DISP_RDMA0_TO_DISP_RDMA0_RSZ0_SOUT"; case 14: return "DISP_RDMA0_RSZ0_SOUT_OUT0_TO_DSI0_SEL_IN0"; case 15: return "DISP_RDMA0_RSZ0_SOUT_OUT1_TO_DISP_COLOR0"; case 16: return "DISP_RDMA0_SEL_TO_DISP_RDMA0"; case 17: return "DISP_RDMA2_RSZ0_RSZ1_SOUT_OUT0_TO_DISP_OVL0_2L_IN2"; case 18: return "DISP_RDMA2_RSZ0_RSZ1_SOUT_OUT1_TO_DISP_OVL0_IN2"; case 19: return "DISP_RSZ0_TO_DISP_RSZ0_MOUT"; case 20: return "DISP_RSZ0_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN1"; case 21: return "DISP_RSZ0_MOUT_OUT1_TO_DISP_WDMA0_SEL_IN1"; case 22: return "DISP_RSZ0_MOUT_OUT2_TO_DISP_RDMA2_RSZ0_RSZ1_SOUT"; case 23: return "DISP_RSZ0_SEL_TO_DISP_RSZ0"; case 24: return "DISP_TOVL0_OUT0_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN2"; case 25: return "DISP_TOVL0_OUT0_MOUT_OUT1_TO_DISP_RSZ0_SEL_IN0"; case 26: return "DISP_TOVL0_OUT0_MOUT_OUT2_TO_DISP_WDMA0_SEL_IN2"; case 27: return "DISP_TOVL0_OUT1_MOUT_OUT0_TO_DISP_RDMA0_SEL_IN0"; case 28: return "DISP_TOVL0_OUT1_MOUT_OUT1_TO_DISP_RSZ0_SEL_IN1"; case 29: return "DISP_TOVL0_OUT1_MOUT_OUT2_TO_DISP_WDMA0_SEL_IN3"; case 30: return "DISP_WDMA0_SEL_TO_DISP_WDMA0"; case 31: return "DSI0_SEL_TO_THP_LMT_DSI0"; default: return NULL; } } static char *ddp_signal_1_mt6781(int bit) { switch (bit) { case 0: return "THP_LMT_DSI0_TO_DSI0"; case 1: return "DISP_DSC_WRAP0_MOUT_OUT0_TO_DISP_WDMA0_SEL_IN4"; case 2: return "DISP_DSC_WRAP0_MOUT_OUT1_TO_DSI0_SEL_IN2"; default: return NULL; } } static char *ddp_greq_name_mt6885(int bit) { switch (bit) { case 0: return "OVL0 "; case 1: return "OVL0_2L "; case 2: return "DISP_RDMA0 "; case 3: return "DISP_WDMA0 "; case 4: return "MDP_RDMA0 "; case 5: return "MDP_WDMA0 "; case 6: return "MDP_WROT0 "; case 7: return "DISP_FAKE "; default: return NULL; } } static char *ddp_greq_name_larb0_mt6873(int bit) { switch (bit) { case 0: return "DISP_POSTMASK0 "; case 1: return "DISP_OVL0_HDR "; case 2: return "DISP_OVL0 "; case 3: return "DISP_RDMA0 "; case 4: return "DISP_WDMA0 "; case 5: return "DISP_FAKE_ENG0 "; default: return NULL; } } static char *ddp_greq_name_larb1_mt6873(int bit) { switch (bit) { case 0: return "DISP_OVL0_2L_HDR "; case 1: return "DISP_OVL2_2L_HDR "; case 2: return "DISP_OVL0_2L "; case 3: return "DISP_OVL2_2L "; case 4: return "MDP_RDMA4 "; case 5: return "DISP_RDMA4 "; case 6: return "DISP_UFBC_WDMA0 "; case 7: return "DISP_FAKE_ENG1 "; default: return NULL; } } static char *ddp_greq_name_larb0_mt6853(int bit) { switch (bit) { case 0: return "DISP_POSTMASK0 "; case 1: return "DISP_OVL0_HDR "; case 2: return "DISP_OVL0 "; case 3: return "DISP_FAKE_ENG0 "; default: return NULL; } } static char *ddp_greq_name_larb1_mt6853(int bit) { switch (bit) { case 0: return "DISP_OVL0_2L_HDR "; case 1: return "DISP_OVL0_2L "; case 2: return "DISP_RDMA0"; case 3: return "DISP_WDMA0"; case 4: return "DISP_FAKE_ENG1 "; default: return NULL; } } static char *ddp_greq_name_larb0_mt6877(int bit) { switch (bit) { case 0: return "DISP_POSTMASK0 "; case 1: return "DISP_OVL0_HDR "; case 2: return "DISP_OVL0 "; case 3: return "DISP_FAKE_ENG0 "; default: return NULL; } } static char *ddp_greq_name_larb1_mt6877(int bit) { switch (bit) { case 0: return "DISP_OVL0_2L_HDR "; case 1: return "DISP_OVL0_2L "; case 2: return "DISP_RDMA0"; case 3: return "DISP_WDMA0"; case 4: return "DISP_FAKE_ENG1 "; default: return NULL; } } static char *ddp_greq_name_larb0_mt6833(int bit) { switch (bit) { case 0: return "DISP_POSTMASK0 "; case 1: return "OVL0_RDMA0_HDR "; case 2: return "OVL_RDMA0 "; case 3: return "DISP_FAKE_ENG0 "; default: return NULL; } } static char *ddp_greq_name_larb1_mt6833(int bit) { switch (bit) { case 0: return "OVL_2L_RDMA0_HDR "; case 1: return "OVL_2L_RDMA0 "; case 2: return "DISP_RDMA0 "; case 3: return "DISP_WDMA0 "; case 4: return "DISP_FAKE_ENG1 "; default: return NULL; } } static char *ddp_greq_name_larb0_mt6781(int bit) { switch (bit) { case 0: return "DISP_POSTMASK0 "; case 1: return "null module "; case 2: return "DISP_OVL0 "; case 3: return "DISP_FAKE_ENG0 "; default: return NULL; } } static char *ddp_greq_name_larb1_mt6781(int bit) { switch (bit) { case 0: return "DISP_RDMA1 "; case 1: return "DISP_OVL0_2L "; case 2: return "DISP_RDMA0"; case 3: return "DISP_WDMA0"; case 4: return "DISP_FAKE_ENG1 "; default: return NULL; } } static char *ddp_get_mutex_module0_name_mt6885(unsigned int bit) { switch (bit) { case 0: return "ovl0"; case 1: return "ovl0_2l"; case 2: return "rdma0"; case 3: return "wdma0"; case 4: return "color0"; case 5: return "ccorr0"; case 6: return "aal0"; case 7: return "gamma0"; case 8: return "dither0"; case 9: return "dsi0"; case 10: return "rsz0"; case 11: return "pwm0"; case 12: return "ovl1"; case 13: return "ovl1_2l"; case 14: return "rdma1"; case 15: return "wdma1"; case 16: return "color1"; case 17: return "ccorr1"; case 18: return "aal1"; case 19: return "gamma1"; case 20: return "dither1"; case 21: return "dsi1"; case 22: return "rsz1"; case 23: return "ovl2_2l"; case 24: return "ovl3_2l"; case 25: return "postmask0"; case 26: return "postmask1"; case 27: return "merge0"; case 28: return "merge1"; case 29: return "dsc0"; case 30: return "dsc1"; case 31: return "dp_intf"; default: break; } return "unknown-mutex"; } static char *ddp_get_mutex_module1_name_mt6885(unsigned int bit) { switch (bit) { case 0: return "mdp_aal4"; case 1: return "mdp_aal5"; case 2: return "mdp_rdma4"; case 3: return "mdp_rdma4"; case 4: return "mdp_hdr4"; case 5: return "mdp_hdr5"; case 6: return "mdp_rsz4"; case 7: return "mdp_rsz5"; case 8: return "mdp_tdshp4"; case 9: return "mdp_tdshp5"; case 10: return "rdma4"; case 11: return "rdma5"; default: break; } return "unknown-mutex"; } static char *ddp_get_mutex_module0_name_mt6873(unsigned int bit) { switch (bit) { case 0: return "disp_ovl0"; case 1: return "disp_ovl0_2l"; case 2: return "disp_rdma0"; case 3: return "disp_rsz0"; case 4: return "disp_color0"; case 5: return "disp_ccorr0"; case 6: return "disp_aal0"; case 7: return "disp_gamma0"; case 8: return "disp_postmask0"; case 9: return "disp_dither0"; case 10: return "disp_dsc_wrap0_core0"; case 11: return "disp_dsc_wrap0_core1"; case 12: return "dsi0"; case 13: return "disp_wdma0"; case 14: return "disp_ufbc_wdma0"; case 15: return "disp_pwm0"; case 16: return "disp_ovl2_2l"; case 17: return "disp_rdma4"; case 18: return "dpi0"; case 19: return "mdp_rdma4"; case 20: return "mdp_hdr4"; case 21: return "mdp_rsz4"; case 22: return "mdp_aal4"; case 23: return "mdp_tdshp4"; case 24: return "mdp_color4"; case 25: return "disp_y2r0"; default: return "mutex-unknown"; } } static char *ddp_get_mutex_module0_name_mt6853(unsigned int bit) { switch (bit) { case 0: return "disp_ovl0"; case 1: return "disp_ovl0_2l"; case 2: return "disp_rdma0"; case 3: return "disp_rsz0"; case 4: return "disp_color0"; case 5: return "disp_ccorr0"; case 6: return "disp_ccorr1"; case 7: return "disp_aal0"; case 8: return "disp_gamma0"; case 9: return "disp_postmask0"; case 10: return "disp_dither0"; case 11: return "disp_cm0"; case 12: return "spr0"; case 13: return "disp_dsc_wrap0"; case 14: return "dsi0"; case 15: return "disp_wdma0"; case 16: return "disp_pwm0"; default: return "mutex-unknown"; } } static char *ddp_get_mutex_module0_name_mt6877(unsigned int bit) { switch (bit) { case 0: return "disp_ovl0"; case 1: return "disp_ovl0_2l"; case 2: return "disp_rdma0"; case 3: return "disp_rsz0"; case 4: return "disp_color0"; case 5: return "disp_ccorr0"; case 6: return "disp_ccorr1"; case 7: return "disp_aal0"; case 8: return "disp_gamma0"; case 9: return "disp_postmask0"; case 10: return "disp_dither0"; case 11: return "disp_cm0"; case 12: return "spr0"; case 13: return "disp_dsc_wrap0"; case 14: return "dsi0"; case 15: return "disp_wdma0"; case 16: return "disp_pwm0"; case 17: return "disp_ovl1_2l"; case 18: return "disp_ufbc_wdma0"; default: return "mutex-unknown"; } } static char *ddp_get_mutex_module0_name_mt6833(unsigned int bit) { switch (bit) { case 0: return "disp_ovl0"; case 1: return "disp_ovl0_2l"; case 2: return "disp_rdma0"; case 3: return "disp_rsz0"; case 4: return "disp_color0"; case 5: return "disp_ccorr0"; case 7: return "disp_aal0"; case 8: return "disp_gamma0"; case 9: return "disp_postmask0"; case 10: return "disp_dither0"; case 14: return "dsi0"; case 15: return "disp_wdma0"; case 16: return "disp_pwm0"; default: return "mutex-unknown"; } } static char *ddp_get_mutex_module0_name_mt6781(unsigned int bit) { switch (bit) { case 0: return "disp_ovl0"; case 1: return "disp_ovl0_2l"; case 2: return "disp_rdma0"; case 3: return "disp_rsz0"; case 4: return "disp_color0"; case 5: return "disp_ccorr0"; case 7: return "disp_aal0"; case 8: return "disp_gamma0"; case 9: return "disp_postmask0"; case 10: return "disp_dither0"; case 13: return "disp_dsc_wrap0"; case 14: return "dsi0"; case 15: return "disp_wdma0"; case 16: return "disp_pwm0"; default: return "mutex-unknown"; } } char *mtk_ddp_get_mutex_sof_name_mt6885(unsigned int regval) { switch (regval) { case MUTEX_SOF_SINGLE_MODE: return "single"; case MUTEX_SOF_DSI0: return "dsi0"; case MUTEX_SOF_DPI0: return "dpi"; default: DDPDUMP("%s, unknown reg=%d\n", __func__, regval); return "unknown"; } } char *mtk_ddp_get_mutex_sof_name_mt6873(unsigned int regval) { switch (regval) { case MUTEX_SOF_SINGLE_MODE: return "single"; case MUTEX_SOF_DSI0: return "dsi0"; case MUTEX_SOF_DPI0: return "dpi"; default: DDPDUMP("%s, unknown reg=%d\n", __func__, regval); return "unknown"; } } char *mtk_ddp_get_mutex_sof_name_mt6853(unsigned int regval) { switch (regval) { case MUTEX_SOF_SINGLE_MODE: return "single"; case MUTEX_SOF_DSI0: return "dsi0"; default: DDPDUMP("%s, unknown reg=%d\n", __func__, regval); return "unknown"; } } char *mtk_ddp_get_mutex_sof_name_mt6877(unsigned int regval) { switch (regval) { case MUTEX_SOF_SINGLE_MODE: return "single"; case MUTEX_SOF_DSI0: return "dsi0"; default: DDPDUMP("%s, unknown reg=%d\n", __func__, regval); return "unknown"; } } char *mtk_ddp_get_mutex_sof_name_mt6833(unsigned int regval) { switch (regval) { case MUTEX_SOF_SINGLE_MODE: return "single"; case MUTEX_SOF_DSI0: return "dsi0"; default: DDPDUMP("%s, unknown reg=%d\n", __func__, regval); return "unknown"; } } char *mtk_ddp_get_mutex_sof_name_mt6781(unsigned int regval) { switch (regval) { case MUTEX_SOF_SINGLE_MODE: return "single"; case MUTEX_SOF_DSI0: return "dsi0"; default: DDPDUMP("%s, unknown reg=%d\n", __func__, regval); return "unknown"; } } static char *ddp_clock_0_mt6885(int bit) { switch (bit) { case 0: return "rsz0, "; case 1: return "rsz1, "; case 2: return "ovl0, "; case 3: return "inline_rotate, "; case 4: return "mdp_tdshp4, "; case 5: return "mdp_tdshp5, "; case 6: return "mdp_aal4, "; case 7: return "mdp_aal5 "; case 8: return "mdp_hdr4, "; case 9: return "mdp_hdr5, "; case 10: return "mdp_rsz4, "; case 11: return "mdp_rsz5, "; case 12: return "mdp_rdma4, "; case 13: return "mdp_rdma5, "; case 16: return "ovl0_2l, "; case 17: return "ovl1_2l, "; case 18: return "ovl2_2l, "; case 19: return "mutex, "; case 20: return "ovl1, "; case 21: return "ovl3_2l, "; case 22: return "ccorr0, "; case 23: return "ccorr1, "; case 24: return "color0, "; case 25: return "color1, "; case 26: return "postmask0, "; case 27: return "postmask1, "; case 28: return "dither0, "; case 29: return "dither1, "; case 30: return "dsi0, "; case 31: return "dsi1, "; default: break; } return NULL; } static char *ddp_clock_1_mt6885(int bit) { switch (bit) { case 0: return "gamma0, "; case 1: return "gamma1, "; case 2: return "aal0, "; case 3: return "aal1, "; case 4: return "wdma0, "; case 5: return "wdma1, "; case 8: return "rdma0, "; case 9: return "rdma1, "; case 10: return "rdma4, "; case 11: return "rdma5, "; case 12: return "dsc, "; case 13: return "dp, "; case 14: return "merge0, "; case 15: return "merge1, "; case 19: return "smi_common, "; case 23: return "smi_gals, "; case 27: return "smi_infra, "; case 31: return "smi_iommu, "; default: break; } return NULL; } static char *ddp_clock_0_mt6873(int bit) { switch (bit) { case 0: return "disp_mutex0, "; case 1: return "dispsys_config, "; case 2: return "disp_ovl0, "; case 3: return "disp_rdma0, "; case 4: return "disp_ovl0_2l, "; case 5: return "disp_wdma0, "; case 6: return "disp_ufbc_wdma0, "; case 7: return "disp_rsz0, "; case 8: return "disp_aal0, "; case 9: return "disp_ccorr0, "; case 10: return "disp_dither0, "; case 11: return "smi_infra, "; case 12: return "disp_gamma0, "; case 13: return "disp_postmask0, "; case 14: return "disp_dsc_wrap0, "; case 15: return "dsi0, "; case 16: return "disp_color0, "; case 17: return "smi_common, "; case 18: return "disp_fake_eng0, "; case 19: return "disp_fake_eng1, "; case 20: return "mdp_tdshp4, "; case 21: return "mdp_rsz4, "; case 22: return "mdp_aal4, "; case 23: return "mdp_hdr4, "; case 24: return "mdp_rdma4, "; case 25: return "mdp_color4, "; case 26: return "disp_y2r0, "; case 27: return "smi_gals, "; case 28: return "disp_ovl2_2l, "; case 29: return "disp_rdma4, "; case 30: return "disp_dpi0, "; default: return NULL; } } static char *ddp_clock_1_mt6873(int bit) { switch (bit) { case 0: return "smi_iommu, "; default: return NULL; } } static char *ddp_clock_0_mt6853(int bit) { switch (bit) { case 0: return "disp_mutex0, "; case 1: return "dispsys_config, "; case 2: return "disp_ovl0, "; case 3: return "disp_rdma0, "; case 4: return "disp_ovl0_2l, "; case 5: return "disp_wdma0, "; case 6: return "disp_ccorr1, "; case 7: return "disp_rsz0, "; case 8: return "disp_aal0, "; case 9: return "disp_ccorr0, "; case 10: return "disp_color0, "; case 11: return "smi_infra, "; case 12: return "disp_dsc_wrap0, "; case 13: return "disp_gamma0, "; case 14: return "disp_postmask0, "; case 15: return "spr0, "; case 16: return "disp_dither0, "; case 17: return "smi_common, "; case 18: return "disp_cm0, "; case 19: return "dsi0, "; case 20: return "disp_fake_eng0, "; case 21: return "disp_fake_eng1, "; case 22: return "smi_gals, "; case 23: return "reserve, "; case 24: return "smi_iommu, "; default: return NULL; } } static char *ddp_clock_0_mt6877(int bit) { switch (bit) { case 0: return "disp_mutex0, "; case 1: return "dispsys_config, "; case 2: return "disp_ovl0, "; case 3: return "disp_rdma0, "; case 4: return "disp_ovl0_2l, "; case 5: return "disp_wdma0, "; case 6: return "disp_ccorr1, "; case 7: return "disp_rsz0, "; case 8: return "disp_aal0, "; case 9: return "disp_ccorr0, "; case 10: return "disp_color0, "; case 11: return "smi_infra, "; case 12: return "reserve, "; case 13: return "disp_gamma0, "; case 14: return "disp_postmask0, "; case 15: return "spr0, "; case 16: return "disp_dither0, "; case 17: return "smi_common, "; case 18: return "disp_cm0, "; case 19: return "dsi0, "; case 20: return "disp_fake_eng0, "; case 21: return "disp_fake_eng1, "; case 22: return "smi_gals, "; case 23: return "disp_dsc_wrap0, "; case 24: return "smi_iommu, "; case 26: return "disp_ovl1_2l, "; case 27: return "disp_ufbc_wdma, "; default: return NULL; } } static char *ddp_clock_0_mt6833(int bit) { switch (bit) { case 0: return "disp_mutex0, "; case 1: return "apb_bus, "; case 2: return "disp_ovl0, "; case 3: return "disp_rdma0, "; case 4: return "disp_ovl0_2l, "; case 5: return "disp_wdma0, "; case 6: return "reserve, "; case 7: return "disp_rsz0, "; case 8: return "disp_aal0, "; case 9: return "disp_ccorr0, "; case 10: return "disp_color0, "; case 11: return "smi_infra, "; case 12: return "reserve, "; case 13: return "disp_gama0, "; case 14: return "disp_postmask0, "; case 15: return "reserve, "; case 16: return "disp_dither0, "; case 17: return "smi_common, "; case 18: return "reserve, "; case 19: return "dsi0, "; case 20: return "disp_fake_eng0, "; case 21: return "disp_fake_eng1, "; case 22: return "smi_gals, "; case 23: return "reserve, "; case 24: return "smi_iommu, "; default: return NULL; } } static char *ddp_clock_0_mt6781(int bit) { switch (bit) { case 0: return "disp_mutex0, "; case 1: return "apb_bus, "; case 2: return "disp_ovl0, "; case 3: return "disp_rdma0, "; case 4: return "disp_ovl0_2l, "; case 5: return "disp_wdma0, "; case 6: return "reserve, "; case 7: return "disp_rsz0, "; case 8: return "disp_aal0, "; case 9: return "disp_ccorr0, "; case 10: return "disp_color0, "; case 11: return "smi_infra, "; case 12: return "disp_dsc_wrap0 "; case 13: return "disp_gama0, "; case 14: return "disp_postmask0, "; case 15: return "reserve, "; case 16: return "disp_dither0, "; case 17: return "smi_common, "; case 18: return "reserve, "; case 19: return "dsi0, "; case 20: return "disp_fake_eng0, "; case 21: return "disp_fake_eng1, "; case 22: return "smi_gals, "; case 23: return "reserve, "; case 24: return "smi_iommu, "; default: return NULL; } } char *mtk_ddp_get_mutex_sof_name(unsigned int regval) { switch (regval) { case MUTEX_SOF_SINGLE_MODE: return "single"; case MUTEX_SOF_DSI0: return "dsi0"; case MUTEX_SOF_DPI0: return "dpi"; default: DDPDUMP("%s, unknown reg=%d\n", __func__, regval); return "unknown"; } } static int mtk_ddp_mout_en_MT6885(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_OVL0) { *addr = MT6885_MMSYS_OVL_CON; value = DISP_OVL0_2L_TO_DISP_OVL0_2L_OVL1_OVL1_2L_BGOUT_SEL; } else if (cur == DDP_COMPONENT_OVL1_2L && next == DDP_COMPONENT_OVL1) { *addr = MT6885_MMSYS_OVL_CON; value = DISP_OVL0_2L_TO_DISP_OVL1_2L_OVL1_OVL1_2L_BGOUT_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_OVL0_2L_VIRTUAL0) { *addr = MT6885_MMSYS_OVL_CON; value = DISP_OVL0_2L_TO_DISP_OVL0_2L_BLENDOUT_SOUT; } else if (cur == DDP_COMPONENT_OVL1_2L && next == DDP_COMPONENT_OVL1_2L_VIRTUAL0) { *addr = MT6885_MMSYS_OVL_CON; value = DISP_OVL1_2L_TO_DISP_OVL1_2L_BLENDOUT_SOUT; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL0_VIRTUAL0) { *addr = MT6885_MMSYS_OVL_CON; value = DISP_OVL0_TO_DISP_OVL0_BLENDOUT_SOUT; } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_OVL1_VIRTUAL0) { *addr = MT6885_MMSYS_OVL_CON; value = DISP_OVL1_TO_DISP_OVL1_BLENDOUT_SOUT; } else if (cur == DDP_COMPONENT_OVL0_VIRTUAL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6885_DISP_TOVL0_OUT1_MOUT_EN; value = DISP_TOVL0_OUT1_MOUT_EN_TO_DISP_RDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL1_VIRTUAL0 && next == DDP_COMPONENT_RDMA1) { *addr = MT6885_DISP_TOVL1_OUT1_MOUT_EN; value = DISP_TOVL1_OUT1_MOUT_EN_TO_DISP_RDMA1_SEL; } else if (cur == DDP_COMPONENT_OVL0_VIRTUAL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6885_DISP_TOVL0_OUT1_MOUT_EN; value = DISP_TOVL0_OUT1_MOUT_EN_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL1_VIRTUAL0 && next == DDP_COMPONENT_WDMA1) { *addr = MT6885_DISP_TOVL1_OUT1_MOUT_EN; value = DISP_TOVL1_OUT1_MOUT_EN_TO_DISP_WDMA1_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L_VIRTUAL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6885_DISP_TOVL0_OUT0_MOUT_EN; value = DISP_TOVL0_OUT0_MOUT_TO_DISP_RSZ0_SEL; } else if (cur == DDP_COMPONENT_OVL1_2L_VIRTUAL0 && next == DDP_COMPONENT_RSZ1) { *addr = MT6885_DISP_TOVL1_OUT0_MOUT_EN; value = DISP_TOVL1_OUT0_MOUT_TO_DISP_RSZ1_SEL; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6885_DISP_RSZ0_MOUT_EN; value = DISP_RSZ0_MOUT_EN_TO_DISP_RDMA2_RSZ0_RSZ1_SEL; } else if (cur == DDP_COMPONENT_RSZ1 && next == DDP_COMPONENT_OVL1) { *addr = MT6885_DISP_RSZ1_MOUT_EN; value = DISP_RSZ1_MOUT_EN_TO_DISP_RDMA3_SOUT; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_DSI0) { *addr = MT6885_DISP_DITHER0_MOUT_EN; value = DISP_DITHER0_MOUT_EN_TO_DSI0_SEL; } else if (cur == DDP_COMPONENT_DITHER1 && next == DDP_COMPONENT_DSI1) { *addr = MT6885_DISP_DITHER1_MOUT_EN; value = DISP_DITHER1_MOUT_EN_TO_DSI1_SEL; } else if (cur == DDP_COMPONENT_OVL2_2L && next == DDP_COMPONENT_RDMA4) { *addr = MT6885_DISP_OVL2_2L_OUT0_MOUT; value = DISP_OVL2_2L_OUT0_MOUT_TO_DISP_RDMA4; } else if (cur == DDP_COMPONENT_OVL2_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6885_DISP_OVL2_2L_OUT0_MOUT; value = DISP_OVL2_2L_OUT0_MOUT_TO_DISP_WDMA0; } else if (cur == DDP_COMPONENT_OVL3_2L && next == DDP_COMPONENT_RDMA5) { *addr = MT6885_DISP_OVL3_2L_OUT0_MOUT; value = DISP_OVL3_2L_OUT0_MOUT_TO_DISP_RDMA5; } else if (cur == DDP_COMPONENT_OVL3_2L && next == DDP_COMPONENT_WDMA1) { *addr = MT6885_DISP_OVL3_2L_OUT0_MOUT; value = DISP_OVL3_2L_OUT0_MOUT_TO_DISP_WDMA1; } else if (cur == DDP_COMPONENT_OVL1_2L_VIRTUAL0 && next == DDP_COMPONENT_WDMA1) { *addr = MT6885_DISP_TOVL1_OUT0_MOUT_EN; value = DISP_TOVL1_OUT0_MOUT_TO_DISP_WDMA1_SEL; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6885_DISP_DITHER0_MOUT_EN; value = DISP_DITHER0_MOUT_EN_TO_WDMA0_SEL; } else if (cur == DDP_COMPONENT_DITHER1 && next == DDP_COMPONENT_WDMA1) { *addr = MT6885_DISP_DITHER1_MOUT_EN; value = DISP_DITHER1_MOUT_EN_TO_WDMA1_SEL; } else { value = -1; } return value; } static int mtk_ddp_mout_en_1_MT6885(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; if (cur == DDP_COMPONENT_OVL3_2L && next == DDP_COMPONENT_WDMA1) { *addr = MT6885_MMSYS_OVL_CON; value = DISP_OVL3_2L_TO_DISP_RDMA5; } else { value = -1; } return value; } static int mtk_ddp_sel_in_MT6885(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_OVL0) { *addr = MT6885_DISP_OVL0_2L_OVL1_OVL1_2L_BGOUT_SEL; value = DISP_OVL0_2L_OVL1_OVL1_2L_BGOUT_SEL_FROM_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_OVL0_2L_VIRTUAL0) { *addr = MT6885_DISP_TOVL0_OUT0_SEL_IN; value = DISP_TOVL0_OUT0_SEL_IN_FROM_DISP_OVL0_2L_BLENDOUT_SOUT; } else if (cur == DDP_COMPONENT_OVL1_2L && next == DDP_COMPONENT_OVL1_2L_VIRTUAL0) { *addr = MT6885_DISP_TOVL1_OUT0_SEL_IN; value = DISP_TOVL1_OUT0_SEL_IN_FROM_DISP_OVL1_2L_BLENDOUT_SOUT; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL0_VIRTUAL0) { *addr = MT6885_DISP_TOVL0_OUT1_SEL_IN; value = DISP_TOVL0_OUT1_SEL_IN_FROM_DISP_OVL0_BLENDOUT_SOUT; } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_OVL1_VIRTUAL0) { *addr = MT6885_DISP_TOVL1_OUT1_SEL_IN; value = DISP_TOVL1_OUT1_SEL_IN_FROM_DISP_OVL1_BLENDOUT_SOUT; } else if (cur == DDP_COMPONENT_OVL0_2L_VIRTUAL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6885_DISP_RSZ0_SEL_IN; value = DISP_RSZ0_SEL_IN_FROM_DISP_TOVL0_OUT0_MOUT; } else if (cur == DDP_COMPONENT_OVL1_2L_VIRTUAL0 && next == DDP_COMPONENT_RSZ1) { *addr = MT6885_DISP_RSZ1_SEL_IN; value = DISP_RSZ1_SEL_IN_FROM_DISP_TOVL1_OUT0_MOUT; } else if (cur == DDP_COMPONENT_OVL0_VIRTUAL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6885_DISP_RDMA0_SEL_IN; value = DISP_RDMA0_SEL_IN_FROM_DISP_TOVL0_OUT1_MOUT; } else if (cur == DDP_COMPONENT_OVL1_VIRTUAL0 && next == DDP_COMPONENT_RDMA1) { *addr = MT6885_DISP_RDMA1_SEL_IN; value = DISP_RDMA1_SEL_IN_FROM_DISP_TOVL1_OUT1_MOUT; } else if (cur == DDP_COMPONENT_OVL0_VIRTUAL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6885_DISP_WDMA0_SEL_IN; value = MT6885_WDMA0_SEL_IN_FROM_DISP_TOVL0_OUT1_MOUT; } else if (cur == DDP_COMPONENT_OVL1_VIRTUAL0 && next == DDP_COMPONENT_WDMA1) { *addr = MT6885_DISP_WDMA1_SEL_IN; value = MT6885_WDMA1_SEL_IN_FROM_DISP_TOVL1_OUT1_MOUT; } else if (cur == DDP_COMPONENT_OVL1_2L_VIRTUAL0 && next == DDP_COMPONENT_WDMA1) { *addr = MT6885_DISP_WDMA1_SEL_IN; value = MT6885_WDMA1_SEL_IN_FROM_DISP_TOVL1_OUT0_MOUT; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6885_DISP_RDMA2_RSZ0_RSZ1_SEL_IN; value = DISP_RDMA2_RSZ0_RSZ1_SEL_IN_FROM_DISP_RSZ0_MOUT; } else if (cur == DDP_COMPONENT_RSZ1 && next == DDP_COMPONENT_OVL0) { *addr = MT6885_DISP_RDMA2_RSZ0_RSZ1_SEL_IN; value = DISP_RDMA2_RSZ0_RSZ1_SEL_IN_FROM_DISP_RSZ1_MOUT; } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_RDMA0_VIRTUAL0) { *addr = MT6885_DISP_RDMA0_RSZ0_SEL_IN; value = DISP_RDMA0_RSZ0_SEL_IN_FROM_DISP_RDMA0_SOUT; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_RDMA1_VIRTUAL0) { *addr = MT6885_DISP_RDMA1_RSZ1_SEL_IN; value = DISP_RDMA0_RSZ0_SEL_IN_FROM_DISP_RDMA0_SOUT; } else if (cur == DDP_COMPONENT_COLOR0 && next == DDP_COMPONENT_CCORR0) { *addr = MT6885_DISP_COLOR0_OUT_SEL_IN; value = DISP_COLOR0_OUT_SEL_IN_FROM_DISP_COLOR0; } else if (cur == DDP_COMPONENT_COLOR1 && next == DDP_COMPONENT_CCORR1) { *addr = MT6885_DISP_COLOR1_OUT_SEL_IN; value = DISP_COLOR1_OUT_SEL_IN_FROM_DISP_COLOR1; } else if (cur == DDP_COMPONENT_CCORR0 && next == DDP_COMPONENT_AAL0) { *addr = MT6885_DISP_AAL0_SEL_IN; value = DISP_AAL0_SEL_IN_FROM_DISP_CCORR0_SOUT; } else if (cur == DDP_COMPONENT_DMDP_AAL0 && next == DDP_COMPONENT_AAL0) { *addr = MT6885_DISP_AAL0_SEL_IN; value = DISP_AAL0_SEL_IN_FROM_DISP_MDP_AAL4_SOUT; } else if (cur == DDP_COMPONENT_CCORR1 && next == DDP_COMPONENT_AAL1) { *addr = MT6885_DISP_AAL1_SEL_IN; value = DISP_AAL1_SEL_IN_FROM_DISP_CCORR1_SOUT; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_DSI0) { *addr = MT6885_DSI0_SEL_IN; value = DSI0_SEL_IN_FROM_DISP_DITHER0_MOUT; } else if (cur == DDP_COMPONENT_DITHER1 && next == DDP_COMPONENT_DSI1) { *addr = MT6885_DSI1_SEL_IN; value = DSI1_SEL_IN_FROM_DISP_DITHER1_MOUT; } else if (cur == DDP_COMPONENT_OVL2_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6885_DISP_WDMA0_SEL_IN; value = MT6885_WDMA0_SEL_IN_FROM_DISP_TOVL2_2L_OUT0_MOUT; } else if (cur == DDP_COMPONENT_OVL3_2L && next == DDP_COMPONENT_WDMA1) { *addr = MT6885_DISP_WDMA1_SEL_IN; value = MT6885_WDMA1_SEL_IN_FROM_DISP_TOVL3_2L_OUT0_MOUT; } else if (cur == DDP_COMPONENT_CCORR0 && next == DDP_COMPONENT_DMDP_AAL0) { *addr = MT6885_DISP_MDP_AAL4_SEL_IN; value = DISP_MDP_AAL4_SEL_IN_FROM_DISP_CCORR0_SOUT; } else if (cur == DDP_COMPONENT_DMDP_AAL1 && next == DDP_COMPONENT_AAL1) { *addr = MT6885_DISP_AAL1_SEL_IN; value = DISP_AAL1_SEL_IN_FROM_DISP_MDP_AAL5_SOUT; } else if (cur == DDP_COMPONENT_CCORR1 && next == DDP_COMPONENT_DMDP_AAL1) { *addr = MT6885_DISP_MDP_AAL5_SEL_IN; value = DISP_MDP_AAL5_SEL_IN_FROM_DISP_CCORR1_SOUT; } else if (cur == DDP_COMPONENT_RDMA4 && next == DDP_COMPONENT_DP_INTF0) { *addr = MT6885_DISP_DP_WRAP_SEL_IN; value = DISP_DISP_RDMA4_SOUT_TO_DISP_DP_INTF0; } else if (cur == DDP_COMPONENT_RDMA4 && next == DDP_COMPONENT_DSC0) { *addr = MT6885_DISP_RDMA4_PQ0_MERGE0_SEL_IN; value = DISP_RDMA4_SOUT_TO_DISP_RDMA4_PQ0_MERGE0_SEL; } else if (cur == DDP_COMPONENT_RDMA5 && next == DDP_COMPONENT_DSC0) { *addr = MT6885_DISP_RDMA4_PQ0_MERGE0_SEL_IN; value = DISP_RDMA4_SOUT_TO_DISP_RDMA4_PQ0_MERGE0_SEL; } else if (cur == DDP_COMPONENT_OVL1_2L_VIRTUAL0 && next == DDP_COMPONENT_WDMA1) { *addr = MT6885_DISP_WDMA1_SEL_IN; value = MT6885_WDMA1_SEL_IN_FROM_DISP_TOVL3_2L_OUT0_MOUT; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6885_DISP_WDMA0_SEL_IN; value = MT6885_WDMA0_SEL_IN_FROM_DISP_DITHER0_MOUT; } else if (cur == DDP_COMPONENT_DITHER1 && next == DDP_COMPONENT_WDMA1) { *addr = MT6885_DISP_WDMA1_SEL_IN; value = MT6885_WDMA1_SEL_IN_FROM_DISP_DITHER1_MOUT; } else { value = -1; } return value; } static int mtk_ddp_sout_sel_MT6885(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL0_VIRTUAL0) { *addr = MT6885_DISP_OVL0_BLENDOUT_SOUT_SEL; value = DISP_OVL0_BLENDOUT_SOUT_SEL_TO_DISP_TOVL0_OUT1_SEL; } else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_OVL1_VIRTUAL0) { *addr = MT6885_DISP_OVL1_BLENDOUT_SOUT_SEL; value = DISP_OVL1_BLENDOUT_SOUT_SEL_TO_DISP_TOVL1_OUT1_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_OVL0_2L_VIRTUAL0) { *addr = MT6885_DISP_OVL0_2L_BLENDOUT_SOUT_SEL; value = DISP_OVL0_2L_BLENDOUT_SOUT_SEL_TO_DISP_TOVL0_OUT0_SEL; } else if (cur == DDP_COMPONENT_OVL1_2L && next == DDP_COMPONENT_OVL1_2L_VIRTUAL0) { *addr = MT6885_DISP_OVL1_2L_BLENDOUT_SOUT_SEL; value = DISP_OVL1_2L_BLENDOUT_SOUT_SEL_TO_DISP_TOVL1_OUT0_SEL; } else if (cur == DDP_COMPONENT_OVL1_2L && next == DDP_COMPONENT_OVL1) { *addr = MT6885_DISP_OVL1_2L_BGOUT_SOUT_SEL; value = DISP_OVL1_2L_BGOUT_SOUT_SEL_TO_DISP_OVL1; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6885_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL; value = DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL_TO_DISP_OVL0; } else if (cur == DDP_COMPONENT_RSZ1 && next == DDP_COMPONENT_OVL1) { *addr = MT6885_DISP_RDMA3_SOUT_SEL; value = DISP_RDMA3_SOUT_SEL_TO_DISP_OVL1; } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_RDMA0_VIRTUAL0) { *addr = MT6885_DISP_RDMA0_SOUT_SEL; value = DISP_RDMA0_SOUT_SEL_TO_DISP_RDMA0_RSZ0_SEL; } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_RDMA1_VIRTUAL0) { *addr = MT6885_DISP_RDMA1_SOUT_SEL; value = DISP_RDMA1_SOUT_SEL_TO_DISP_RDMA1_RSZ1_SEL; } else if (cur == DDP_COMPONENT_RDMA0_VIRTUAL0 && next == DDP_COMPONENT_DSI0) { *addr = MT6885_DISP_RDMA0_RSZ0_SOUT_SEL; value = DISP_RDMA0_RSZ0_SOUT_SEL_TO_DSI0_SEL_IN; } else if (cur == DDP_COMPONENT_RDMA1_VIRTUAL0 && next == DDP_COMPONENT_DSI1) { *addr = MT6885_DISP_RDMA1_RSZ1_SOUT_SEL; value = DISP_RDMA1_RSZ1_SOUT_SEL_TO_DSI1_SEL_IN; } else if (cur == DDP_COMPONENT_RDMA0_VIRTUAL0 && next == DDP_COMPONENT_COLOR0) { *addr = MT6885_DISP_RDMA0_RSZ0_SOUT_SEL; value = DISP_RDMA0_RSZ0_SOUT_SEL_TO_DISP_COLOR0; } else if (cur == DDP_COMPONENT_RDMA1_VIRTUAL0 && next == DDP_COMPONENT_COLOR1) { *addr = MT6885_DISP_RDMA1_RSZ1_SOUT_SEL; value = DISP_RDMA1_RSZ1_SOUT_SEL_TO_DISP_COLOR1; } else if (cur == DDP_COMPONENT_CCORR0 && next == DDP_COMPONENT_AAL0) { *addr = MT6885_DISP_CCORR0_SOUT_SEL; value = DISP_CCORR0_SOUT_SEL_TO_DISP_AAL0_SEL; } else if (cur == DDP_COMPONENT_CCORR0 && next == DDP_COMPONENT_DMDP_AAL0) { *addr = MT6885_DISP_CCORR0_SOUT_SEL; value = DISP_CCORR0_SOUT_SEL_TO_DMDP_AAL0_SEL; } else if (cur == DDP_COMPONENT_CCORR1 && next == DDP_COMPONENT_AAL1) { *addr = MT6885_DISP_CCORR1_SOUT_SEL; value = DISP_CCORR1_SOUT_SEL_TO_DISP_AAL1_SEL; } else if (cur == DDP_COMPONENT_DMDP_AAL0 && next == DDP_COMPONENT_AAL0) { *addr = MT6885_DISP_MDP_AAL4_SOUT_SEL; value = DISP_MDP_AAL4_SOUT_SEL_TO_DISP_AAL0_SEL; } else if (cur == DDP_COMPONENT_CCORR1 && next == DDP_COMPONENT_DMDP_AAL1) { *addr = MT6885_DISP_CCORR1_SOUT_SEL; value = DISP_CCORR1_SOUT_SEL_TO_DISP_MDP_AAL5_SEL; } else if (cur == DDP_COMPONENT_DMDP_AAL1 && next == DDP_COMPONENT_AAL1) { *addr = MT6885_DISP_MDP_AAL5_SOUT_SEL; value = DISP_MDP_AAL5_SOUT_SEL_TO_DISP_AAL1_SEL; } else if (cur == DDP_COMPONENT_RDMA4 && next == DDP_COMPONENT_MERGE1) { *addr = MT6885_DISP_RDMA4_SOUT; value = DISP_RDMA4_TO_DISP_MERGE1; } else if (cur == DDP_COMPONENT_RDMA4 && next == DDP_COMPONENT_RDMA0_VIRTUAL0) { *addr = MT6885_DISP_RDMA4_SOUT; value = DISP_RDMA4_TO_DISP_RDMA4_PQ0_MERGE0_SEL; } else if (cur == DDP_COMPONENT_RDMA4 && next == DDP_COMPONENT_DP_INTF0) { *addr = MT6885_DISP_RDMA4_SOUT; value = DISP_RDMA4_TO_DISP_DP_WRAP_SEL; } else if (cur == DDP_COMPONENT_RDMA5 && next == DDP_COMPONENT_MERGE1) { *addr = MT6885_DISP_RDMA5_SOUT; value = DISP_RDMA5_TO_DISP_MERGE1; } else if (cur == DDP_COMPONENT_RDMA5 && next == DDP_COMPONENT_DSC0) { *addr = MT6885_DISP_RDMA5_SOUT; value = DISP_RDMA5_TO_DISP_RDMA5_PQ1_SEL; } else if (cur == DDP_COMPONENT_DSC0 && next == DDP_COMPONENT_DP_INTF0) { *addr = MT6885_DISP_DSC_WRAP_SOUT_SEL; value = DISP_DSC_WRAP_SOUT_TO_DISP_DP_WRAP_SEL; } else { value = -1; } return value; } static int mtk_ddp_mout_en_MT6873(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*DISP_TOVL0_OUT0_MOUT*/ if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = MOUT_TO_DISP_RDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6873_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = MOUT_TO_DISP_RSZ0_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = MOUT_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_UFBC_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = MOUT_TO_DISP_UFBC_WDMA0_SEL; /*DISP_TOVL0_OUT1_MOUT*/ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = MOUT_TO_DISP_RDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6873_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = MOUT_TO_DISP_RSZ0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = MOUT_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_UFBC_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = MOUT_TO_DISP_UFBC_WDMA0_SEL; /*DISP_OVL2_2L_OUT0_MOUT*/ } else if (cur == DDP_COMPONENT_OVL2_2L && next == DDP_COMPONENT_RDMA4) { *addr = MT6873_DISP_REG_CONFIG_DISP_OVL2_2L_OUT0_MOUT_EN; value = MOUT_OVL2_2L_TO_DISP_RDMA4; } else if (cur == DDP_COMPONENT_OVL2_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_OVL2_2L_OUT0_MOUT_EN; value = MOUT_OVL2_2L_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL2_2L && next == DDP_COMPONENT_UFBC_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_OVL2_2L_OUT0_MOUT_EN; value = MOUT_OVL2_2L_TO_DISP_UFBC_WDMA0_SEL; /*DISP_RSZ0_MOUT*/ } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN; value = MOUT_RSZ0_TO_DISP_RDMA0_SEL; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN; value = MOUT_RSZ0_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_UFBC_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN; value = MOUT_RSZ0_TO_DISP_UFBC_WDMA0_SEL; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6873_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN; value = MOUT_RSZ0_TO_DISP_RDMA2_RSZ0_RSZ1_SOUT; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0_2L) { *addr = MT6873_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN; value = MOUT_RSZ0_TO_DISP_RDMA2_RSZ0_RSZ1_SOUT; /*DISP_DITHER0_MOUT*/ } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_DSI0) { *addr = MT6873_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = MOUT_DITHER0_TO_DISP_DSI0_SEL; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_DSC0) { *addr = MT6873_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = MOUT_DITHER0_TO_DISP_DSC_WRAP0; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = MOUT_DITHER0_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_UFBC_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = MOUT_DITHER0_TO_DISP_UFBC_WDMA0_SEL; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_sel_in_MT6873(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*DISP_OVL0_2L_UFOD_SEL*/ if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6873_DISP_REG_CONFIG_DISP_OVL0_2L_UFOD_SEL_IN; value = SEL_IN_FROM_DISP_RDMA2_RSZ0_RSZ1_SOUT; /*DISP_OVL0_UFOD_SEL*/ } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0_2L) { *addr = MT6873_DISP_REG_CONFIG_DISP_OVL0_UFOD_SEL_IN; value = SEL_IN_FROM_DISP_RDMA2_RSZ0_RSZ1_SOUT; /*DISP_RDMA0_SEL*/ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN; value = SEL_IN_FROM_DISP_OVL0; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN; value = SEL_IN_FROM_DISP_RSZ0; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN; value = SEL_IN_FROM_DISP_OVL0_2L; /*DISP_AAL0_SEL*/ } else if (cur == DDP_COMPONENT_CCORR0 && next == DDP_COMPONENT_AAL0) { *addr = MT6873_DISP_REG_CONFIG_DISP_AAL0_SEL_IN; value = SEL_IN_FROM_DISP_CCORR0; } else if (cur == DDP_COMPONENT_DMDP_AAL0 && next == DDP_COMPONENT_AAL0) { *addr = MT6873_DISP_REG_CONFIG_DISP_AAL0_SEL_IN; value = SEL_IN_FROM_MDP_AAL4; /*DISP_DSI0_SEL*/ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI0) { *addr = MT6873_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_RDMA0; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_DSI0) { *addr = MT6873_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_DITHER0; } else if (cur == DDP_COMPONENT_DSC0 && next == DDP_COMPONENT_DSI0) { *addr = MT6873_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_DSC0; /*DISP_WDMA0_SEL*/ } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = SEL_IN_WDMA_FROM_DISP_DITHER0; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = SEL_IN_WDMA_FROM_DISP_RSZ0; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = SEL_IN_WDMA_FROM_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = SEL_IN_WDMA_FROM_DISP_OVL0; } else if (cur == DDP_COMPONENT_OVL2_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = SEL_IN_WDMA_FROM_DISP_OVL2_2L; /*DISP_UFBC_WDMA0_SEL*/ } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_UFBC_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_UFBC_WDMA0_SEL_IN; value = SEL_IN_WDMA_FROM_DISP_DITHER0; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_UFBC_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_UFBC_WDMA0_SEL_IN; value = SEL_IN_WDMA_FROM_DISP_RSZ0; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_UFBC_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_UFBC_WDMA0_SEL_IN; value = SEL_IN_WDMA_FROM_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_UFBC_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_UFBC_WDMA0_SEL_IN; value = SEL_IN_WDMA_FROM_DISP_OVL0; } else if (cur == DDP_COMPONENT_OVL2_2L && next == DDP_COMPONENT_UFBC_WDMA0) { *addr = MT6873_DISP_REG_CONFIG_UFBC_WDMA0_SEL_IN; value = SEL_IN_WDMA_FROM_DISP_OVL2_2L; /*DISP_RSZ0_SEL*/ } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6873_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN; value = SEL_IN_RSZ0_FROM_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6873_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN; value = SEL_IN_RSZ0_FROM_DISP_OVL0; /*DISP_MDP_AAL4_SEL*/ } else if (cur == DDP_COMPONENT_CCORR0 && next == DDP_COMPONENT_DMDP_AAL0) { *addr = MT6873_DISP_REG_CONFIG_DISP_MDP_AAL4_SEL_IN; value = SEL_IN_PQ_AAL_FROM_DISP_CCORR0; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_sout_sel_MT6873(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*DISP_RDMA2_RSZ0_RSZ1_SOUT*/ if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0_2L) { *addr = MT6873_DISP_REG_CONFIG_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL; value = SOUT_TO_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6873_DISP_REG_CONFIG_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL; value = SOUT_TO_DISP_OVL0; /*DISP_RDMA0_RSZ0_SOUT*/ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI0) { *addr = MT6873_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL; value = SOUT_TO_DISP_DSI0; } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { *addr = MT6873_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL; value = SOUT_TO_DISP_COLOR0; /*DISP_CCORR0_SOUT*/ } else if (cur == DDP_COMPONENT_CCORR0 && next == DDP_COMPONENT_DMDP_AAL0) { *addr = MT6873_DISP_REG_CONFIG_DISP_CCORR0_SOUT_SEL; value = SOUT_TO_MDP_AAL4; } else if (cur == DDP_COMPONENT_CCORR0 && next == DDP_COMPONENT_AAL0) { *addr = MT6873_DISP_REG_CONFIG_DISP_CCORR0_SOUT_SEL; value = SOUT_TO_DISP_AAL0; /*DISP_MDP_AAL4_SOUT*/ } else if (cur == DDP_COMPONENT_DMDP_AAL0 && next == DDP_COMPONENT_AAL0) { *addr = MT6873_DISP_REG_CONFIG_DISP_MDP_AAL4_SOUT_SEL; value = SOUT_MDP_AAL4_TO_DISP_AAL0; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_ovl_bg_blend_en_MT6873(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*OVL0_2L*/ if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_OVL0) { *addr = MT6873_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BG; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6873_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RDMA0) { *addr = MT6873_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6873_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; /*OVL0*/ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL0_2L) { *addr = MT6873_MMSYS_OVL_CON; value = DISP_OVL0_GO_BG; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6873_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6873_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6873_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_mout_en_MT6853(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*DISP_TOVL0_OUT0_MOUT*/ if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = OVL0_2L_MOUT_TO_DISP_RDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = OVL0_2L_MOUT_TO_DISP_RSZ0_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = OVL0_2L_MOUT_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = OVL0_MOUT_TO_DISP_RDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = OVL0_MOUT_TO_DISP_RSZ0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = OVL0_MOUT_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6853_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN; value = RSZ0_MOUT_TO_DISP_RDMA2_RSZ0_RSZ1_SOUT; /*DISP_DITHER0_MOUT*/ } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = DITHER0_MOUT_TO_DISP_DISP_WDMA0; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_SPR0_VIRTUAL) { *addr = MT6853_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = DITHER0_MOUT_TO_DISP_DISP_BYPASS_SPR0_SEL; } else if (cur == DDP_COMPONENT_SPR0_VIRTUAL && next == DDP_COMPONENT_DSI0) { *addr = MT6853_DISP_REG_CONFIG_DISP_SPR0_MOUT_EN; value = SPR0_MOUT_TO_DISP_DSI0_SEL; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_sel_in_MT6853(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN; value = SEL_IN_RDMA0_FROM_DISP_OVL0; /*DISP_DSI0_SEL*/ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI0) { *addr = MT6853_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_RDMA0_RSZ0_SOUT; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_DSI0) { *addr = MT6853_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_SPR0_MOUT; } else if (cur == DDP_COMPONENT_DSC0 && next == DDP_COMPONENT_DSI0) { *addr = MT6853_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_DSC_WRAP0; /*DISP_WDMA0_SEL*/ } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = MT6853_WDMA0_SEL_IN_FROM_DISP_DITHER0_MOUT; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = WDMA0_SEL_IN_FROM_DISP_OVL0; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = WDMA0_SEL_IN_FROM_DISP_OVL0_2L; /*DISP_RSZ0_SEL*/ } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6853_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN; value = RSZ0_FROM_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6853_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN; value = RSZ0_FROM_DISP_OVL0; } else if (cur == DDP_COMPONENT_SPR0_VIRTUAL && next == DDP_COMPONENT_DSI0) { *addr = MT6853_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_SPR0_MOUT; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_sout_sel_MT6853(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*DISP_RDMA2_RSZ0_RSZ1_SOUT*/ if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0_2L) { *addr = MT6853_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL; value = RSZ0_SOUT_TO_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6853_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL; value = RSZ0_SOUT_TO_DISP_OVL0; /*DISP_RDMA0_RSZ0_SOUT*/ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI0) { *addr = MT6853_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL; value = SOUT_TO_DISP_DSI0_SEL; } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { *addr = MT6853_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL; value = RDMA0_SOUT_TO_DISP_COLOR0; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_ovl_bg_blend_en_MT6853(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*OVL0_2L*/ if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_OVL0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BG; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RDMA0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; /*OVL0*/ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL0_2L) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_GO_BG; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_mout_en_MT6877(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*DISP_TOVL0_OUT0_MOUT*/ if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = OVL0_2L_MOUT_TO_DISP_RDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = OVL0_2L_MOUT_TO_DISP_RSZ0_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = OVL0_2L_MOUT_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = OVL0_MOUT_TO_DISP_RDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = OVL0_MOUT_TO_DISP_RSZ0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = OVL0_MOUT_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6853_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN; value = RSZ0_MOUT_TO_DISP_RDMA2_RSZ0_RSZ1_SOUT; /*DISP_DITHER0_MOUT*/ } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_SPR0_VIRTUAL) { *addr = MT6853_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = DITHER0_MOUT_TO_DISP_DISP_BYPASS_SPR0_SEL; } else if (cur == DDP_COMPONENT_SPR0_VIRTUAL && next == DDP_COMPONENT_DSI0) { *addr = MT6853_DISP_REG_CONFIG_DISP_SPR0_MOUT_EN; value = SPR0_MOUT_TO_DISP_DSI0_SEL; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_sel_in_MT6877(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN; value = SEL_IN_RDMA0_FROM_DISP_OVL0; /*DISP_DSI0_SEL*/ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI0) { *addr = MT6853_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_RDMA0_RSZ0_SOUT; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_DSI0) { *addr = MT6853_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_SPR0_MOUT; } else if (cur == DDP_COMPONENT_DSC0 && next == DDP_COMPONENT_DSI0) { *addr = MT6853_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_DSC_WRAP0; /*DISP_WDMA0_SEL*/ } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = WDMA0_SEL_IN_FROM_DISP_SPR0_MOUT; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = WDMA0_SEL_IN_FROM_DISP_OVL0; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = WDMA0_SEL_IN_FROM_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_OVL1_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = MT6877_WDMA0_SEL_IN_FROM_DISP_OVL1_2L; /*DISP_RSZ0_SEL*/ } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6853_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN; value = RSZ0_FROM_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6853_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN; value = RSZ0_FROM_DISP_OVL0; } else if (cur == DDP_COMPONENT_SPR0_VIRTUAL && next == DDP_COMPONENT_DSI0) { *addr = MT6853_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_SPR0_MOUT; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_sout_sel_MT6877(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*DISP_RDMA2_RSZ0_RSZ1_SOUT*/ if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0_2L) { *addr = MT6853_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL; value = RSZ0_SOUT_TO_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6853_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL; value = RSZ0_SOUT_TO_DISP_OVL0; /*DISP_RDMA0_RSZ0_SOUT*/ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI0) { *addr = MT6853_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL; value = SOUT_TO_DISP_DSI0_SEL; } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { *addr = MT6853_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL; value = RDMA0_SOUT_TO_DISP_COLOR0; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_ovl_bg_blend_en_MT6877(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*OVL0_2L*/ if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_OVL0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BG; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RDMA0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; /*OVL0*/ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL0_2L) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_GO_BG; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6853_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_mout_en_MT6833(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*DISP_TOVL0_OUT0_MOUT*/ if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RDMA0) { *addr = MT6833_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = MT6833_OVL0_2L_MOUT_TO_DISP_RDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6833_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = MT6833_OVL0_2L_MOUT_TO_DISP_RSZ0_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6833_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = MT6833_OVL0_2L_MOUT_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6833_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = MT6833_OVL0_MOUT_TO_DISP_RDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6833_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = MT6833_OVL0_MOUT_TO_DISP_RSZ0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6833_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = MT6833_OVL0_MOUT_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6833_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN; value = MT6833_RSZ0_MOUT_TO_DISP_RDMA2_RSZ0_RSZ1_SOUT; /*DISP_DITHER0_MOUT*/ } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_DSI0) { *addr = MT6833_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = MT6833_DITHER0_MOUT_TO_DISP_DSI0_SEL; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_sel_in_MT6833(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6833_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN; value = MT6833_RDMA0_SEL_IN_FROM_DISP_OVL0; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RDMA0) { *addr = MT6833_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN; value = MT6833_RDMA0_SEL_IN_FROM_DISP_OVL0_2L; /*DISP_DSI0_SEL*/ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI0) { *addr = MT6833_DISP_REG_CONFIG_DSI0_SEL_IN; value = MT6833_DSI0_SEL_IN_FROM_DISP_RDMA0_RSZ0_SOUT; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_DSI0) { *addr = MT6833_DISP_REG_CONFIG_DSI0_SEL_IN; value = MT6833_DSI0_SEL_IN_FROM_DISP_DITHER0; /*DISP_WDMA0_SEL*/ } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6833_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = MT6833_WDMA0_SEL_IN_FROM_DISP_DITHER0; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6833_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = MT6833_WDMA0_SEL_IN_FROM_DISP_OVL0; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6833_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = MT6833_WDMA0_SEL_IN_FROM_DISP_OVL0_2L; /*DISP_RSZ0_SEL*/ } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6833_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN; value = MT6833_RSZ0_SEL_IN_FROM_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6833_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN; value = MT6833_RSZ0_SEL_IN_FROM_DISP_OVL0; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_sout_sel_MT6833(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*DISP_RDMA2_RSZ0_RSZ1_SOUT*/ if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0_2L) { *addr = MT6833_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL; value = MT6833_RSZ0_SOUT_TO_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6833_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL; value = MT6833_RSZ0_SOUT_TO_DISP_OVL0; /*DISP_RDMA0_RSZ0_SOUT*/ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI0) { *addr = MT6833_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL; value = MT6833_RDMA0_SOUT_TO_DISP_DSI0_SEL; } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { *addr = MT6833_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL; value = MT6833_RDMA0_SOUT_TO_DISP_COLOR0; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_ovl_bg_blend_en_MT6833(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*OVL0_2L*/ if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_OVL0) { *addr = MT6833_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BG; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6833_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RDMA0) { *addr = MT6833_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6833_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; /*OVL0*/ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL0_2L) { *addr = MT6833_MMSYS_OVL_CON; value = DISP_OVL0_GO_BG; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6833_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6833_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6833_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_mout_en_MT6781(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*DISP_TOVL0_OUT0_MOUT*/ if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RDMA0) { *addr = MT6781_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = MT6781_OVL0_2L_MOUT_TO_DISP_RDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6781_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = MT6781_OVL0_2L_MOUT_TO_DISP_RSZ0_SEL; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6781_DISP_REG_CONFIG_DISP_TOVL0_OUT0_MOUT_EN; value = MT6781_OVL0_2L_MOUT_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6781_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = MT6781_OVL0_MOUT_TO_DISP_RDMA0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6781_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = MT6781_OVL0_MOUT_TO_DISP_RSZ0_SEL; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6781_DISP_REG_CONFIG_DISP_TOVL0_OUT1_MOUT_EN; value = MT6781_OVL0_MOUT_TO_DISP_WDMA0_SEL; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6781_DISP_REG_CONFIG_DISP_RSZ0_MOUT_EN; value = MT6781_RSZ0_MOUT_TO_DISP_RDMA2_RSZ0_RSZ1_SOUT; /*DISP_DITHER0_MOUT*/ } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_DSC0) { *addr = MT6781_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = MT6781_DITHER0_MOUT_TO_DISP_DISP_DSC_WRAP0; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6781_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = MT6781_DITHER0_MOUT_TO_DISP_DISP_WDMA0; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_DSI0) { *addr = MT6781_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = MT6781_DITHER0_MOUT_TO_DISP_DSI0_SEL; } else if (cur == DDP_COMPONENT_DSC0 && next == DDP_COMPONENT_DSI0) { *addr = MT6781_DISP_REG_CONFIG_DISP_DSC_WRAP0_MOUT_EN; value = MT6781_DISP_DSC_WRAP0_TO_DISP_DSI0_SEL; } else if (cur == DDP_COMPONENT_DSC0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6781_DISP_REG_CONFIG_DISP_DSC_WRAP0_MOUT_EN; value = MT6781_DISP_DSC_WRAP0_TO_DISP_WDMA0_SEL; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_sel_in_MT6781(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6781_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN; value = MT6781_SEL_IN_RDMA0_FROM_DISP_OVL0; /*DISP_DSI0_SEL*/ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI0) { *addr = MT6781_DISP_REG_CONFIG_DSI0_SEL_IN; value = MT6781_SEL_IN_FROM_DISP_RDMA0_RSZ0_SOUT; } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_DSI0) { *addr = MT6781_DISP_REG_CONFIG_DSI0_SEL_IN; value = MT6781_SEL_IN_FROM_DISP_DITHERR0; } else if (cur == DDP_COMPONENT_DSC0 && next == DDP_COMPONENT_DSI0) { *addr = MT6781_DISP_REG_CONFIG_DSI0_SEL_IN; value = MT6781_SEL_IN_FROM_DISP_DSC_WRAP0; /*DISP_WDMA0_SEL*/ } else if (cur == DDP_COMPONENT_DITHER0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6781_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = MT6781_WDMA0_SEL_IN_FROM_DISP_DITHER0_MOUT; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6781_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = MT6781_WDMA0_SEL_IN_FROM_DISP_OVL0; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6781_DISP_REG_CONFIG_DISP_WDMA0_SEL_IN; value = MT6781_WDMA0_SEL_IN_FROM_DISP_OVL0_2L; /*DISP_RSZ0_SEL*/ } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6781_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN; value = MT6781_RSZ0_FROM_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6781_DISP_REG_CONFIG_DISP_RSZ0_SEL_IN; value = MT6781_RSZ0_FROM_DISP_OVL0; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_sout_sel_MT6781(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*DISP_RDMA2_RSZ0_RSZ1_SOUT*/ if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0_2L) { *addr = MT6781_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL; value = MT6781_RSZ0_SOUT_TO_DISP_OVL0_2L; } else if (cur == DDP_COMPONENT_RSZ0 && next == DDP_COMPONENT_OVL0) { *addr = MT6781_DISP_RDMA2_RSZ0_RSZ1_SOUT_SEL; value = MT6781_RSZ0_SOUT_TO_DISP_OVL0; /*DISP_RDMA0_RSZ0_SOUT*/ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI0) { *addr = MT6781_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL; value = MT6781_SOUT_TO_DISP_DSI0_SEL; } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_COLOR0) { *addr = MT6781_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SOUT_SEL; value = MT6781_RDMA0_SOUT_TO_DISP_COLOR0; /*No cur or next component*/ } else { value = -1; } return value; } static int mtk_ddp_ovl_bg_blend_en_MT6781(const struct mtk_mmsys_reg_data *data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, unsigned int *addr) { int value; /*OVL0_2L*/ if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_OVL0) { *addr = MT6781_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BG; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RSZ0) { *addr = MT6781_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_RDMA0) { *addr = MT6781_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0_2L && next == DDP_COMPONENT_WDMA0) { *addr = MT6781_MMSYS_OVL_CON; value = DISP_OVL0_2L_GO_BLEND; /*OVL0*/ } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_OVL0_2L) { *addr = MT6781_MMSYS_OVL_CON; value = DISP_OVL0_GO_BG; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RSZ0) { *addr = MT6781_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) { *addr = MT6781_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; } else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_WDMA0) { *addr = MT6781_MMSYS_OVL_CON; value = DISP_OVL0_GO_BLEND; /*No cur or next component*/ } else { value = -1; } return value; } void mtk_disp_ultra_offset(void __iomem *config_regs, enum mtk_ddp_comp_id comp, bool is_dc) { unsigned int addr, reg; unsigned int shift; switch (comp) { case DDP_COMPONENT_OVL0: shift = REG_FLD_SHIFT(FLD_OVL0_ULTRA_SEL); break; case DDP_COMPONENT_OVL1: shift = REG_FLD_SHIFT(FLD_OVL1_ULTRA_SEL); break; case DDP_COMPONENT_OVL0_2L: shift = REG_FLD_SHIFT(FLD_OVL0_2L_ULTRA_SEL); break; case DDP_COMPONENT_OVL1_2L: shift = REG_FLD_SHIFT(FLD_OVL1_2L_ULTRA_SEL); break; case DDP_COMPONENT_OVL2_2L: shift = REG_FLD_SHIFT(FLD_OVL2_2L_ULTRA_SEL); break; case DDP_COMPONENT_OVL3_2L: shift = REG_FLD_SHIFT(FLD_OVL3_2L_ULTRA_SEL); break; default: DDPPR_ERR("unsupport comp id:%d\n", comp); return; } addr = DISP_REG_CONFIG_MMSYS_MISC; if (!is_dc) { reg = readl_relaxed(config_regs + addr) & ~(0x1 << shift); writel_relaxed(reg | (0x1 << shift), config_regs + addr); } else { reg = readl_relaxed(config_regs + addr) & ~(0x0 << shift); writel_relaxed(reg | (0x0 << shift), config_regs + addr); } } void mtk_ddp_add_comp_to_path(struct mtk_drm_crtc *mtk_crtc, struct mtk_ddp_comp *comp, enum mtk_ddp_comp_id prev, enum mtk_ddp_comp_id next) { int value; unsigned int addr, reg; const struct mtk_mmsys_reg_data *reg_data = mtk_crtc->mmsys_reg_data; enum mtk_ddp_comp_id cur = comp->id; void __iomem *config_regs = mtk_crtc->config_regs; struct mtk_drm_private *priv = mtk_crtc->base.dev->dev_private; switch (priv->data->mmsys_id) { case MMSYS_MT2701: break; case MMSYS_MT2712: break; case MMSYS_MT8173: break; case MMSYS_MT6779: break; case MMSYS_MT6885: value = mtk_ddp_mout_en_MT6885(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) | (unsigned int)value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_mout_en_1_MT6885(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_sout_sel_MT6885(reg_data, cur, next, &addr); if (value >= 0) writel_relaxed(value, config_regs + addr); value = mtk_ddp_sel_in_MT6885(reg_data, cur, next, &addr); if (value >= 0) writel_relaxed(value, config_regs + addr); break; case MMSYS_MT6873: value = mtk_ddp_mout_en_MT6873(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_sout_sel_MT6873(reg_data, cur, next, &addr); if (value >= 0) writel_relaxed(value, config_regs + addr); value = mtk_ddp_sel_in_MT6873(reg_data, cur, next, &addr); if (value >= 0) writel_relaxed(value, config_regs + addr); value = mtk_ddp_ovl_bg_blend_en_MT6873( reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } break; case MMSYS_MT6853: value = mtk_ddp_mout_en_MT6853(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_sout_sel_MT6853(reg_data, cur, next, &addr); if (value >= 0) writel_relaxed(value, config_regs + addr); value = mtk_ddp_sel_in_MT6853(reg_data, cur, next, &addr); if (value >= 0) writel_relaxed(value, config_regs + addr); value = mtk_ddp_ovl_bg_blend_en_MT6853( reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } break; case MMSYS_MT6877: value = mtk_ddp_mout_en_MT6877(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_sout_sel_MT6877(reg_data, cur, next, &addr); if (value >= 0) writel_relaxed(value, config_regs + addr); value = mtk_ddp_sel_in_MT6877(reg_data, cur, next, &addr); if (value >= 0) writel_relaxed(value, config_regs + addr); value = mtk_ddp_ovl_bg_blend_en_MT6877( reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } break; case MMSYS_MT6833: value = mtk_ddp_mout_en_MT6833(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_sout_sel_MT6833(reg_data, cur, next, &addr); if (value >= 0) writel_relaxed(value, config_regs + addr); value = mtk_ddp_sel_in_MT6833(reg_data, cur, next, &addr); if (value >= 0) writel_relaxed(value, config_regs + addr); value = mtk_ddp_ovl_bg_blend_en_MT6833( reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } break; case MMSYS_MT6781: value = mtk_ddp_mout_en_MT6781(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_sout_sel_MT6781(reg_data, cur, next, &addr); if (value >= 0) writel_relaxed(value, config_regs + addr); value = mtk_ddp_sel_in_MT6781(reg_data, cur, next, &addr); if (value >= 0) writel_relaxed(value, config_regs + addr); value = mtk_ddp_ovl_bg_blend_en_MT6781( reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); } break; default: pr_info("%s mtk drm not support mmsys id %d\n", __func__, priv->data->mmsys_id); break; } if (comp->funcs && comp->funcs->connect) comp->funcs->connect(comp, prev, next); } void mtk_ddp_add_comp_to_path_with_cmdq(struct mtk_drm_crtc *mtk_crtc, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, struct cmdq_pkt *handle) { unsigned int addr; int value; struct mtk_drm_private *priv = mtk_crtc->base.dev->dev_private; switch (priv->data->mmsys_id) { case MMSYS_MT2701: break; case MMSYS_MT2712: break; case MMSYS_MT8173: break; case MMSYS_MT6779: break; case MMSYS_MT6885: value = mtk_ddp_mout_en_MT6885(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); value = mtk_ddp_mout_en_1_MT6885(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); value = mtk_ddp_sout_sel_MT6885(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); value = mtk_ddp_sel_in_MT6885(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); break; case MMSYS_MT6873: value = mtk_ddp_mout_en_MT6873(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); value = mtk_ddp_sout_sel_MT6873(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); value = mtk_ddp_sel_in_MT6873(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); value = mtk_ddp_ovl_bg_blend_en_MT6873(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); break; case MMSYS_MT6853: value = mtk_ddp_mout_en_MT6853(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); value = mtk_ddp_sout_sel_MT6853(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); value = mtk_ddp_sel_in_MT6853(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); value = mtk_ddp_ovl_bg_blend_en_MT6853(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); break; case MMSYS_MT6877: value = mtk_ddp_mout_en_MT6877(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); value = mtk_ddp_sout_sel_MT6877(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); value = mtk_ddp_sel_in_MT6877(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); value = mtk_ddp_ovl_bg_blend_en_MT6877(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); break; case MMSYS_MT6833: value = mtk_ddp_mout_en_MT6833(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); value = mtk_ddp_sout_sel_MT6833(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); value = mtk_ddp_sel_in_MT6833(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); value = mtk_ddp_ovl_bg_blend_en_MT6833(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); break; case MMSYS_MT6781: value = mtk_ddp_mout_en_MT6781(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); value = mtk_ddp_sout_sel_MT6781(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); value = mtk_ddp_sel_in_MT6781(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); value = mtk_ddp_ovl_bg_blend_en_MT6781(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); break; default: pr_info("%s mtk drm not support mmsys id %d\n", __func__, priv->data->mmsys_id); break; } } void mtk_ddp_remove_comp_from_path(void __iomem *config_regs, const struct mtk_mmsys_reg_data *reg_data, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next) { unsigned int addr, reg; int value; #if defined(CONFIG_MACH_MT6885) || defined(CONFIG_MACH_MT6893) value = mtk_ddp_mout_en_MT6885(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) & ~(unsigned int)value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_mout_en_1_MT6885(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); } #endif #if defined(CONFIG_MACH_MT6873) value = mtk_ddp_mout_en_MT6873(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) & ~(unsigned int)value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_ovl_bg_blend_en_MT6873(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) & ~(unsigned int)value; writel_relaxed(reg, config_regs + addr); } #endif #if defined(CONFIG_MACH_MT6853) value = mtk_ddp_mout_en_MT6853(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_ovl_bg_blend_en_MT6853(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); } #endif #if defined(CONFIG_MACH_MT6877) value = mtk_ddp_mout_en_MT6877(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) & ~(unsigned int)value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_ovl_bg_blend_en_MT6877(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) & ~(unsigned int)value; writel_relaxed(reg, config_regs + addr); } #endif #if defined(CONFIG_MACH_MT6833) value = mtk_ddp_mout_en_MT6833(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_ovl_bg_blend_en_MT6833(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) & ~value; writel_relaxed(reg, config_regs + addr); } #endif #if defined(CONFIG_MACH_MT6781) value = mtk_ddp_mout_en_MT6781(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) & ~(unsigned int)value; writel_relaxed(reg, config_regs + addr); } value = mtk_ddp_ovl_bg_blend_en_MT6781(reg_data, cur, next, &addr); if (value >= 0) { reg = readl_relaxed(config_regs + addr) & ~(unsigned int)value; writel_relaxed(reg, config_regs + addr); } #endif } void mtk_ddp_remove_comp_from_path_with_cmdq(struct mtk_drm_crtc *mtk_crtc, enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next, struct cmdq_pkt *handle) { unsigned int addr; int value; #if defined(CONFIG_MACH_MT6885) || defined(CONFIG_MACH_MT6893) value = mtk_ddp_mout_en_MT6885(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~(unsigned int)value, value); value = mtk_ddp_mout_en_1_MT6885(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); #endif #if defined(CONFIG_MACH_MT6873) value = mtk_ddp_mout_en_MT6873(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~(unsigned int)value, value); value = mtk_ddp_ovl_bg_blend_en_MT6873(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~(unsigned int)value, value); #endif #if defined(CONFIG_MACH_MT6853) value = mtk_ddp_mout_en_MT6853(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); value = mtk_ddp_ovl_bg_blend_en_MT6853(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); #endif #if defined(CONFIG_MACH_MT6877) value = mtk_ddp_mout_en_MT6877(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); value = mtk_ddp_ovl_bg_blend_en_MT6877(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); #endif #if defined(CONFIG_MACH_MT6833) value = mtk_ddp_mout_en_MT6833(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); value = mtk_ddp_ovl_bg_blend_en_MT6833(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); #endif #if defined(CONFIG_MACH_MT6781) value = mtk_ddp_mout_en_MT6781(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); value = mtk_ddp_ovl_bg_blend_en_MT6781(mtk_crtc->mmsys_reg_data, cur, next, &addr); if (value >= 0) cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); #endif } void mtk_ddp_insert_dsc_prim_MT6853(struct mtk_drm_crtc *mtk_crtc, struct cmdq_pkt *handle) { unsigned int addr, value; /* DISP_DITHER0_MOUT -> DISP_DSC_WRAP0 */ addr = MT6853_DISP_REG_CONFIG_DISP_SPR0_MOUT_EN; value = SPR0_MOUT_TO_DISP_DSC0_SEL; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); addr = MT6853_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_DSC0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); } void mtk_ddp_remove_dsc_prim_MT6853(struct mtk_drm_crtc *mtk_crtc, struct cmdq_pkt *handle) { unsigned int addr, value; /* DISP_DITHER0_MOUT -> DISP_DSC_WRAP0 */ addr = MT6853_DISP_REG_CONFIG_DISP_SPR0_MOUT_EN; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); addr = MT6853_DISP_REG_CONFIG_DSI0_SEL_IN; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); } void mtk_ddp_insert_dsc_prim_MT6781(struct mtk_drm_crtc *mtk_crtc, struct cmdq_pkt *handle) { unsigned int addr, value; /* DISP_DITHER0_MOUT -> DISP_DSC_WRAP0 */ addr = MT6781_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = MT6781_DITHER0_MOUT_TO_DISP_DISP_DSC_WRAP0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); /* DISP_DSC_WRAP0 -> DISP_DSI */ addr = MT6781_DISP_REG_CONFIG_DISP_DSC_WRAP0_MOUT_EN; value = MT6781_DISP_DSC_WRAP0_TO_DISP_DSI0_SEL; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); addr = MT6781_DISP_REG_CONFIG_DSI0_SEL_IN; value = MT6781_SEL_IN_FROM_DISP_DSC_WRAP0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); } void mtk_ddp_remove_dsc_prim_MT6781(struct mtk_drm_crtc *mtk_crtc, struct cmdq_pkt *handle) { unsigned int addr, value; /* DISP_DITHER0_MOUT -> DISP_DSC_WRAP0 */ addr = MT6781_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); /* DISP_DSC_WRAP0 -> DISP_DSI */ addr = MT6781_DISP_REG_CONFIG_DISP_DSC_WRAP0_MOUT_EN; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); addr = MT6781_DISP_REG_CONFIG_DSI0_SEL_IN; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); } void mtk_ddp_insert_dsc_prim_MT6873(struct mtk_drm_crtc *mtk_crtc, struct cmdq_pkt *handle) { unsigned int addr, value; /* DISP_DITHER0_MOUT -> DISP_DSC_WRAP0 */ addr = MT6873_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = MOUT_DITHER0_TO_DISP_DSC_WRAP0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); addr = MT6873_DISP_REG_CONFIG_DSI0_SEL_IN; value = SEL_IN_FROM_DISP_DSC0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); } void mtk_ddp_remove_dsc_prim_MT6873(struct mtk_drm_crtc *mtk_crtc, struct cmdq_pkt *handle) { unsigned int addr, value; /* DISP_DITHER0_MOUT -> DISP_DSC_WRAP0 */ addr = MT6873_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); addr = MT6873_DISP_REG_CONFIG_DSI0_SEL_IN; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); } void mtk_ddp_insert_dsc_prim_MT6885(struct mtk_drm_crtc *mtk_crtc, struct cmdq_pkt *handle) { struct mtk_panel_params *panel_ext = mtk_drm_get_lcm_ext_params(&mtk_crtc->base); unsigned int addr, value; /* remove DISP_DITHER0_MOUT -> DSI0_SEL*/ addr = MT6885_DISP_DITHER0_MOUT_EN; value = DISP_DITHER0_MOUT_EN_TO_DSI0_SEL; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); /* DISP_DITHER0_MOUT -> DISP_PQ0_SOUT */ value = DISP_DITHER0_MOUT_EN_TO_PQ0_SOUT; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); /* DISP_PQ0_SOUT -> DISP_RDMA4_PQ0_MERGE0_SEL_IN */ addr = MT6885_DISP_PQ0_SOUT_SEL; value = 1; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); addr = MT6885_DISP_RDMA4_PQ0_MERGE0_SEL_IN; value = 1; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); /* DISP_DSI0_DSC_WRAP_SOUT -> DISP_DSC_WRAP0 */ addr = MT6885_DISP_DSI0_DSC_WRAP_SOUT_SEL; value = 1; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); /* DISP_DSC_WRAP_SOUT -> DSI0 */ addr = MT6885_DISP_DSC_WRAP_SOUT_SEL; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); addr = MT6885_DSI0_SEL_IN; value = 3; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); if (!mtk_crtc->is_dual_pipe) return; /*DSC_WARP0-> DSI1*/ if (panel_ext && panel_ext->output_mode == MTK_PANEL_DUAL_PORT) { addr = MT6885_DSI1_SEL_IN; value = DSI1_SEL_IN_FROM_DSC_WRAP0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); } /* remove MT6885_DISP_DITHER1_MOUT_EN -> DSI1_SEL*/ addr = MT6885_DISP_DITHER1_MOUT_EN; value = DISP_DITHER1_MOUT_EN_TO_DSI1_SEL; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); /* MT6885_DISP_DITHER1_MOUT_EN -> PQ1_SOUT */ addr = MT6885_DISP_DITHER1_MOUT_EN; value = DISP_DITHER1_MOUT_EN_TO_PQ1_SOUT; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, value); /* MT6885_DISP_PQ1_SOUT_SEL -> RDMA5_PQ1_SEL */ addr = MT6885_DISP_PQ1_SOUT_SEL; value = DISP_PQ1_SOUT_SEL_TO_DISP_RDMA5_PQ1_SEL; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); /* MT6885_DISP_RDMA5_PQ1_SEL_IN -> DSC_WRAP0 */ addr = MT6885_DISP_RDMA5_PQ1_SEL_IN; value = MT6885_DISP_RDMA5_PQ1_SEL_IN_FROM_PQ1_SOUT; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); } void mtk_ddp_remove_dsc_prim_MT6885(struct mtk_drm_crtc *mtk_crtc, struct cmdq_pkt *handle) { struct mtk_panel_params *panel_ext = mtk_drm_get_lcm_ext_params(&mtk_crtc->base); unsigned int addr, value; /* DISP_DITHER0_MOUT -> DISP_PQ0_SOUT */ addr = MT6885_DISP_DITHER0_MOUT_EN; value = DISP_DITHER0_MOUT_EN_TO_PQ0_SOUT; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); /* DISP_PQ0_SOUT -> DISP_RDMA4_PQ0_MERGE0_SEL_IN */ addr = MT6885_DISP_PQ0_SOUT_SEL; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); addr = MT6885_DISP_RDMA4_PQ0_MERGE0_SEL_IN; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); /* DISP_DSI0_DSC_WRAP_SOUT -> DISP_DSC_WRAP0 */ addr = MT6885_DISP_DSI0_DSC_WRAP_SOUT_SEL; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); /* DISP_DSC_WRAP_SOUT -> DSI0 */ addr = MT6885_DISP_DSC_WRAP_SOUT_SEL; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); addr = MT6885_DSI0_SEL_IN; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); if (!mtk_crtc->is_dual_pipe) return; /*DSC_WARP0-> DSI1*/ if (panel_ext && panel_ext->output_mode == MTK_PANEL_DUAL_PORT) { addr = MT6885_DSI1_SEL_IN; value = 0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); } /* MT6885_DISP_DITHER1_MOUT_EN -> PQ1_SOUT */ addr = MT6885_DISP_DITHER1_MOUT_EN; value = DISP_DITHER1_MOUT_EN_TO_PQ1_SOUT; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, ~value, value); /* MT6885_DISP_PQ1_SOUT_SEL -> RDMA5_PQ1_SEL */ addr = MT6885_DISP_PQ1_SOUT_SEL; value = DISP_PQ1_SOUT_SEL_TO_DISP_MERGE0; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); /* MT6885_DISP_RDMA5_PQ1_SEL_IN -> DSC_WRAP0 */ addr = MT6885_DISP_RDMA5_PQ1_SEL_IN; value = MT6885_DISP_RDMA5_PQ1_SEL_IN_FROM_RDMA5_SOUT; cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, mtk_crtc->config_regs_pa + addr, value, ~0); } static void mtk_ddp_ext_dual_pipe_dsc_MT6885(struct mtk_drm_crtc *mtk_crtc, struct mtk_disp_mutex *mutex) { unsigned int addr, value, shift, reg; void __iomem *config_regs = mtk_crtc->config_regs; DDPFUNC(); /* DISP_OVL3_2L_OUT0_MOUT -> DISP_RDMA5 */ addr = MT6885_DISP_OVL3_2L_OUT0_MOUT; value = DISP_OVL3_2L_OUT0_MOUT_TO_DISP_RDMA5; writel_relaxed(value, config_regs + addr); /* DISP_OVL3_2L -> display*/ addr = MT6885_MMSYS_OVL_CON; value = DISP_OVL3_2L_TO_DISP_RDMA5; reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); /*OVL3 Ultra/pre ultra from RDMA setting, "00"RDMA4;"01"RDMA5*/ shift = REG_FLD_SHIFT(FLD_OVL3_2L_ULTRA_SEL); addr = DISP_REG_CONFIG_MMSYS_MISC; reg = readl_relaxed(config_regs + addr) & ~(0x0 << shift); writel_relaxed(reg | (0x5 << shift), config_regs + addr); /* DISP_RDMA5_SOUT -> DISP_MERGE1 * addr = MT6885_DISP_RDMA5_SOUT; * value = DISP_RDMA5_TO_DISP_MERGE1; * writel_relaxed(value, config_regs + addr); * * DISP_RDMA4_SOUT -> DISP_MERGE1 * addr = MT6885_DISP_RDMA4_SOUT; * value = DISP_RDMA4_TO_DISP_MERGE1; * writel_relaxed(value, config_regs + addr); * * DISP_MERGE1 -> DISP_DP_WRAP_SEL * addr = MT6885_DISP_DP_WRAP_SEL_IN; * value = DISP_MERGE1_TO_DISP_DP_INTF0; * writel_relaxed(value, config_regs + addr); */ /* DISP_RDMA4_SOUT -> RDMA4_PQ0_MERGE0*/ addr = MT6885_DISP_RDMA4_SOUT; value = DISP_RDMA4_TO_DISP_RDMA4_PQ0_MERGE0_SEL; writel_relaxed(value, config_regs + addr); /* DISP_RDMA4_SOUT -> RDMA4_PQ0_MERGE0*/ addr = MT6885_DISP_RDMA4_PQ0_MERGE0_SEL_IN; value = DISP_RDMA4_SOUT_TO_DISP_RDMA4_PQ0_MERGE0_SEL; writel_relaxed(value, config_regs + addr); /* DISP_RDMA5_SOUT -> DISP_RDMA5_PQ1_SEL*/ addr = MT6885_DISP_RDMA5_SOUT; value = DISP_RDMA5_TO_DISP_RDMA5_PQ1_SEL; writel_relaxed(value, config_regs + addr); /*RDMA5_SOUT -> RDMA5_PQ1_SEL_IN*/ addr = MT6885_DISP_RDMA5_PQ1_SEL_IN; value = MT6885_DISP_RDMA5_PQ1_SEL_IN_FROM_RDMA5_SOUT; writel_relaxed(value, config_regs + addr); /* DSI0_DSC_WRAP_SOUT -> DSC_WRAP*/ addr = MT6885_DISP_DSI0_DSC_WRAP_SOUT_SEL; value = MT6885_DISP_DSI0_DSC_WRAP_SOUT_TO_DISP_DSC_WRAP0; writel_relaxed(value, config_regs + addr); /* DSC_WRAP_SOUT -> DP*/ addr = MT6885_DISP_DSC_WRAP_SOUT_SEL; value = DISP_DSC_WRAP_SOUT_TO_DISP_DP_WRAP_SEL; writel_relaxed(value, config_regs + addr); /* DSC_WRAP_SOUT -> DP*/ addr = MT6885_DISP_DP_WRAP_SEL_IN; value = DISP_DSC_WRAP_SOUT_TO_DISP_DP_INTF0; writel_relaxed(value, config_regs + addr); } static void mtk_ddp_ext_insert_dual_pipe_MT6885(struct mtk_drm_crtc *mtk_crtc, struct mtk_disp_mutex *mutex) { unsigned int addr, value, shift, reg; void __iomem *config_regs = mtk_crtc->config_regs; DDPFUNC(); /* DISP_OVL3_2L_OUT0_MOUT -> DISP_RDMA5 */ addr = MT6885_DISP_OVL3_2L_OUT0_MOUT; value = DISP_OVL3_2L_OUT0_MOUT_TO_DISP_RDMA5; writel_relaxed(value, config_regs + addr); /* DISP_OVL3_2L -> display*/ addr = MT6885_MMSYS_OVL_CON; value = DISP_OVL3_2L_TO_DISP_RDMA5; reg = readl_relaxed(config_regs + addr) | value; writel_relaxed(reg, config_regs + addr); /*OVL3 Ultra/pre ultra from RDMA setting, "00"RDMA4;"01"RDMA5*/ shift = REG_FLD_SHIFT(FLD_OVL3_2L_ULTRA_SEL); addr = DISP_REG_CONFIG_MMSYS_MISC; reg = readl_relaxed(config_regs + addr) & ~(0x0 << shift); writel_relaxed(reg | (0x5 << shift), config_regs + addr); /* DISP_RDMA5_SOUT -> DISP_MERGE1 */ addr = MT6885_DISP_RDMA5_SOUT; value = DISP_RDMA5_TO_DISP_MERGE1; writel_relaxed(value, config_regs + addr); /* DISP_RDMA4_SOUT -> DISP_MERGE1 */ addr = MT6885_DISP_RDMA4_SOUT; value = DISP_RDMA4_TO_DISP_MERGE1; writel_relaxed(value, config_regs + addr); /* DISP_MERGE1 -> DISP_DP_WRAP_SEL */ addr = MT6885_DISP_DP_WRAP_SEL_IN; value = DISP_MERGE1_TO_DISP_DP_INTF0; writel_relaxed(value, config_regs + addr); } void mtk_ddp_dual_pipe_dump(struct mtk_drm_crtc *mtk_crtc) { unsigned int addr, shift, reg; void __iomem *config_regs = mtk_crtc->config_regs; DDPDUMP("%s\n", __func__); addr = MT6885_DISP_OVL2_2L_OUT0_MOUT; reg = readl_relaxed(config_regs + addr); DDPDUMP("MT6885_DISP_OVL2_2L_OUT0_MOUT:0x%x\n", reg); addr = MT6885_DISP_RDMA4_SOUT; reg = readl_relaxed(config_regs + addr); DDPDUMP("MT6885_DISP_RDMA4_SOUT:0x%x\n", reg); /* DISP_OVL3_2L_OUT0_MOUT -> DISP_RDMA5 */ addr = MT6885_DISP_OVL3_2L_OUT0_MOUT; reg = readl_relaxed(config_regs + addr); DDPDUMP("MT6885_DISP_OVL3_2L_OUT0_MOUT:0x%x\n", reg); /* DISP_OVL3_2L -> DISP_RDMA5 */ addr = MT6885_MMSYS_OVL_CON; reg = readl_relaxed(config_regs + addr); DDPDUMP("MT6885_MMSYS_OVL_CON:0x%x\n", reg); /*OVL3 Ultra/pre ultra from RDMA setting, "00"RDMA4;"01"RDMA5*/ shift = REG_FLD_SHIFT(FLD_OVL3_2L_ULTRA_SEL); addr = DISP_REG_CONFIG_MMSYS_MISC; reg = readl_relaxed(config_regs + addr); DDPDUMP("DISP_REG_CONFIG_MMSYS_MISC:0x%x\n", reg); /* DISP_RDMA5_SOUT -> DISP_MERGE1 */ addr = MT6885_DISP_RDMA5_SOUT; reg = readl_relaxed(config_regs + addr); DDPDUMP("MT6885_DISP_RDMA5_SOUT:0x%x\n", reg); /* DISP_MERGE1 -> DISP_DP_WRAP_SEL */ addr = MT6885_DISP_DP_WRAP_SEL_IN; reg = readl_relaxed(config_regs + addr); DDPDUMP("MT6885_DISP_DP_WRAP_SEL_IN:0x%x\n", reg); } void mtk_ddp_connect_dual_pipe_path(struct mtk_drm_crtc *mtk_crtc, struct mtk_disp_mutex *mutex) { DDPFUNC(); if (drm_crtc_index(&mtk_crtc->base) == 1) { if ((&mtk_crtc->base)->state->adjusted_mode.vrefresh == 60) mtk_ddp_ext_dual_pipe_dsc_MT6885(mtk_crtc, mutex); else mtk_ddp_ext_insert_dual_pipe_MT6885(mtk_crtc, mutex); } else if (drm_crtc_index(&mtk_crtc->base) == 0) { unsigned int i, j; struct mtk_ddp_comp *comp; struct mtk_ddp_comp **ddp_comp; enum mtk_ddp_comp_id prev_id, next_id; DDPMSG("connect dual pipe path\n"); for_each_comp_in_dual_pipe(comp, mtk_crtc, i, j) { if (j >= mtk_crtc->dual_pipe_ddp_ctx.ddp_comp_nr[i]) { DDPINFO("exceed comp nr\n"); continue; } DDPINFO("%d %d\n", i, j); ddp_comp = mtk_crtc->dual_pipe_ddp_ctx.ddp_comp[i]; prev_id = (j == 0 ? DDP_COMPONENT_ID_MAX : ddp_comp[j - 1]->id); /*connect the last comp to encoder*/ if (j + 1 == mtk_crtc->dual_pipe_ddp_ctx.ddp_comp_nr[i]) next_id = DDP_COMPONENT_DSI1; else next_id = ddp_comp[j + 1]->id; mtk_ddp_add_comp_to_path(mtk_crtc, ddp_comp[j], prev_id, next_id); DDPINFO("con %u %u-\n", prev_id, next_id); } } } const struct mtk_mmsys_reg_data * mtk_ddp_get_mmsys_reg_data(enum mtk_mmsys_id mmsys_id) { const struct mtk_mmsys_reg_data *data = NULL; switch (mmsys_id) { case MMSYS_MT2701: data = &mt2701_mmsys_reg_data; break; case MMSYS_MT2712: data = &mt2712_mmsys_reg_data; break; case MMSYS_MT8173: data = &mt8173_mmsys_reg_data; break; case MMSYS_MT6779: data = &mt6779_mmsys_reg_data; break; case MMSYS_MT6885: data = &mt6885_mmsys_reg_data; break; case MMSYS_MT6873: data = &mt6873_mmsys_reg_data; break; case MMSYS_MT6853: case MMSYS_MT6877: data = &mt6853_mmsys_reg_data; break; case MMSYS_MT6833: data = &mt6833_mmsys_reg_data; break; case MMSYS_MT6781: data = &mt6781_mmsys_reg_data; break; default: pr_info("mtk drm not support mmsys id %d\n", mmsys_id); break; } return data; } struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id) { struct mtk_ddp *ddp = dev_get_drvdata(dev); if (id >= 10) return ERR_PTR(-EINVAL); if (ddp->mutex[id].claimed) return ERR_PTR(-EBUSY); ddp->mutex[id].claimed = true; return &ddp->mutex[id]; } void mtk_disp_mutex_put(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); if (&ddp->mutex[mutex->id] != mutex) DDPAEE("%s:%d, invalid mutex:(%p,%p) id:%d\n", __func__, __LINE__, &ddp->mutex[mutex->id], mutex, mutex->id); mutex->claimed = false; } int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); int ret; ret = pm_runtime_get_sync(ddp->dev); if (ret < 0) DRM_ERROR("Failed to enable power domain: %d\n", ret); return clk_prepare_enable(ddp->clk); } void mtk_disp_mutex_unprepare(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); int ret; clk_disable_unprepare(ddp->clk); ret = pm_runtime_put(ddp->dev); if (ret < 0) DRM_ERROR("Failed to disable power domain: %d\n", ret); } void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex, enum mtk_ddp_comp_id id) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int reg; if (&ddp->mutex[mutex->id] != mutex) DDPAEE("%s:%d, invalid mutex:(%p,%p) id:%d\n", __func__, __LINE__, &ddp->mutex[mutex->id], mutex, mutex->id); if (ddp->data->mutex_mod[id] <= BIT(31)) { reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, mutex->id)); reg |= ddp->data->mutex_mod[id]; writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, mutex->id)); } else { reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD2(mutex->id)); reg |= (ddp->data->mutex_mod[id] & ~BIT(31)); writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD2(mutex->id)); } DDPDBG("%s mutex%d add %d\n", __func__, mutex->id, id); } /* TODO: should be refactor, need path rather than crtc */ void mtk_disp_mutex_src_set(struct mtk_drm_crtc *mtk_crtc, bool is_cmd_mode) { struct mtk_disp_mutex *mutex = mtk_crtc->mutex[0]; struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); int i, j, id, type; unsigned int val = DDP_MUTEX_SOF_SINGLE_MODE; struct mtk_ddp_comp *comp = NULL; if (&ddp->mutex[mutex->id] != mutex) DDPAEE("%s:%d, invalid mutex:(%p,%p) id:%d\n", __func__, __LINE__, &ddp->mutex[mutex->id], mutex, mutex->id); if (is_cmd_mode) { writel_relaxed( ddp->data->mutex_sof[val], ddp->regs + DISP_REG_MUTEX_SOF(ddp->data, mutex->id)); return; } id = DDP_COMPONENT_DSI0; for_each_comp_in_cur_crtc_path(comp, mtk_crtc, i, j) { id = comp->id; type = mtk_ddp_comp_get_type(id); if (type == MTK_DSI || type == MTK_DPI || type == MTK_DP_INTF) break; } if (id == DDP_COMPONENT_DSI0) val = DDP_MUTEX_SOF_DSI0; else if (id == DDP_COMPONENT_DSI1) val = DDP_MUTEX_SOF_DSI1; else if ((id == DDP_COMPONENT_DPI0) || (id == DDP_COMPONENT_DP_INTF0)) val = DDP_MUTEX_SOF_DPI0; else if (id == DDP_COMPONENT_DPI1) val = DDP_MUTEX_SOF_DPI1; DDPMSG("%s, id:%d, val:0x%x\n", __func__, id, ddp->data->mutex_sof[val]); writel_relaxed(ddp->data->mutex_sof[val], ddp->regs + DISP_REG_MUTEX_SOF(ddp->data, mutex->id)); } void mtk_disp_mutex_add_comp_with_cmdq(struct mtk_drm_crtc *mtk_crtc, enum mtk_ddp_comp_id id, bool is_cmd_mode, struct cmdq_pkt *handle, unsigned int mutex_id) { struct mtk_panel_params *panel_ext = mtk_drm_get_lcm_ext_params(&mtk_crtc->base); struct mtk_disp_mutex *mutex = NULL; struct mtk_ddp *ddp = NULL; unsigned int reg; if (mutex_id >= DDP_PATH_NR) { DDPPR_ERR("mutex id is out of bound:%d\n", mutex_id); return; } mutex = mtk_crtc->mutex[mutex_id]; ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); if (&ddp->mutex[mutex->id] != mutex) DDPAEE("%s:%d, invalid mutex:(%p,%p) id:%d\n", __func__, __LINE__, &ddp->mutex[mutex->id], mutex, mutex->id); reg = DDP_MUTEX_SOF_SINGLE_MODE; switch (id) { case DDP_COMPONENT_DSI0: if (is_cmd_mode) reg = DDP_MUTEX_SOF_SINGLE_MODE; else reg = DDP_MUTEX_SOF_DSI0; break; case DDP_COMPONENT_DSI1: if (is_cmd_mode) reg = DDP_MUTEX_SOF_SINGLE_MODE; else reg = DDP_MUTEX_SOF_DSI1; break; case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DP_INTF0: if (is_cmd_mode) reg = DDP_MUTEX_SOF_SINGLE_MODE; else reg = DDP_MUTEX_SOF_DPI0; break; case DDP_COMPONENT_DPI1: if (is_cmd_mode) reg = DDP_MUTEX_SOF_SINGLE_MODE; else reg = DDP_MUTEX_SOF_DPI1; break; default: if (ddp->data->mutex_mod[id] <= BIT(31)) { cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, ddp->regs_pa + DISP_REG_MUTEX_MOD(ddp->data, mutex->id), ddp->data->mutex_mod[id], ddp->data->mutex_mod[id]); if (panel_ext && panel_ext->output_mode == MTK_PANEL_DUAL_PORT && id == DDP_COMPONENT_DSC0) { cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, ddp->regs_pa + DISP_REG_MUTEX_MOD(ddp->data, mutex->id), MT6885_MUTEX_MOD0_DISP_DSC1, MT6885_MUTEX_MOD0_DISP_DSC1); DDPINFO("mutex_add_comp /w cmdq mutex%d add DSC1\n", mutex->id); } } else { cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, ddp->regs_pa + DISP_REG_MUTEX_MOD2(mutex->id), ddp->data->mutex_mod[id] & ~BIT(31), ddp->data->mutex_mod[id] & ~BIT(31)); } DDPINFO("mutex_add_comp /w cmdq mutex%d add %s\n", mutex->id, mtk_dump_comp_str_id(id)); return; } cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, ddp->regs_pa + DISP_REG_MUTEX_SOF(ddp->data, mutex->id), ddp->data->mutex_sof[reg], ~0); } void mtk_disp_mutex_remove_comp(struct mtk_disp_mutex *mutex, enum mtk_ddp_comp_id id) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int reg; if (&ddp->mutex[mutex->id] != mutex) DDPAEE("%s:%d, invalid mutex:(%p,%p) id:%d\n", __func__, __LINE__, &ddp->mutex[mutex->id], mutex, mutex->id); switch (id) { case DDP_COMPONENT_DSI0: case DDP_COMPONENT_DSI1: case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DP_INTF0: case DDP_COMPONENT_DPI1: writel_relaxed( MUTEX_SOF_SINGLE_MODE, ddp->regs + DISP_REG_MUTEX_SOF(ddp->data, mutex->id)); break; default: if (ddp->data->mutex_mod[id] <= BIT(31)) { reg = readl_relaxed( ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, mutex->id)); reg &= ~(ddp->data->mutex_mod[id]); writel_relaxed( reg, ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, mutex->id)); } else { reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD2(mutex->id)); reg &= ~(ddp->data->mutex_mod[id] & ~BIT(31)); writel_relaxed(reg, ddp->regs + DISP_REG_MUTEX_MOD2( mutex->id)); } break; } } void mtk_disp_mutex_remove_comp_with_cmdq(struct mtk_drm_crtc *mtk_crtc, enum mtk_ddp_comp_id id, struct cmdq_pkt *handle, unsigned int mutex_id) { struct mtk_panel_params *panel_ext = mtk_drm_get_lcm_ext_params(&mtk_crtc->base); struct mtk_disp_mutex *mutex = NULL; struct mtk_ddp *ddp = NULL; if (mutex_id >= DDP_PATH_NR) { DDPPR_ERR("mutex id is out of bound:%d\n", mutex_id); return; } mutex = mtk_crtc->mutex[mutex_id]; ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); if (&ddp->mutex[mutex->id] != mutex) DDPAEE("%s:%d, invalid mutex:(%p,%p) id:%d\n", __func__, __LINE__, &ddp->mutex[mutex->id], mutex, mutex->id); switch (id) { case DDP_COMPONENT_DSI0: case DDP_COMPONENT_DSI1: case DDP_COMPONENT_DPI0: case DDP_COMPONENT_DP_INTF0: case DDP_COMPONENT_DPI1: cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, ddp->regs_pa + DISP_REG_MUTEX_SOF(ddp->data, mutex->id), MUTEX_SOF_SINGLE_MODE, ~0); break; default: if (ddp->data->mutex_mod[id] <= BIT(31)) { cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, ddp->regs_pa + DISP_REG_MUTEX_MOD(ddp->data, mutex->id), ~(ddp->data->mutex_mod[id]), ddp->data->mutex_mod[id]); if (panel_ext && panel_ext->output_mode == MTK_PANEL_DUAL_PORT && id == DDP_COMPONENT_DSC0) { cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, ddp->regs_pa + DISP_REG_MUTEX_MOD(ddp->data, mutex->id), ~((unsigned int)MT6885_MUTEX_MOD0_DISP_DSC1), (unsigned int)MT6885_MUTEX_MOD0_DISP_DSC1); DDPINFO("mutex_remove_comp /w cmdq mutex%d add DSC1\n", mutex->id); } } else { cmdq_pkt_write(handle, mtk_crtc->gce_obj.base, ddp->regs_pa + DISP_REG_MUTEX_MOD2(mutex->id), ~(ddp->data->mutex_mod[id] & ~BIT(31)), (ddp->data->mutex_mod[id] & ~BIT(31))); } break; } } void mtk_disp_mutex_trigger(struct mtk_disp_mutex *mutex, void *handle) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); cmdq_pkt_write(handle, ddp->cmdq_base, ddp->regs_pa + DISP_REG_MUTEX_EN(mutex->id), 1, ~0); } void mtk_disp_mutex_inten_enable(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int val; val = readl_relaxed(ddp->regs + DISP_REG_MUTEX_INTEN); val |= (0x1 << (unsigned int)mutex->id); val |= (0x1 << (unsigned int)(mutex->id + DISP_MUTEX_TOTAL)); writel_relaxed(val, ddp->regs + DISP_REG_MUTEX_INTEN); } void mtk_disp_mutex_inten_enable_cmdq(struct mtk_disp_mutex *mutex, void *handle) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int val = 0; val |= (0x1 << (unsigned int)mutex->id); val |= (0x1 << (unsigned int)(mutex->id + DISP_MUTEX_TOTAL)); cmdq_pkt_write(handle, ddp->cmdq_base, ddp->regs_pa + DISP_REG_MUTEX_INTEN, val, val); } void mtk_disp_mutex_inten_disable_cmdq(struct mtk_disp_mutex *mutex, void *handle) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int mask = 0; mask |= (0x1 << (unsigned int)mutex->id); mask |= (0x1 << (unsigned int)(mutex->id + DISP_MUTEX_TOTAL)); cmdq_pkt_write(handle, ddp->cmdq_base, ddp->regs_pa + DISP_REG_MUTEX_INTEN, 0, mask); } void mtk_disp_mutex_enable(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); if (&ddp->mutex[mutex->id] != mutex) DDPAEE("%s:%d, invalid mutex:(%p,%p) id:%d\n", __func__, __LINE__, &ddp->mutex[mutex->id], mutex, mutex->id); writel(1, ddp->regs + DISP_REG_MUTEX_EN(mutex->id)); mtk_disp_mutex_inten_enable(mutex); } void mtk_disp_mutex_enable_cmdq(struct mtk_disp_mutex *mutex, struct cmdq_pkt *cmdq_handle, struct cmdq_base *cmdq_base) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); if (&ddp->mutex[mutex->id] != mutex) DDPAEE("%s:%d, invalid mutex:(%p,%p) id:%d\n", __func__, __LINE__, &ddp->mutex[mutex->id], mutex, mutex->id); cmdq_pkt_write(cmdq_handle, cmdq_base, ddp->regs_pa + DISP_REG_MUTEX_CFG, 0, ~0); cmdq_pkt_write(cmdq_handle, cmdq_base, ddp->regs_pa + DISP_REG_MUTEX_EN(mutex->id), 1, ~0); mtk_disp_mutex_inten_enable_cmdq(mutex, cmdq_handle); } void mtk_disp_mutex_disable(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); if (&ddp->mutex[mutex->id] != mutex) DDPAEE("%s:%d, invalid mutex:(%p,%p) id:%d\n", __func__, __LINE__, &ddp->mutex[mutex->id], mutex, mutex->id); writel(0, ddp->regs + DISP_REG_MUTEX_EN(mutex->id)); if (mutex->id == 2) { writel(1, ddp->regs + DISP_REG_MUTEX_RST(mutex->id)); udelay(1); writel(0, ddp->regs + DISP_REG_MUTEX_RST(mutex->id)); } } void mtk_disp_mutex_acquire(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); u32 tmp; writel(1, ddp->regs + DISP_REG_MUTEX_EN(mutex->id)); writel(1, ddp->regs + DISP_REG_MUTEX(mutex->id)); if (readl_poll_timeout_atomic(ddp->regs + DISP_REG_MUTEX(mutex->id), tmp, tmp & INT_MUTEX, 1, 10000)) DDPPR_ERR("could not acquire mutex %d\n", mutex->id); } void mtk_disp_mutex_release(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); writel(0, ddp->regs + DISP_REG_MUTEX(mutex->id)); } void mtk_disp_mutex_submit_sof(struct mtk_disp_mutex *mutex) { unsigned int reg; struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); if (&ddp->mutex[mutex->id] != mutex) DDPAEE("%s:%d, invalid mutex:(%p,%p) id:%d\n", __func__, __LINE__, &ddp->mutex[mutex->id], mutex, mutex->id); //select mutex sof control:0,submit SOF directly; 1 wait until 0 reg = readl_relaxed(ddp->regs + DISP_REG_MUTEX_SOF(ddp->data, mutex->id)) & 0XFFDF; writel(reg, ddp->regs + DISP_REG_MUTEX_SOF(ddp->data, mutex->id)); DDPFUNC(); } static irqreturn_t mtk_disp_mutex_irq_handler(int irq, void *dev_id) { struct mtk_ddp *ddp = dev_id; unsigned int val = 0; unsigned int m_id = 0; int ret = 0; if (mtk_drm_top_clk_isr_get("mutex_irq") == false) { DDPIRQ("%s, top clk off\n", __func__); return IRQ_NONE; } val = readl(ddp->regs + DISP_REG_MUTEX_INTSTA) & DISP_MUTEX_INT_MSK; if (!val) { ret = IRQ_NONE; goto out; } DRM_MMP_MARK(IRQ, irq, val); DDPIRQ("MM_MUTEX irq, val:0x%x\n", val); writel(~val, ddp->regs + DISP_REG_MUTEX_INTSTA); for (m_id = 0; m_id < DISP_MUTEX_DDP_COUNT; m_id++) { if (val & (0x1 << m_id)) { DDPIRQ("[IRQ] mutex%d sof!\n", m_id); DRM_MMP_MARK(mutex[m_id], val, 0); mtk_drm_cwb_backup_copy_size(); disp_aal_on_start_of_frame(); } if (val & (0x1 << (m_id + DISP_MUTEX_TOTAL))) { DDPIRQ("[IRQ] mutex%d eof!\n", m_id); DRM_MMP_MARK(mutex[m_id], val, 1); } } ret = IRQ_HANDLED; out: mtk_drm_top_clk_isr_put("mutex_irq"); return ret; } void mutex_dump_reg_mt6885(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); void __iomem *module_base = ddp->regs; DDPDUMP("== DISP MUTEX REGS ==\n"); DDPDUMP("0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x\n", 0x0, readl_relaxed(module_base + 0x0), 0x4, readl_relaxed(module_base + 0x4), 0x8, readl_relaxed(module_base + 0x8), 0x020, readl_relaxed(module_base + 0x020)); DDPDUMP("0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x\n", 0x028, readl_relaxed(module_base + 0x028), 0x02C, readl_relaxed(module_base + 0x02C), 0x030, readl_relaxed(module_base + 0x030), 0x034, readl_relaxed(module_base + 0x034)); DDPDUMP("0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x\n", 0x040, readl_relaxed(module_base + 0x040), 0x048, readl_relaxed(module_base + 0x048), 0x04C, readl_relaxed(module_base + 0x04C), 0x050, readl_relaxed(module_base + 0x050)); DDPDUMP("0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x\n", 0x054, readl_relaxed(module_base + 0x054), 0x060, readl_relaxed(module_base + 0x060), 0x068, readl_relaxed(module_base + 0x068), 0x06C, readl_relaxed(module_base + 0x06C)); DDPDUMP("0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x\n", 0x070, readl_relaxed(module_base + 0x070), 0x074, readl_relaxed(module_base + 0x074), 0x080, readl_relaxed(module_base + 0x080), 0x088, readl_relaxed(module_base + 0x088)); DDPDUMP("0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x\n", 0x08C, readl_relaxed(module_base + 0x08C), 0x090, readl_relaxed(module_base + 0x090), 0x094, readl_relaxed(module_base + 0x094)); } void mutex_dump_reg_mt6873(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); void __iomem *module_base = ddp->regs; DDPDUMP("== DISP MUTEX REGS ==\n"); DDPDUMP("0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x\n", 0x0, readl_relaxed(module_base + 0x0), 0x4, readl_relaxed(module_base + 0x4), 0x8, readl_relaxed(module_base + 0x8), 0x020, readl_relaxed(module_base + 0x020)); DDPDUMP("0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x\n", 0x028, readl_relaxed(module_base + 0x028), 0x02C, readl_relaxed(module_base + 0x02C), 0x030, readl_relaxed(module_base + 0x030), 0x034, readl_relaxed(module_base + 0x034)); DDPDUMP("0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x\n", 0x040, readl_relaxed(module_base + 0x040), 0x048, readl_relaxed(module_base + 0x048), 0x04C, readl_relaxed(module_base + 0x04C), 0x050, readl_relaxed(module_base + 0x050)); DDPDUMP("0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x\n", 0x054, readl_relaxed(module_base + 0x054), 0x060, readl_relaxed(module_base + 0x060), 0x068, readl_relaxed(module_base + 0x068), 0x06C, readl_relaxed(module_base + 0x06C)); DDPDUMP("0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x\n", 0x070, readl_relaxed(module_base + 0x070), 0x074, readl_relaxed(module_base + 0x074), 0x080, readl_relaxed(module_base + 0x080), 0x088, readl_relaxed(module_base + 0x088)); DDPDUMP("0x%03x=0x%08x 0x%03x=0x%08x 0x%03x=0x%08x\n", 0x08C, readl_relaxed(module_base + 0x08C), 0x090, readl_relaxed(module_base + 0x090), 0x094, readl_relaxed(module_base + 0x094)); } void mutex_dump_analysis_mt6885(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int i = 0; unsigned int j = 0; char mutex_module[512] = {'\0'}; char *p = NULL; int len = 0; unsigned int val; DDPDUMP("== DISP Mutex Analysis ==\n"); for (i = 0; i < 5; i++) { unsigned int mod0, mod1; p = mutex_module; len = 0; if (readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, i)) == 0) continue; val = readl_relaxed(ddp->regs + DISP_REG_MUTEX_SOF(ddp->data, i)); len = sprintf(p, "MUTEX%d:SOF=%s,EOF=%s,WAIT=%d,module=(", i, mtk_ddp_get_mutex_sof_name( REG_FLD_VAL_GET(SOF_FLD_MUTEX0_SOF, val)), mtk_ddp_get_mutex_sof_name( REG_FLD_VAL_GET(SOF_FLD_MUTEX0_EOF, val)), REG_FLD_VAL_GET(SOF_FLD_MUTEX0_SOF_WAIT, val)); if (len < 0) { /* Handle sprintf() error */ DDPPR_ERR("sprintf error\n"); } p += len; mod0 = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, i)); for (j = 0; j < 32; j++) { if ((mod0 & (1 << j))) { len = sprintf(p, "%s,", ddp_get_mutex_module0_name_mt6885(j)); if (len < 0) { /* Handle sprintf() error */ DDPPR_ERR("sprintf error\n"); } p += len; } } mod1 = readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD2(mutex->id)); for (j = 0; j < 32; j++) { if ((mod1 & (1 << j))) { len = sprintf(p, "%s,", ddp_get_mutex_module1_name_mt6885(j)); if (len < 0) { /* Handle sprintf() error */ DDPPR_ERR("sprintf error\n"); } p += len; } } DDPDUMP("%s)\n", mutex_module); } } void mutex_dump_analysis_mt6873(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); unsigned int i = 0; unsigned int j = 0; char mutex_module[512] = {'\0'}; char *p = NULL; int len = 0; unsigned int val; DDPDUMP("== DISP Mutex Analysis ==\n"); for (i = 0; i < 5; i++) { p = mutex_module; len = 0; if (readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, i)) == 0) continue; val = readl_relaxed(ddp->regs + DISP_REG_MUTEX_SOF(ddp->data, i)); len = sprintf(p, "MUTEX%d:SOF=%s,EOF=%s,WAIT=%d,module=(", i, mtk_ddp_get_mutex_sof_name( REG_FLD_VAL_GET(SOF_FLD_MUTEX0_SOF, val)), mtk_ddp_get_mutex_sof_name( REG_FLD_VAL_GET(SOF_FLD_MUTEX0_EOF, val)), REG_FLD_VAL_GET(SOF_FLD_MUTEX0_SOF_WAIT, val)); p += len; for (j = 0; j < 32; j++) { unsigned int regval = readl_relaxed( ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, i)); if ((regval & (1 << j))) { len = sprintf(p, "%s,", ddp_get_mutex_module0_name_mt6873(j)); p += len; } } DDPDUMP("%s)\n", mutex_module); } } void mutex_dump_analysis_mt6853(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); int i = 0; int j = 0; char mutex_module[512] = {'\0'}; char *p = NULL; int len = 0; unsigned int val; DDPDUMP("== DISP Mutex Analysis ==\n"); for (i = 0; i < 5; i++) { p = mutex_module; len = 0; if (readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, i)) == 0) continue; val = readl_relaxed(ddp->regs + DISP_REG_MUTEX_SOF(ddp->data, i)); len = sprintf(p, "MUTEX%d:SOF=%s,EOF=%s,WAIT=%d,module=(", i, mtk_ddp_get_mutex_sof_name( REG_FLD_VAL_GET(SOF_FLD_MUTEX0_SOF, val)), mtk_ddp_get_mutex_sof_name( REG_FLD_VAL_GET(SOF_FLD_MUTEX0_EOF, val)), REG_FLD_VAL_GET(SOF_FLD_MUTEX0_SOF_WAIT, val)); p += len; for (j = 0; j < 32; j++) { unsigned int regval = readl_relaxed( ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, i)); if ((regval & (1 << j))) { len = sprintf(p, "%s,", ddp_get_mutex_module0_name_mt6853(j)); p += len; } } DDPDUMP("%s)\n", mutex_module); } } void mutex_dump_analysis_mt6877(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); int i = 0; int j = 0; char mutex_module[512] = {'\0'}; char *p = NULL; int len = 0; unsigned int val; int string_buf_avail_len = 0; DDPDUMP("== DISP Mutex Analysis ==\n"); for (i = 0; i < 5; i++) { p = mutex_module; len = 0; string_buf_avail_len = sizeof(mutex_module) - 1; if (readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, i)) == 0) continue; val = readl_relaxed(ddp->regs + DISP_REG_MUTEX_SOF(ddp->data, i)); len = snprintf(p, string_buf_avail_len, "MUTEX%d:SOF=%s,EOF=%s,WAIT=%d,module=(", i, mtk_ddp_get_mutex_sof_name( REG_FLD_VAL_GET(SOF_FLD_MUTEX0_SOF, val)), mtk_ddp_get_mutex_sof_name( REG_FLD_VAL_GET(SOF_FLD_MUTEX0_EOF, val)), REG_FLD_VAL_GET(SOF_FLD_MUTEX0_SOF_WAIT, val)); if (len >= 0 && len <= string_buf_avail_len) { p += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of mutex_module array range\n", __func__); return; } for (j = 0; j < 32; j++) { unsigned int regval = readl_relaxed( ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, i)); if ((regval & (1 << j))) { len = snprintf(p, string_buf_avail_len, "%s,", ddp_get_mutex_module0_name_mt6877(j)); if (len >= 0 && len <= string_buf_avail_len) { p += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of mutex_module array range\n", __func__); return; } } } DDPDUMP("%s)\n", mutex_module); } } void mutex_dump_analysis_mt6833(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); int i = 0; int j = 0; char mutex_module[512] = {'\0'}; char *p = NULL; int len = 0; unsigned int val; DDPDUMP("== DISP Mutex Analysis ==\n"); for (i = 0; i < 5; i++) { p = mutex_module; len = 0; if (readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, i)) == 0) continue; val = readl_relaxed(ddp->regs + DISP_REG_MUTEX_SOF(ddp->data, i)); len = sprintf(p, "MUTEX%d:SOF=%s,EOF=%s,WAIT=%d,module=(", i, mtk_ddp_get_mutex_sof_name( REG_FLD_VAL_GET(SOF_FLD_MUTEX0_SOF, val)), mtk_ddp_get_mutex_sof_name( REG_FLD_VAL_GET(SOF_FLD_MUTEX0_EOF, val)), REG_FLD_VAL_GET(SOF_FLD_MUTEX0_SOF_WAIT, val)); if (len >= 0) p += len; for (j = 0; j < 32; j++) { unsigned int regval = readl_relaxed( ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, i)); if ((regval & (1 << j))) { len = sprintf(p, "%s,", ddp_get_mutex_module0_name_mt6833(j)); if (len >= 0) p += len; } } DDPDUMP("%s)\n", mutex_module); } } void mutex_dump_analysis_mt6781(struct mtk_disp_mutex *mutex) { struct mtk_ddp *ddp = container_of(mutex, struct mtk_ddp, mutex[mutex->id]); int i = 0; int j = 0; char mutex_module[512] = {'\0'}; char *p = NULL; int len = 0; unsigned int val; int string_buf_avail_len = 0; DDPDUMP("== DISP Mutex Analysis ==\n"); for (i = 0; i < 5; i++) { p = mutex_module; len = 0; string_buf_avail_len = sizeof(mutex_module) - 1; if (readl_relaxed(ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, i)) == 0) continue; val = readl_relaxed(ddp->regs + DISP_REG_MUTEX_SOF(ddp->data, i)); len = snprintf(p, string_buf_avail_len, "MUTEX%d:SOF=%s,EOF=%s,WAIT=%d,module=(", i, mtk_ddp_get_mutex_sof_name( REG_FLD_VAL_GET(SOF_FLD_MUTEX0_SOF, val)), mtk_ddp_get_mutex_sof_name( REG_FLD_VAL_GET(SOF_FLD_MUTEX0_EOF, val)), REG_FLD_VAL_GET(SOF_FLD_MUTEX0_SOF_WAIT, val)); if (len >= 0 && len <= string_buf_avail_len) { p += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of mutex_module array range\n", __func__); return; } for (j = 0; j < 32; j++) { unsigned int regval = readl_relaxed( ddp->regs + DISP_REG_MUTEX_MOD(ddp->data, i)); if ((regval & (1 << j))) { len = snprintf(p, string_buf_avail_len, "%s,", ddp_get_mutex_module0_name_mt6781(j)); if (len >= 0 && len <= string_buf_avail_len) { p += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of mutex_module array range\n", __func__); return; } } } DDPDUMP("%s)\n", mutex_module); } } void mmsys_config_dump_reg_mt6885(void __iomem *config_regs) { unsigned int off = 0; DDPDUMP("== DISP MMSYS_CONFIG REGS ==\n"); /* TODO: use raw dump helper here */ for (off = 0x0; off <= 0x40; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); for (off = 0xF0; off <= 0x190; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); for (off = 0x1A0; off <= 0x1e0; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); for (off = 0x200; off <= 0x230; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); for (off = 0x500; off <= 0x550; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); for (off = 0x650; off <= 0x670; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); for (off = 0xE70; off <= 0xff0; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); } void mmsys_config_dump_reg_mt6873(void __iomem *config_regs) { unsigned int off = 0; DDPDUMP("== DISP MMSYS_CONFIG REGS ==\n"); /* TODO: use raw dump helper here */ for (off = 0x0; off <= 0x40; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); for (off = 0xF0; off <= 0x190; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); for (off = 0x1A0; off <= 0x1e0; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); for (off = 0x200; off <= 0x230; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); for (off = 0x500; off <= 0x550; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); for (off = 0x650; off <= 0x670; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); for (off = 0xE70; off <= 0xff0; off += 0x10) mtk_serial_dump_reg(config_regs, off, 4); } /** * ------ clock: * Before power on mmsys: * CLK_CFG_0_CLR (address is 0x10000048) = 0x80000000 (bit 31). * Before using DISP_PWM0 or DISP_PWM1: * CLK_CFG_1_CLR(address is 0x10000058)=0x80 (bit 7). * Before using DPI pixel clock: * CLK_CFG_6_CLR(address is 0x100000A8)=0x80 (bit 7). * * Only need to enable the corresponding bits of MMSYS_CG_CON0 and * MMSYS_CG_CON1 for the modules: smi_common, larb0, mdp_crop, fake_eng, * mutex_32k, pwm0, pwm1, dsi0, dsi1, dpi. * Other bits could keep 1. Suggest to keep smi_common and larb0 * always clock on. * * --------valid & ready * example: * ovl0 -> ovl0_mout_ready=1 means engines after ovl_mout are * ready for receiving data * ovl0_mout_ready=0 means ovl0_mout can not receive data, * maybe ovl0_mout or after engines config error * ovl0 -> ovl0_mout_valid=1 means engines before ovl0_mout is OK, * ovl0_mout_valid=0 means ovl can not transfer data to ovl0_mout, * means ovl0 or before engines are not ready. */ void mmsys_config_dump_analysis_mt6885(void __iomem *config_regs) { unsigned int idx = 0, bit = 0, len = 0; unsigned int reg = 0; char clock_on[512] = {'\0'}; char *pos = NULL; char *name = NULL; unsigned int valid[6] = {0}; unsigned int ready[6] = {0}; unsigned int greq = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_SMI_LARB_GREQ); valid[0] = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_DL_VALID_0); valid[1] = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_DL_VALID_1); valid[2] = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_DL_VALID_2); valid[3] = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_DL_VALID_3); valid[4] = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_DL_VALID_4); valid[5] = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_DL_VALID_5); ready[0] = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_DL_READY_0); ready[1] = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_DL_READY_1); ready[2] = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_DL_READY_2); ready[3] = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_DL_READY_3); ready[4] = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_DL_READY_4); ready[5] = readl_relaxed(config_regs + MT6885_DISP_REG_CONFIG_DL_READY_5); DDPDUMP("== DISP MMSYS_CONFIG ANALYSIS ==\n"); reg = readl_relaxed(config_regs + DISP_REG_CONFIG_MMSYS_CG_CON0_MT6885); for (bit = 0; bit < 32; bit++) { if ((reg & (1 << bit)) == 0) { name = ddp_clock_0_mt6885(bit); if (name) strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } reg = readl_relaxed(config_regs + DISP_REG_CONFIG_MMSYS_CG_CON1_MT6885); for (bit = 0; bit < 32; bit++) { if ((reg & (1 << bit)) == 0) { name = ddp_clock_1_mt6885(bit); if (name) strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } DDPDUMP("clock on modules:%s\n", clock_on); DDPDUMP("va0=0x%x,va1=0x%x,va2=0x%x,va3=0x%x,va4=0x%x,va5=0x%x\n", valid[0], valid[1], valid[2], valid[3], valid[4], valid[5]); DDPDUMP("rd0=0x%x,rd1=0x%x,rd2=0x%x,rd3=0x%x,rd4=0x%x,rd5=0x%x\n", ready[0], ready[1], ready[2], ready[3], ready[4], ready[5]); DDPDUMP("greq=0x%x\n", greq); for (idx = 0; idx < 6; idx++) { for (bit = 0; bit < 32; bit++) { name = ddp_signal_mt6885(idx, bit); if (!name) continue; pos = clock_on; if ((valid[idx] & (1 << bit))) len = sprintf(pos, "%s,", "v"); else len = sprintf(pos, "%s,", "n"); if (len >= 0) pos += len; if ((ready[idx] & (1 << bit))) len = sprintf(pos, "%s", "r"); else len = sprintf(pos, "%s", "n"); if (len >= 0) pos += len; len = sprintf(pos, ": %s", name); if (len >= 0) pos += len; DDPDUMP("%s\n", clock_on); } } /* greq: 1 means SMI dose not grant, maybe SMI hang */ if (greq) { DDPDUMP("smi greq not grant module:\n"); DDPDUMP("(greq: 1 means SMI dose not grant, maybe SMI hang)\n"); } clock_on[0] = '\0'; for (bit = 0; bit < 32; bit++) { if (greq & (1 << bit)) { name = ddp_greq_name_mt6885(bit); if (!name) continue; strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } DDPDUMP("%s\n", clock_on); } void mmsys_config_dump_analysis_mt6873(void __iomem *config_regs) { unsigned int i = 0; unsigned int reg = 0; char clock_on[512] = {'\0'}; char *pos = NULL; char *name = NULL; unsigned int valid0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_0); unsigned int valid1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_1); unsigned int valid2 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_2); unsigned int valid3 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_3); unsigned int valid4 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_4); unsigned int valid5 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_5); unsigned int ready0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_0); unsigned int ready1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_1); unsigned int ready2 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_2); unsigned int ready3 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_3); unsigned int ready4 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_4); unsigned int ready5 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_5); unsigned int greq0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_SMI_LARB0_GREQ); unsigned int greq1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_SMI_LARB1_GREQ); DDPDUMP("== DISP MMSYS_CONFIG ANALYSIS ==\n"); reg = readl_relaxed(config_regs + DISP_REG_CONFIG_MMSYS_CG_CON0_MT6873); for (i = 0; i < 32; i++) { if ((reg & (1 << i)) == 0) { name = ddp_clock_0_mt6873(i); if (name) strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } reg = readl_relaxed(config_regs + DISP_REG_CONFIG_MMSYS_CG_CON1_MT6873); for (i = 0; i < 32; i++) { if ((reg & (1 << i)) == 0) { name = ddp_clock_1_mt6873(i); if (name) strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } DDPDUMP("clock on modules:%s\n", clock_on); DDPDUMP("va0=0x%x,va1=0x%x,va2=0x%x,va3=0x%x,va4=0x%x,va5=0x%x\n", valid0, valid1, valid2, valid3, valid4, valid5); DDPDUMP("rd0=0x%x,rd1=0x%x,rd2=0x%x,rd3=0x%x,rd4=0x%x,rd5=0x%x\n", ready0, ready1, ready2, ready3, ready4, ready5); DDPDUMP("greq0=0x%x greq1=0x%x\n", greq0, greq1); for (i = 0; i < 32; i++) { name = ddp_signal_0_mt6873(i); if (!name) continue; pos = clock_on; if ((valid0 & (1 << i))) pos += sprintf(pos, "%s,", "v"); else pos += sprintf(pos, "%s,", "n"); if ((ready0 & (1 << i))) pos += sprintf(pos, "%s", "r"); else pos += sprintf(pos, "%s", "n"); pos += sprintf(pos, ": %s", name); DDPDUMP("%s\n", clock_on); } for (i = 0; i < 32; i++) { name = ddp_signal_1_mt6873(i); if (!name) continue; pos = clock_on; if ((valid1 & (1 << i))) pos += sprintf(pos, "%s,", "v"); else pos += sprintf(pos, "%s,", "n"); if ((ready1 & (1 << i))) pos += sprintf(pos, "%s", "r"); else pos += sprintf(pos, "%s", "n"); pos += sprintf(pos, ": %s", name); DDPDUMP("%s\n", clock_on); } for (i = 0; i < 32; i++) { name = ddp_signal_2_mt6873(i); if (!name) continue; pos = clock_on; if ((valid2 & (1 << i))) pos += sprintf(pos, "%s,", "v"); else pos += sprintf(pos, "%s,", "n"); if ((ready2 & (1 << i))) pos += sprintf(pos, "%s", "r"); else pos += sprintf(pos, "%s", "n"); pos += sprintf(pos, ": %s", name); DDPDUMP("%s\n", clock_on); } /* greq: 1 means SMI dose not grant, maybe SMI hang */ if (greq0) { DDPDUMP("smi larb0 greq not grant module:\n"); DDPDUMP( "(greq0: 1 means SMI dose not grant, maybe SMI larb0 hang)\n"); } if (greq1) { DDPDUMP("smi larb1 greq not grant module:\n"); DDPDUMP( "(greq1: 1 means SMI dose not grant, maybe SMI larb1 hang)\n"); } clock_on[0] = '\0'; for (i = 0; i < 32; i++) { if (greq0 & (1 << i)) { name = ddp_greq_name_larb0_mt6873(i); if (!name) continue; strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } for (i = 0; i < 32; i++) { if (greq1 & (1 << i)) { name = ddp_greq_name_larb1_mt6873(i); if (!name) continue; strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } DDPDUMP("%s\n", clock_on); #ifdef CONFIG_MTK_SMI_EXT if (greq0 || greq1) { if (!in_interrupt()) smi_debug_bus_hang_detect(false, "DISP"); else DDPDUMP("%s, Can't smi dump in IRQ\n", __func__); } #endif } void mmsys_config_dump_analysis_mt6853(void __iomem *config_regs) { unsigned int i = 0; unsigned int reg = 0; char clock_on[512] = {'\0'}; char *pos = NULL; char *name; //same address for 6853 unsigned int valid0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_0); unsigned int valid1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_1); unsigned int valid2 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_2); unsigned int valid3 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_3); unsigned int valid4 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_4); unsigned int valid5 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_5); unsigned int ready0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_0); unsigned int ready1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_1); unsigned int ready2 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_2); unsigned int ready3 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_3); unsigned int ready4 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_4); unsigned int ready5 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_5); unsigned int greq0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_SMI_LARB0_GREQ); unsigned int greq1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_SMI_LARB1_GREQ); DDPDUMP("== DISP MMSYS_CONFIG ANALYSIS ==\n"); reg = readl_relaxed(config_regs + DISP_REG_CONFIG_MMSYS_CG_CON0_MT6873); for (i = 0; i < 32; i++) { if ((reg & (1 << i)) == 0) { name = ddp_clock_0_mt6853(i); if (name) strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } DDPDUMP("clock on modules:%s\n", clock_on); DDPDUMP("va0=0x%x,va1=0x%x,va2=0x%x,va3=0x%x,va4=0x%x,va5=0x%x\n", valid0, valid1, valid2, valid3, valid4, valid5); DDPDUMP("rd0=0x%x,rd1=0x%x,rd2=0x%x,rd3=0x%x,rd4=0x%x,rd5=0x%x\n", ready0, ready1, ready2, ready3, ready4, ready5); DDPDUMP("greq0=0x%x greq1=0x%x\n", greq0, greq1); for (i = 0; i < 32; i++) { name = ddp_signal_0_mt6853(i); if (!name) continue; pos = clock_on; if ((valid0 & (1 << i))) pos += sprintf(pos, "%s,", "v"); else pos += sprintf(pos, "%s,", "n"); if ((ready0 & (1 << i))) pos += sprintf(pos, "%s", "r"); else pos += sprintf(pos, "%s", "n"); pos += sprintf(pos, ": %s", name); DDPDUMP("%s\n", clock_on); } for (i = 0; i < 32; i++) { name = ddp_signal_1_mt6853(i); if (!name) continue; pos = clock_on; if ((valid1 & (1 << i))) pos += sprintf(pos, "%s,", "v"); else pos += sprintf(pos, "%s,", "n"); if ((ready1 & (1 << i))) pos += sprintf(pos, "%s", "r"); else pos += sprintf(pos, "%s", "n"); pos += sprintf(pos, ": %s", name); DDPDUMP("%s\n", clock_on); } /* greq: 1 means SMI dose not grant, maybe SMI hang */ if (greq0) { DDPDUMP("smi larb0 greq not grant module:\n"); DDPDUMP( "(greq0: 1 means SMI dose not grant, maybe SMI larb0 hang)\n"); } if (greq1) { DDPDUMP("smi larb1 greq not grant module:\n"); DDPDUMP( "(greq1: 1 means SMI dose not grant, maybe SMI larb1 hang)\n"); } clock_on[0] = '\0'; for (i = 0; i < 32; i++) { if (greq0 & (1 << i)) { name = ddp_greq_name_larb0_mt6853(i); if (!name) continue; strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } for (i = 0; i < 32; i++) { if (greq1 & (1 << i)) { name = ddp_greq_name_larb1_mt6853(i); if (!name) continue; strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } DDPDUMP("%s\n", clock_on); #ifdef CONFIG_MTK_SMI_EXT if (greq0 || greq1) { if (!in_interrupt()) smi_debug_bus_hang_detect(false, "DISP"); else DDPDUMP("%s, Can't smi dump in IRQ\n", __func__); } #endif } void mmsys_config_dump_analysis_mt6877(void __iomem *config_regs) { unsigned int i = 0; unsigned int reg = 0; char clock_on[512] = {'\0'}; char *pos = NULL; char *name; int string_buf_avail_len = 0; int len = 0; //same address for 6853 unsigned int valid0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_0); unsigned int valid1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_1); unsigned int ready0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_0); unsigned int ready1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_1); unsigned int greq0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_SMI_LARB0_GREQ); unsigned int greq1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_SMI_LARB1_GREQ); DDPDUMP("== DISP MMSYS_CONFIG ANALYSIS ==\n"); reg = readl_relaxed(config_regs + DISP_REG_CONFIG_MMSYS_CG_CON0_MT6873); for (i = 0; i < 32; i++) { if ((reg & (1 << i)) == 0) { name = ddp_clock_0_mt6877(i); if (name) strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } DDPDUMP("clock on modules:%s\n", clock_on); DDPDUMP("va0=0x%x,va1=0x%x\n", valid0, valid1); DDPDUMP("rd0=0x%x,rd1=0x%x\n", ready0, ready1); DDPDUMP("greq0=0x%x greq1=0x%x\n", greq0, greq1); for (i = 0; i < 32; i++) { name = ddp_signal_0_mt6877(i); if (!name) continue; pos = clock_on; len = 0; string_buf_avail_len = sizeof(clock_on) - 1; if ((valid0 & (1 << i))) { len = snprintf(pos, string_buf_avail_len, "%s,", "v"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } else{ len = snprintf(pos, string_buf_avail_len, "%s,", "n"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } if ((ready0 & (1 << i))) { len = snprintf(pos, string_buf_avail_len, "%s,", "r"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } else{ len = snprintf(pos, string_buf_avail_len, "%s,", "n"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } len = snprintf(pos, string_buf_avail_len, ": %s,", name); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } DDPDUMP("%s\n", clock_on); } for (i = 0; i < 32; i++) { name = ddp_signal_1_mt6877(i); if (!name) continue; pos = clock_on; string_buf_avail_len = sizeof(clock_on) - 1; if ((valid1 & (1 << i))) { len = snprintf(pos, string_buf_avail_len, "%s,", "v"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } else{ len = snprintf(pos, string_buf_avail_len, "%s,", "n"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } if ((ready1 & (1 << i))) { len = snprintf(pos, string_buf_avail_len, "%s,", "r"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } else{ len = snprintf(pos, string_buf_avail_len, "%s,", "n"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } len = snprintf(pos, string_buf_avail_len, ": %s,", name); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } DDPDUMP("%s\n", clock_on); } /* greq: 1 means SMI dose not grant, maybe SMI hang */ if (greq0) { DDPDUMP("smi larb0 greq not grant module:\n"); DDPDUMP( "(greq0: 1 means SMI dose not grant, maybe SMI larb0 hang)\n"); } if (greq1) { DDPDUMP("smi larb1 greq not grant module:\n"); DDPDUMP( "(greq1: 1 means SMI dose not grant, maybe SMI larb1 hang)\n"); } clock_on[0] = '\0'; for (i = 0; i < 32; i++) { if (greq0 & (1 << i)) { name = ddp_greq_name_larb0_mt6877(i); if (!name) continue; strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } for (i = 0; i < 32; i++) { if (greq1 & (1 << i)) { name = ddp_greq_name_larb1_mt6877(i); if (!name) continue; strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } DDPDUMP("%s\n", clock_on); #ifdef CONFIG_MTK_SMI_EXT if (greq0 || greq1) { if (!in_interrupt()) smi_debug_bus_hang_detect(false, "DISP"); else DDPDUMP("%s, Can't smi dump in IRQ\n", __func__); } #endif } void mmsys_config_dump_analysis_mt6833(void __iomem *config_regs) { unsigned int i = 0, len = 0; unsigned int reg = 0; char clock_on[512] = {'\0'}; char *pos = NULL; char *name = NULL; unsigned int valid = 0; unsigned int ready = 0; unsigned int greq0 = 0, greq1 = 0; valid = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_0); ready = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_0); greq0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_SMI_LARB0_GREQ); greq1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_SMI_LARB1_GREQ); DDPDUMP("== DISP MMSYS_CONFIG ANALYSIS ==\n"); reg = readl_relaxed(config_regs + DISP_REG_CONFIG_MMSYS_CG_CON0_MT6873); for (i = 0; i < 32; i++) { if ((reg & (1 << i)) == 0) { name = ddp_clock_0_mt6833(i); if (name) strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } DDPDUMP("clock on modules:%s\n", clock_on); DDPDUMP("va=0x%x, rd=0x%x, greq0=0x%x, greq1=0x%x\n", valid, ready, greq0, greq1); for (i = 0; i < 32; i++) { name = ddp_signal_0_mt6833(i); if (!name) continue; pos = clock_on; if ((valid & (1 << i))) len = sprintf(pos, "%s,", "v"); else len = sprintf(pos, "%s,", "n"); if (len >= 0) pos += len; if ((ready & (1 << i))) len = sprintf(pos, "%s", "r"); else len = sprintf(pos, "%s", "n"); if (len >= 0) pos += len; len = sprintf(pos, ": %s", name); if (len >= 0) pos += len; DDPDUMP("%s\n", clock_on); } /* greq: 1 means SMI dose not grant, maybe SMI hang */ if (greq0) { DDPDUMP("smi larb0 greq not grant module:\n"); DDPDUMP( "(greq0: 1 means SMI dose not grant, maybe SMI larb0 hang)\n"); } if (greq1) { DDPDUMP("smi larb1 greq not grant module:\n"); DDPDUMP( "(greq1: 1 means SMI dose not grant, maybe SMI larb1 hang)\n"); } clock_on[0] = '\0'; for (i = 0; i < 32; i++) { if (greq0 & (1 << i)) { name = ddp_greq_name_larb0_mt6833(i); if (!name) continue; strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } for (i = 0; i < 32; i++) { if (greq1 & (1 << i)) { name = ddp_greq_name_larb1_mt6833(i); if (!name) continue; strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } DDPDUMP("%s\n", clock_on); #ifdef CONFIG_MTK_SMI_EXT if (greq0 || greq1) { if (!in_interrupt()) smi_debug_bus_hang_detect(false, "DISP"); else DDPDUMP("%s, Can't smi dump in IRQ\n", __func__); } #endif } void mmsys_config_dump_analysis_mt6781(void __iomem *config_regs) { unsigned int i = 0; unsigned int reg = 0; char clock_on[512] = {'\0'}; char *pos = NULL; char *name; int len = 0; int string_buf_avail_len = 0; //same address for 6781 unsigned int valid0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_0); unsigned int valid1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_VALID_1); unsigned int ready0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_0); unsigned int ready1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_DL_READY_1); unsigned int greq0 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_SMI_LARB0_GREQ); unsigned int greq1 = readl_relaxed(config_regs + MT6873_DISP_REG_CONFIG_SMI_LARB1_GREQ); DDPDUMP("== DISP MMSYS_CONFIG ANALYSIS ==\n"); reg = readl_relaxed(config_regs + DISP_REG_CONFIG_MMSYS_CG_CON0_MT6873); for (i = 0; i < 32; i++) { if ((reg & (1 << i)) == 0) { name = ddp_clock_0_mt6781(i); if (name) strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } DDPDUMP("clock on modules:%s\n", clock_on); DDPDUMP("va0=0x%x,va1=0x%x\n", valid0, valid1); DDPDUMP("rd0=0x%x,rd1=0x%x\n", ready0, ready1); DDPDUMP("greq0=0x%x greq1=0x%x\n", greq0, greq1); for (i = 0; i < 32; i++) { name = ddp_signal_0_mt6781(i); if (!name) continue; pos = clock_on; string_buf_avail_len = sizeof(clock_on) - 1; if ((valid0 & (1 << i))) { len = snprintf(pos, string_buf_avail_len, "%s,", "v"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } else{ len = snprintf(pos, string_buf_avail_len, "%s,", "n"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } if ((ready0 & (1 << i))) { len = snprintf(pos, string_buf_avail_len, "%s,", "r"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } else{ len = snprintf(pos, string_buf_avail_len, "%s,", "n"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } len = snprintf(pos, string_buf_avail_len, ": %s,", name); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } DDPDUMP("%s\n", clock_on); } for (i = 0; i < 32; i++) { name = ddp_signal_1_mt6781(i); if (!name) continue; pos = clock_on; string_buf_avail_len = sizeof(clock_on) - 1; if ((valid1 & (1 << i))) { len = snprintf(pos, string_buf_avail_len, "%s,", "v"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } else{ len = snprintf(pos, string_buf_avail_len, "%s,", "n"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } if ((ready1 & (1 << i))) { len = snprintf(pos, string_buf_avail_len, "%s,", "r"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } else{ len = snprintf(pos, string_buf_avail_len, "%s,", "n"); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } } len = snprintf(pos, string_buf_avail_len, ": %s,", name); if (len >= 0 && len <= string_buf_avail_len) { pos += len; string_buf_avail_len -= len; } else{ DDPPR_ERR("%s: out of clock_on array range\n", __func__); return; } DDPDUMP("%s\n", clock_on); } /* greq: 1 means SMI dose not grant, maybe SMI hang */ if (greq0) { DDPDUMP("smi larb0 greq not grant module:\n"); DDPDUMP( "(greq0: 1 means SMI dose not grant, maybe SMI larb0 hang)\n"); } if (greq1) { DDPDUMP("smi larb1 greq not grant module:\n"); DDPDUMP( "(greq1: 1 means SMI dose not grant, maybe SMI larb1 hang)\n"); } clock_on[0] = '\0'; for (i = 0; i < 32; i++) { if (greq0 & (1 << i)) { name = ddp_greq_name_larb0_mt6781(i); if (!name) continue; strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } for (i = 0; i < 32; i++) { if (greq1 & (1 << i)) { name = ddp_greq_name_larb1_mt6781(i); if (!name) continue; strncat(clock_on, name, (sizeof(clock_on) - strlen(clock_on) - 1)); } } DDPDUMP("%s\n", clock_on); #ifdef CONFIG_MTK_SMI_EXT if (greq0 || greq1) { if (!in_interrupt()) smi_debug_bus_hang_detect(false, "DISP"); else DDPDUMP("%s, Can't smi dump in IRQ\n", __func__); } #endif } static int mtk_ddp_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct mtk_ddp *ddp = NULL; struct resource *regs = NULL; int irq; int i; int ret; DDPINFO("%s+\n", __func__); ddp = devm_kzalloc(dev, sizeof(*ddp), GFP_KERNEL); if (!ddp) return -ENOMEM; irq = platform_get_irq(pdev, 0); if (irq < 0) return irq; for (i = 0; i < 10; i++) ddp->mutex[i].id = i; #ifndef CONFIG_FPGA_EARLY_PORTING if (!of_find_property(dev->of_node, "clocks", &i)) pr_info("mediatek-drm %s: has no clocks, set freerun\n", dev_name(dev)); else { ddp->clk = devm_clk_get(dev, NULL); if (IS_ERR(ddp->clk)) { pr_info("Failed to get clock\n"); return PTR_ERR(ddp->clk); } } #endif regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); ddp->regs_pa = regs->start; ddp->regs = devm_ioremap_resource(dev, regs); if (IS_ERR(ddp->regs)) { dev_err(dev, "Failed to map mutex registers\n"); return PTR_ERR(ddp->regs); } ddp->regs_pa = regs->start; ddp->data = of_device_get_match_data(dev); ddp->dev = dev; ddp->cmdq_base = cmdq_register_device(dev); ret = devm_request_irq(dev, irq, mtk_disp_mutex_irq_handler, IRQF_TRIGGER_NONE | IRQF_SHARED, dev_name(dev), ddp); if (ret < 0) { DDPAEE("%s:%d, failed to request irq:%d ret:%d\n", __func__, __LINE__, irq, ret); return ret; } pm_runtime_enable(dev); platform_set_drvdata(pdev, ddp); DDPINFO("%s-\n", __func__); return 0; } static int mtk_ddp_remove(struct platform_device *pdev) { pm_runtime_disable(&pdev->dev); return 0; } static const struct of_device_id ddp_driver_dt_match[] = { {.compatible = "mediatek,mt2701-disp-mutex", .data = &mt2701_ddp_driver_data}, {.compatible = "mediatek,mt2712-disp-mutex", .data = &mt2712_ddp_driver_data}, {.compatible = "mediatek,mt6779-disp-mutex", .data = &mt6779_ddp_driver_data}, {.compatible = "mediatek,mt6885-disp-mutex", .data = &mt6885_ddp_driver_data}, {.compatible = "mediatek,mt6873-disp-mutex", .data = &mt6873_ddp_driver_data}, {.compatible = "mediatek,mt6853-disp-mutex", .data = &mt6853_ddp_driver_data}, {.compatible = "mediatek,mt6877-disp-mutex", .data = &mt6877_ddp_driver_data}, {.compatible = "mediatek,mt6833-disp-mutex", .data = &mt6833_ddp_driver_data}, {.compatible = "mediatek,mt6781-disp-mutex", .data = &mt6781_ddp_driver_data}, {.compatible = "mediatek,mt8173-disp-mutex", .data = &mt8173_ddp_driver_data}, {}, }; MODULE_DEVICE_TABLE(of, ddp_driver_dt_match); struct platform_driver mtk_ddp_driver = { .probe = mtk_ddp_probe, .remove = mtk_ddp_remove, .driver = { .name = "mediatek-ddp", .owner = THIS_MODULE, .of_match_table = ddp_driver_dt_match, }, };