314 lines
11 KiB
Plaintext
314 lines
11 KiB
Plaintext
Broadcom iProc Family Clocks
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The iProc clock controller manages clocks that are common to the iProc family.
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An SoC from the iProc family may have several PPLs, e.g., ARMPLL, GENPLL,
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LCPLL0, MIPIPLL, and etc., all derived from an onboard crystal. Each PLL
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comprises of several leaf clocks
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Required properties for a PLL and its leaf clocks:
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- compatible:
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Should have a value of the form "brcm,<soc>-<pll>". For example, GENPLL on
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Cygnus has a compatible string of "brcm,cygnus-genpll"
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- #clock-cells:
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Have a value of <1> since there are more than 1 leaf clock of a given PLL
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- reg:
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Define the base and range of the I/O address space that contain the iProc
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clock control registers required for the PLL
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- clocks:
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The input parent clock phandle for the PLL. For most iProc PLLs, this is an
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onboard crystal with a fixed rate
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- clock-output-names:
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An ordered list of strings defining the names of the clocks
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Example:
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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genpll: genpll {
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#clock-cells = <1>;
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compatible = "brcm,cygnus-genpll";
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reg = <0x0301d000 0x2c>, <0x0301c020 0x4>;
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clocks = <&osc>;
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clock-output-names = "genpll", "axi21", "250mhz", "ihost_sys",
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"enet_sw", "audio_125", "can";
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};
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Required properties for ASIU clocks:
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ASIU clocks are a special case. These clocks are derived directly from the
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reference clock of the onboard crystal
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- compatible:
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Should have a value of the form "brcm,<soc>-asiu-clk". For example, ASIU
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clocks for Cygnus have a compatible string of "brcm,cygnus-asiu-clk"
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- #clock-cells:
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Have a value of <1> since there are more than 1 ASIU clocks
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- reg:
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Define the base and range of the I/O address space that contain the iProc
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clock control registers required for ASIU clocks
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- clocks:
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The input parent clock phandle for the ASIU clock, i.e., the onboard
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crystal
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- clock-output-names:
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An ordered list of strings defining the names of the ASIU clocks
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Example:
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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};
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asiu_clks: asiu_clks {
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#clock-cells = <1>;
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compatible = "brcm,cygnus-asiu-clk";
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reg = <0x0301d048 0xc>, <0x180aa024 0x4>;
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clocks = <&osc>;
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clock-output-names = "keypad", "adc/touch", "pwm";
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};
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Cygnus
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------
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PLL and leaf clock compatible strings for Cygnus are:
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"brcm,cygnus-armpll"
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"brcm,cygnus-genpll"
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"brcm,cygnus-lcpll0"
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"brcm,cygnus-mipipll"
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"brcm,cygnus-asiu-clk"
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"brcm,cygnus-audiopll"
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The following table defines the set of PLL/clock index and ID for Cygnus.
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These clock IDs are defined in:
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"include/dt-bindings/clock/bcm-cygnus.h"
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Clock Source (Parent) Index ID
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--- ----- ----- ---------
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crystal N/A N/A N/A
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armpll crystal N/A N/A
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keypad crystal (ASIU) 0 BCM_CYGNUS_ASIU_KEYPAD_CLK
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adc/tsc crystal (ASIU) 1 BCM_CYGNUS_ASIU_ADC_CLK
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pwm crystal (ASIU) 2 BCM_CYGNUS_ASIU_PWM_CLK
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genpll crystal 0 BCM_CYGNUS_GENPLL
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axi21 genpll 1 BCM_CYGNUS_GENPLL_AXI21_CLK
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250mhz genpll 2 BCM_CYGNUS_GENPLL_250MHZ_CLK
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ihost_sys genpll 3 BCM_CYGNUS_GENPLL_IHOST_SYS_CLK
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enet_sw genpll 4 BCM_CYGNUS_GENPLL_ENET_SW_CLK
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audio_125 genpll 5 BCM_CYGNUS_GENPLL_AUDIO_125_CLK
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can genpll 6 BCM_CYGNUS_GENPLL_CAN_CLK
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lcpll0 crystal 0 BCM_CYGNUS_LCPLL0
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pcie_phy lcpll0 1 BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK
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ddr_phy lcpll0 2 BCM_CYGNUS_LCPLL0_DDR_PHY_CLK
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sdio lcpll0 3 BCM_CYGNUS_LCPLL0_SDIO_CLK
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usb_phy lcpll0 4 BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK
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smart_card lcpll0 5 BCM_CYGNUS_LCPLL0_SMART_CARD_CLK
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ch5_unused lcpll0 6 BCM_CYGNUS_LCPLL0_CH5_UNUSED
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mipipll crystal 0 BCM_CYGNUS_MIPIPLL
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ch0_unused mipipll 1 BCM_CYGNUS_MIPIPLL_CH0_UNUSED
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ch1_lcd mipipll 2 BCM_CYGNUS_MIPIPLL_CH1_LCD
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ch2_v3d mipipll 3 BCM_CYGNUS_MIPIPLL_CH2_V3D
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ch3_unused mipipll 4 BCM_CYGNUS_MIPIPLL_CH3_UNUSED
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ch4_unused mipipll 5 BCM_CYGNUS_MIPIPLL_CH4_UNUSED
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ch5_unused mipipll 6 BCM_CYGNUS_MIPIPLL_CH5_UNUSED
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audiopll crystal 0 BCM_CYGNUS_AUDIOPLL
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ch0_audio audiopll 1 BCM_CYGNUS_AUDIOPLL_CH0
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ch1_audio audiopll 2 BCM_CYGNUS_AUDIOPLL_CH1
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ch2_audio audiopll 3 BCM_CYGNUS_AUDIOPLL_CH2
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Hurricane 2
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------
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PLL and leaf clock compatible strings for Hurricane 2 are:
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"brcm,hr2-armpll"
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The following table defines the set of PLL/clock for Hurricane 2:
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Clock Source Index ID
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--- ----- ----- ---------
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crystal N/A N/A N/A
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armpll crystal N/A N/A
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Northstar and Northstar Plus
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------
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PLL and leaf clock compatible strings for Northstar and Northstar Plus are:
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"brcm,nsp-armpll"
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"brcm,nsp-genpll"
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"brcm,nsp-lcpll0"
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The following table defines the set of PLL/clock index and ID for Northstar and
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Northstar Plus. These clock IDs are defined in:
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"include/dt-bindings/clock/bcm-nsp.h"
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Clock Source Index ID
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--- ----- ----- ---------
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crystal N/A N/A N/A
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armpll crystal N/A N/A
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genpll crystal 0 BCM_NSP_GENPLL
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phy genpll 1 BCM_NSP_GENPLL_PHY_CLK
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ethernetclk genpll 2 BCM_NSP_GENPLL_ENET_SW_CLK
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usbclk genpll 3 BCM_NSP_GENPLL_USB_PHY_REF_CLK
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iprocfast genpll 4 BCM_NSP_GENPLL_IPROCFAST_CLK
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sata1 genpll 5 BCM_NSP_GENPLL_SATA1_CLK
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sata2 genpll 6 BCM_NSP_GENPLL_SATA2_CLK
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lcpll0 crystal 0 BCM_NSP_LCPLL0
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pcie_phy lcpll0 1 BCM_NSP_LCPLL0_PCIE_PHY_REF_CLK
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sdio lcpll0 2 BCM_NSP_LCPLL0_SDIO_CLK
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ddr_phy lcpll0 3 BCM_NSP_LCPLL0_DDR_PHY_CLK
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Northstar 2
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-----------
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PLL and leaf clock compatible strings for Northstar 2 are:
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"brcm,ns2-genpll-scr"
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"brcm,ns2-genpll-sw"
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"brcm,ns2-lcpll-ddr"
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"brcm,ns2-lcpll-ports"
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The following table defines the set of PLL/clock index and ID for Northstar 2.
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These clock IDs are defined in:
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"include/dt-bindings/clock/bcm-ns2.h"
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Clock Source Index ID
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--- ----- ----- ---------
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crystal N/A N/A N/A
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genpll_scr crystal 0 BCM_NS2_GENPLL_SCR
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scr genpll_scr 1 BCM_NS2_GENPLL_SCR_SCR_CLK
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fs genpll_scr 2 BCM_NS2_GENPLL_SCR_FS_CLK
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audio_ref genpll_scr 3 BCM_NS2_GENPLL_SCR_AUDIO_CLK
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ch3_unused genpll_scr 4 BCM_NS2_GENPLL_SCR_CH3_UNUSED
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ch4_unused genpll_scr 5 BCM_NS2_GENPLL_SCR_CH4_UNUSED
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ch5_unused genpll_scr 6 BCM_NS2_GENPLL_SCR_CH5_UNUSED
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genpll_sw crystal 0 BCM_NS2_GENPLL_SW
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rpe genpll_sw 1 BCM_NS2_GENPLL_SW_RPE_CLK
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250 genpll_sw 2 BCM_NS2_GENPLL_SW_250_CLK
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nic genpll_sw 3 BCM_NS2_GENPLL_SW_NIC_CLK
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chimp genpll_sw 4 BCM_NS2_GENPLL_SW_CHIMP_CLK
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port genpll_sw 5 BCM_NS2_GENPLL_SW_PORT_CLK
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sdio genpll_sw 6 BCM_NS2_GENPLL_SW_SDIO_CLK
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lcpll_ddr crystal 0 BCM_NS2_LCPLL_DDR
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pcie_sata_usb lcpll_ddr 1 BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK
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ddr lcpll_ddr 2 BCM_NS2_LCPLL_DDR_DDR_CLK
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ch2_unused lcpll_ddr 3 BCM_NS2_LCPLL_DDR_CH2_UNUSED
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ch3_unused lcpll_ddr 4 BCM_NS2_LCPLL_DDR_CH3_UNUSED
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ch4_unused lcpll_ddr 5 BCM_NS2_LCPLL_DDR_CH4_UNUSED
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ch5_unused lcpll_ddr 6 BCM_NS2_LCPLL_DDR_CH5_UNUSED
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lcpll_ports crystal 0 BCM_NS2_LCPLL_PORTS
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wan lcpll_ports 1 BCM_NS2_LCPLL_PORTS_WAN_CLK
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rgmii lcpll_ports 2 BCM_NS2_LCPLL_PORTS_RGMII_CLK
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ch2_unused lcpll_ports 3 BCM_NS2_LCPLL_PORTS_CH2_UNUSED
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ch3_unused lcpll_ports 4 BCM_NS2_LCPLL_PORTS_CH3_UNUSED
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ch4_unused lcpll_ports 5 BCM_NS2_LCPLL_PORTS_CH4_UNUSED
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ch5_unused lcpll_ports 6 BCM_NS2_LCPLL_PORTS_CH5_UNUSED
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BCM63138
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--------
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PLL and leaf clock compatible strings for BCM63138 are:
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"brcm,bcm63138-armpll"
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Stingray
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-----------
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PLL and leaf clock compatible strings for Stingray are:
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"brcm,sr-genpll0"
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"brcm,sr-genpll1"
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"brcm,sr-genpll2"
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"brcm,sr-genpll3"
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"brcm,sr-genpll4"
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"brcm,sr-genpll5"
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"brcm,sr-genpll6"
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"brcm,sr-lcpll0"
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"brcm,sr-lcpll1"
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"brcm,sr-lcpll-pcie"
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The following table defines the set of PLL/clock index and ID for Stingray.
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These clock IDs are defined in:
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"include/dt-bindings/clock/bcm-sr.h"
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Clock Source Index ID
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--- ----- ----- ---------
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crystal N/A N/A N/A
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crmu_ref25m crystal N/A N/A
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genpll0 crystal 0 BCM_SR_GENPLL0
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clk_125m genpll0 1 BCM_SR_GENPLL0_125M_CLK
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clk_scr genpll0 2 BCM_SR_GENPLL0_SCR_CLK
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clk_250 genpll0 3 BCM_SR_GENPLL0_250M_CLK
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clk_pcie_axi genpll0 4 BCM_SR_GENPLL0_PCIE_AXI_CLK
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clk_paxc_axi_x2 genpll0 5 BCM_SR_GENPLL0_PAXC_AXI_X2_CLK
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clk_paxc_axi genpll0 6 BCM_SR_GENPLL0_PAXC_AXI_CLK
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genpll1 crystal 0 BCM_SR_GENPLL1
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clk_pcie_tl genpll1 1 BCM_SR_GENPLL1_PCIE_TL_CLK
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clk_mhb_apb genpll1 2 BCM_SR_GENPLL1_MHB_APB_CLK
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genpll2 crystal 0 BCM_SR_GENPLL2
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clk_nic genpll2 1 BCM_SR_GENPLL2_NIC_CLK
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clk_ts_500_ref genpll2 2 BCM_SR_GENPLL2_TS_500_REF_CLK
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clk_125_nitro genpll2 3 BCM_SR_GENPLL2_125_NITRO_CLK
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clk_chimp genpll2 4 BCM_SR_GENPLL2_CHIMP_CLK
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clk_nic_flash genpll2 5 BCM_SR_GENPLL2_NIC_FLASH_CLK
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clk_fs genpll2 6 BCM_SR_GENPLL2_FS_CLK
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genpll3 crystal 0 BCM_SR_GENPLL3
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clk_hsls genpll3 1 BCM_SR_GENPLL3_HSLS_CLK
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clk_sdio genpll3 2 BCM_SR_GENPLL3_SDIO_CLK
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genpll4 crystal 0 BCM_SR_GENPLL4
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clk_ccn genpll4 1 BCM_SR_GENPLL4_CCN_CLK
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clk_tpiu_pll genpll4 2 BCM_SR_GENPLL4_TPIU_PLL_CLK
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clk_noc genpll4 3 BCM_SR_GENPLL4_NOC_CLK
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clk_chclk_fs4 genpll4 4 BCM_SR_GENPLL4_CHCLK_FS4_CLK
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clk_bridge_fscpu genpll4 5 BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK
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genpll5 crystal 0 BCM_SR_GENPLL5
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clk_fs4_hf genpll5 1 BCM_SR_GENPLL5_FS4_HF_CLK
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clk_crypto_ae genpll5 2 BCM_SR_GENPLL5_CRYPTO_AE_CLK
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clk_raid_ae genpll5 3 BCM_SR_GENPLL5_RAID_AE_CLK
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genpll6 crystal 0 BCM_SR_GENPLL6
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clk_48_usb genpll6 1 BCM_SR_GENPLL6_48_USB_CLK
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lcpll0 crystal 0 BCM_SR_LCPLL0
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clk_sata_refp lcpll0 1 BCM_SR_LCPLL0_SATA_REFP_CLK
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clk_sata_refn lcpll0 2 BCM_SR_LCPLL0_SATA_REFN_CLK
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clk_sata_350 lcpll0 3 BCM_SR_LCPLL0_SATA_350_CLK
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clk_sata_500 lcpll0 4 BCM_SR_LCPLL0_SATA_500_CLK
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lcpll1 crystal 0 BCM_SR_LCPLL1
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clk_wan lcpll1 1 BCM_SR_LCPLL1_WAN_CLK
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clk_usb_ref lcpll1 2 BCM_SR_LCPLL1_USB_REF_CLK
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clk_crmu_ts lcpll1 3 BCM_SR_LCPLL1_CRMU_TS_CLK
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lcpll_pcie crystal 0 BCM_SR_LCPLL_PCIE
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clk_pcie_phy_ref lcpll1 1 BCM_SR_LCPLL_PCIE_PHY_REF_CLK
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