41 lines
1.5 KiB
Plaintext
41 lines
1.5 KiB
Plaintext
* Renesas CPG DIV6 Clock
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The CPG DIV6 clocks are variable factor clocks provided by the Clock Pulse
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Generator (CPG). Their clock input is divided by a configurable factor from 1
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to 64.
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Required Properties:
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- compatible: Must be one of the following
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- "renesas,r8a73a4-div6-clock" for R8A73A4 (R-Mobile APE6) DIV6 clocks
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- "renesas,r8a7740-div6-clock" for R8A7740 (R-Mobile A1) DIV6 clocks
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- "renesas,r8a7790-div6-clock" for R8A7790 (R-Car H2) DIV6 clocks
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- "renesas,r8a7791-div6-clock" for R8A7791 (R-Car M2-W) DIV6 clocks
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- "renesas,r8a7793-div6-clock" for R8A7793 (R-Car M2-N) DIV6 clocks
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- "renesas,r8a7794-div6-clock" for R8A7794 (R-Car E2) DIV6 clocks
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- "renesas,sh73a0-div6-clock" for SH73A0 (SH-Mobile AG5) DIV6 clocks
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and "renesas,cpg-div6-clock" as a fallback.
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- reg: Base address and length of the memory resource used by the DIV6 clock
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- clocks: Reference to the parent clock(s); either one, four, or eight
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clocks must be specified. For clocks with multiple parents, invalid
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settings must be specified as "<0>".
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- #clock-cells: Must be 0
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Optional Properties:
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- clock-output-names: The name of the clock as a free-form string
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Example
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-------
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sdhi2_clk: sdhi2_clk@e615007c {
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compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615007c 0 4>;
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clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
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<0>, <&extal2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sdhi2ck";
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};
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