42 lines
1.3 KiB
Plaintext
42 lines
1.3 KiB
Plaintext
These bindings should be considered EXPERIMENTAL for now.
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* Renesas R8A7740 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R8A7740 SoC. It includes three PLLs
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and several fixed ratio and variable ratio dividers.
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Required Properties:
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- compatible: Must be "renesas,r8a7740-cpg-clocks"
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: Reference to the three parent clocks
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are
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"system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b",
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"m1", "hp", "hpp", "usbp", "s", "zb", "m3", and "cp".
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- renesas,mode: board-specific settings of the MD_CK* bits
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Example
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-------
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7740-cpg-clocks";
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reg = <0xe6150000 0x10000>;
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clocks = <&extal1_clk>, <&extal2_clk>, <&extalr_clk>;
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#clock-cells = <1>;
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clock-output-names = "system", "pllc0", "pllc1",
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"pllc2", "r",
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"usb24s",
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"i", "zg", "b", "m1", "hp",
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"hpp", "usbp", "s", "zb", "m3",
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"cp";
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};
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&cpg_clocks {
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renesas,mode = <0x05>;
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};
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