61 lines
2 KiB
Plaintext
61 lines
2 KiB
Plaintext
* Renesas R-Car Gen2 Clock Pulse Generator (CPG)
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The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs
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and several fixed ratio dividers.
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The CPG also provides a Clock Domain for SoC devices, in combination with the
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CPG Module Stop (MSTP) Clocks.
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Required Properties:
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- compatible: Must be one of
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- "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG
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- "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG
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- "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG
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- "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG
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- "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG
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and "renesas,rcar-gen2-cpg-clocks" as a fallback.
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- reg: Base address and length of the memory resource used by the CPG
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- clocks: References to the parent clocks: first to the EXTAL clock, second
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to the USB_EXTAL clock
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- #clock-cells: Must be 1
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- clock-output-names: The names of the clocks. Supported clocks are "main",
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"pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and
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"adsp"
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- #power-domain-cells: Must be 0
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SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed
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through an MSTP clock should refer to the CPG device node in their
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"power-domains" property, as documented by the generic PM domain bindings in
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Documentation/devicetree/bindings/power/power_domain.txt.
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Examples
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--------
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- CPG device node:
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cpg_clocks: cpg_clocks@e6150000 {
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compatible = "renesas,r8a7790-cpg-clocks",
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"renesas,rcar-gen2-cpg-clocks";
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reg = <0 0xe6150000 0 0x1000>;
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clocks = <&extal_clk &usb_extal_clk>;
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#clock-cells = <1>;
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clock-output-names = "main", "pll0, "pll1", "pll3",
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"lb", "qspi", "sdh", "sd0", "sd1", "z",
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"rcan", "adsp";
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#power-domain-cells = <0>;
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};
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- CPG/MSTP Clock Domain member device node:
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thermal@e61f0000 {
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compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
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reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
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interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
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power-domains = <&cpg_clocks>;
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};
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