29 lines
1,006 B
Plaintext
29 lines
1,006 B
Plaintext
Allwinner A80 Display Engine Clock Control Binding
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--------------------------------------------------
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Required properties :
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- compatible: must contain one of the following compatibles:
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- "allwinner,sun9i-a80-de-clks"
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- reg: Must contain the registers base address and length
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- clocks: phandle to the clocks feeding the display engine subsystem.
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Three are needed:
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- "mod": the display engine module clock
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- "dram": the DRAM bus clock for the system
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- "bus": the bus clock for the whole display engine subsystem
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- clock-names: Must contain the clock names described just above
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- resets: phandle to the reset control for the display engine subsystem.
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- #clock-cells : must contain 1
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- #reset-cells : must contain 1
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Example:
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de_clocks: clock@3000000 {
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compatible = "allwinner,sun9i-a80-de-clks";
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reg = <0x03000000 0x30>;
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clocks = <&ccu CLK_DE>, <&ccu CLK_SDRAM>, <&ccu CLK_BUS_DE>;
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clock-names = "mod", "dram", "bus";
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resets = <&ccu RST_BUS_DE>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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