139 lines
3.5 KiB
Plaintext
139 lines
3.5 KiB
Plaintext
* Qualcomm NAND controller
|
|
|
|
Required properties:
|
|
- compatible: must be one of the following:
|
|
* "qcom,ipq806x-nand" - for EBI2 NAND controller being used in IPQ806x
|
|
SoC and it uses ADM DMA
|
|
* "qcom,ipq4019-nand" - for QPIC NAND controller v1.4.0 being used in
|
|
IPQ4019 SoC and it uses BAM DMA
|
|
* "qcom,ipq8074-nand" - for QPIC NAND controller v1.5.0 being used in
|
|
IPQ8074 SoC and it uses BAM DMA
|
|
|
|
- reg: MMIO address range
|
|
- clocks: must contain core clock and always on clock
|
|
- clock-names: must contain "core" for the core clock and "aon" for the
|
|
always on clock
|
|
|
|
EBI2 specific properties:
|
|
- dmas: DMA specifier, consisting of a phandle to the ADM DMA
|
|
controller node and the channel number to be used for
|
|
NAND. Refer to dma.txt and qcom_adm.txt for more details
|
|
- dma-names: must be "rxtx"
|
|
- qcom,cmd-crci: must contain the ADM command type CRCI block instance
|
|
number specified for the NAND controller on the given
|
|
platform
|
|
- qcom,data-crci: must contain the ADM data type CRCI block instance
|
|
number specified for the NAND controller on the given
|
|
platform
|
|
|
|
QPIC specific properties:
|
|
- dmas: DMA specifier, consisting of a phandle to the BAM DMA
|
|
and the channel number to be used for NAND. Refer to
|
|
dma.txt, qcom_bam_dma.txt for more details
|
|
- dma-names: must contain all 3 channel names : "tx", "rx", "cmd"
|
|
- #address-cells: <1> - subnodes give the chip-select number
|
|
- #size-cells: <0>
|
|
|
|
* NAND chip-select
|
|
|
|
Each controller may contain one or more subnodes to represent enabled
|
|
chip-selects which (may) contain NAND flash chips. Their properties are as
|
|
follows.
|
|
|
|
Required properties:
|
|
- reg: a single integer representing the chip-select
|
|
number (e.g., 0, 1, 2, etc.)
|
|
- #address-cells: see partition.txt
|
|
- #size-cells: see partition.txt
|
|
|
|
Optional properties:
|
|
- nand-bus-width: see nand.txt
|
|
- nand-ecc-strength: see nand.txt. If not specified, then ECC strength will
|
|
be used according to chip requirement and available
|
|
OOB size.
|
|
|
|
Each nandcs device node may optionally contain a 'partitions' sub-node, which
|
|
further contains sub-nodes describing the flash partition mapping. See
|
|
partition.txt for more detail.
|
|
|
|
Example:
|
|
|
|
nand-controller@1ac00000 {
|
|
compatible = "qcom,ipq806x-nand";
|
|
reg = <0x1ac00000 0x800>;
|
|
|
|
clocks = <&gcc EBI2_CLK>,
|
|
<&gcc EBI2_AON_CLK>;
|
|
clock-names = "core", "aon";
|
|
|
|
dmas = <&adm_dma 3>;
|
|
dma-names = "rxtx";
|
|
qcom,cmd-crci = <15>;
|
|
qcom,data-crci = <3>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
nand@0 {
|
|
reg = <0>;
|
|
|
|
nand-ecc-strength = <4>;
|
|
nand-bus-width = <8>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "boot-nand";
|
|
reg = <0 0x58a0000>;
|
|
};
|
|
|
|
partition@58a0000 {
|
|
label = "fs-nand";
|
|
reg = <0x58a0000 0x4000000>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
nand-controller@79b0000 {
|
|
compatible = "qcom,ipq4019-nand";
|
|
reg = <0x79b0000 0x1000>;
|
|
|
|
clocks = <&gcc GCC_QPIC_CLK>,
|
|
<&gcc GCC_QPIC_AHB_CLK>;
|
|
clock-names = "core", "aon";
|
|
|
|
dmas = <&qpicbam 0>,
|
|
<&qpicbam 1>,
|
|
<&qpicbam 2>;
|
|
dma-names = "tx", "rx", "cmd";
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
nand@0 {
|
|
reg = <0>;
|
|
nand-ecc-strength = <4>;
|
|
nand-bus-width = <8>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "boot-nand";
|
|
reg = <0 0x58a0000>;
|
|
};
|
|
|
|
partition@58a0000 {
|
|
label = "fs-nand";
|
|
reg = <0x58a0000 0x4000000>;
|
|
};
|
|
};
|
|
};
|
|
};
|