92 lines
3.2 KiB
Plaintext
92 lines
3.2 KiB
Plaintext
APM X-Gene SoC Ethernet nodes
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Ethernet nodes are defined to describe on-chip ethernet interfaces in
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APM X-Gene SoC.
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Required properties for all the ethernet interfaces:
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- compatible: Should state binding information from the following list,
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- "apm,xgene-enet": RGMII based 1G interface
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- "apm,xgene1-sgenet": SGMII based 1G interface
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- "apm,xgene1-xgenet": XFI based 10G interface
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- reg: Address and length of the register set for the device. It contains the
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information of registers in the same order as described by reg-names
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- reg-names: Should contain the register set names
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- "enet_csr": Ethernet control and status register address space
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- "ring_csr": Descriptor ring control and status register address space
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- "ring_cmd": Descriptor ring command register address space
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- interrupts: Two interrupt specifiers can be specified.
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- First is the Rx interrupt. This irq is mandatory.
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- Second is the Tx completion interrupt.
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This is supported only on SGMII based 1GbE and 10GbE interfaces.
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- channel: Ethernet to CPU, start channel (prefetch buffer) number
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- Must map to the first irq and irqs must be sequential
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- port-id: Port number (0 or 1)
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- clocks: Reference to the clock entry.
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- local-mac-address: MAC address assigned to this device
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- phy-connection-type: Interface type between ethernet device and PHY device
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Required properties for ethernet interfaces that have external PHY:
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- phy-handle: Reference to a PHY node connected to this device
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- mdio: Device tree subnode with the following required properties:
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- compatible: Must be "apm,xgene-mdio".
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- #address-cells: Must be <1>.
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- #size-cells: Must be <0>.
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For the phy on the mdio bus, there must be a node with the following fields:
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- compatible: PHY identifier. Please refer ./phy.txt for the format.
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- reg: The ID number for the phy.
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Optional properties:
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- status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok".
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- tx-delay: Delay value for RGMII bridge TX clock.
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Valid values are between 0 to 7, that maps to
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417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps
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Default value is 4, which corresponds to 1611 ps
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- rx-delay: Delay value for RGMII bridge RX clock.
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Valid values are between 0 to 7, that maps to
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273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps
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Default value is 2, which corresponds to 899 ps
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- rxlos-gpios: Input gpio from SFP+ module to indicate availability of
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incoming signal.
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Example:
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menetclk: menetclk {
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compatible = "apm,xgene-device-clock";
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clock-output-names = "menetclk";
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status = "ok";
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};
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menet: ethernet@17020000 {
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compatible = "apm,xgene-enet";
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status = "disabled";
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reg = <0x0 0x17020000 0x0 0xd100>,
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<0x0 0x17030000 0x0 0x400>,
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<0x0 0x10000000 0x0 0x200>;
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reg-names = "enet_csr", "ring_csr", "ring_cmd";
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interrupts = <0x0 0x3c 0x4>;
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port-id = <0>;
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clocks = <&menetclk 0>;
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local-mac-address = [00 01 73 00 00 01];
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phy-connection-type = "rgmii";
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phy-handle = <&menetphy>;
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mdio {
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compatible = "apm,xgene-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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menetphy: menetphy@3 {
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compatible = "ethernet-phy-id001c.c915";
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reg = <0x3>;
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};
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};
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};
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/* Board-specific peripheral configurations */
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&menet {
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tx-delay = <4>;
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rx-delay = <2>;
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status = "ok";
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};
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