94 lines
3.9 KiB
Plaintext
94 lines
3.9 KiB
Plaintext
* Freescale IOMUX Controller (IOMUXC) for i.MX
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The IOMUX Controller (IOMUXC), together with the IOMUX, enables the IC
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to share one PAD to several functional blocks. The sharing is done by
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multiplexing the PAD input/output signals. For each PAD there are up to
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8 muxing options (called ALT modes). Since different modules require
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different PAD settings (like pull up, keeper, etc) the IOMUXC controls
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also the PAD settings parameters.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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Freescale IMX pin configuration node is a node of a group of pins which can be
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used for a specific device or function. This node represents both mux and config
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of the pins in that group. The 'mux' selects the function mode(also named mux
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mode) this pin can work on and the 'config' configures various pad settings
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such as pull-up, open drain, drive strength, etc.
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Required properties for iomux controller:
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- compatible: "fsl,<soc>-iomuxc"
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Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
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Required properties for pin configuration node:
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- fsl,pins: each entry consists of 6 integers and represents the mux and config
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setting for one pin. The first 5 integers <mux_reg conf_reg input_reg mux_val
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input_val> are specified using a PIN_FUNC_ID macro, which can be found in
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imx*-pinfunc.h under device tree source folder. The last integer CONFIG is
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the pad setting value like pull-up on this pin. And that's why fsl,pins entry
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looks like <PIN_FUNC_ID CONFIG> in the example below.
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Bits used for CONFIG:
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NO_PAD_CTL(1 << 31): indicate this pin does not need config.
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SION(1 << 30): Software Input On Field.
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Force the selected mux mode input path no matter of MUX_MODE functionality.
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By default the input path is determined by functionality of the selected
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mux mode (regular).
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Other bits are used for PAD setting.
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Please refer to each fsl,<soc>-pinctrl,txt binding doc for SoC specific part
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of bits definitions.
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NOTE:
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Some requirements for using fsl,imx-pinctrl binding:
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1. We have pin function node defined under iomux controller node to represent
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what pinmux functions this SoC supports.
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2. The pin configuration node intends to work on a specific function should
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to be defined under that specific function node.
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The function node's name should represent well about what function
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this group of pins in this pin configuration node are working on.
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3. The driver can use the function node's name and pin configuration node's
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name describe the pin function and group hierarchy.
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For example, Linux IMX pinctrl driver takes the function node's name
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as the function name and pin configuration node's name as group name to
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create the map table.
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4. Each pin configuration node should have a phandle, devices can set pins
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configurations by referring to the phandle of that pin configuration node.
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Examples:
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usdhc@219c000 { /* uSDHC4 */
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non-removable;
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vmmc-supply = <®_3p3v>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usdhc4_1>;
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};
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iomuxc@20e0000 {
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compatible = "fsl,imx6q-iomuxc";
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reg = <0x020e0000 0x4000>;
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/* shared pinctrl settings */
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usdhc4 {
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pinctrl_usdhc4_1: usdhc4grp-1 {
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fsl,pins = <
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MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
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MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
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MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
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MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
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MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
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MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
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MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
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MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
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MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
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MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
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>;
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};
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....
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};
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Refer to the IOMUXC controller chapter in imx6q datasheet,
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0x17059 means enable hysteresis, 47KOhm Pull Up, 50Mhz speed,
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80Ohm driver strength and Fast Slew Rate.
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User should refer to each SoC spec to set the correct value.
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