62 lines
1.7 KiB
Plaintext
62 lines
1.7 KiB
Plaintext
* Freescale i.MX7ULP IOMUX Controller
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i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
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ports and IOMUXC DDR for DDR interface.
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Note:
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This binding doc is only for the IOMUXC1 support in A7 Domain and it only
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supports generic pin config.
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Please also refer pinctrl-bindings.txt in this directory for generic pinctrl
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binding.
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=== Pin Controller Node ===
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Required properties:
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- compatible: "fsl,imx7ulp-iomuxc1"
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- reg: Should contain the base physical address and size of the iomuxc
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registers.
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=== Pin Configuration Node ===
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- pinmux: One integers array, represents a group of pins mux setting.
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The format is pinmux = <PIN_FUNC_ID>, PIN_FUNC_ID is a pin working on
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a specific function.
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NOTE: i.MX7ULP PIN_FUNC_ID consists of 4 integers as it shares one mux
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and config register as follows:
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<mux_conf_reg input_reg mux_mode input_val>
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Refer to imx7ulp-pinfunc.h in in device tree source folder for all
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available imx7ulp PIN_FUNC_ID.
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Optional Properties:
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- drive-strength Integer. Controls Drive Strength
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0: Standard
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1: Hi Driver
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- drive-push-pull Bool. Enable Pin Push-pull
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- drive-open-drain Bool. Enable Pin Open-drian
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- slew-rate: Integer. Controls Slew Rate
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0: Standard
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1: Slow
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- bias-disable: Bool. Pull disabled
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- bias-pull-down: Bool. Pull down on pin
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- bias-pull-up: Bool. Pull up on pin
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Examples:
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#include "imx7ulp-pinfunc.h"
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/* Pin Controller Node */
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iomuxc1: iomuxc@40ac0000 {
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compatible = "fsl,imx7ulp-iomuxc1";
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reg = <0x40ac0000 0x1000>;
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/* Pin Configuration Node */
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pinctrl_lpuart4: lpuart4grp {
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pinmux = <
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IMX7ULP_PAD_PTC3__LPUART4_RX
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IMX7ULP_PAD_PTC2__LPUART4_TX
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>;
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bias-pull-up;
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};
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};
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