102 lines
3.3 KiB
Plaintext
102 lines
3.3 KiB
Plaintext
Qualcomm IPQ8064 TLMM block
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Required properties:
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- compatible: "qcom,ipq8064-pinctrl"
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- reg: Should be the base address and length of the TLMM block.
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- interrupts: Should be the parent IRQ of the TLMM block.
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- interrupt-controller: Marks the device node as an interrupt controller.
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- #interrupt-cells: Should be two.
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- gpio-controller: Marks the device node as a GPIO controller.
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- #gpio-cells : Should be two.
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The first cell is the gpio pin number and the
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second cell is used for optional parameters.
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- gpio-ranges: see ../gpio/gpio.txt
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Optional properties:
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- gpio-reserved-ranges: see ../gpio/gpio.txt
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Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
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a general description of GPIO and interrupt bindings.
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Please refer to pinctrl-bindings.txt in this directory for details of the
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common pinctrl bindings used by client devices, including the meaning of the
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phrase "pin configuration node".
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Qualcomm's pin configuration nodes act as a container for an arbitrary number of
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subnodes. Each of these subnodes represents some desired configuration for a
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pin, a group, or a list of pins or groups. This configuration can include the
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mux function to select on those pin(s)/group(s), and various pin configuration
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parameters, such as pull-up, drive strength, etc.
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The name of each subnode is not important; all subnodes should be enumerated
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and processed purely based on their content.
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Each subnode only affects those parameters that are explicitly listed. In
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other words, a subnode that lists a mux function but no pin configuration
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parameters implies no information about any pin configuration parameters.
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Similarly, a pin subnode that describes a pullup parameter implies no
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information about e.g. the mux function.
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The following generic properties as defined in pinctrl-bindings.txt are valid
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to specify in a pin configuration subnode:
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pins, function, bias-disable, bias-pull-down, bias-pull,up, drive-strength,
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output-low, output-high.
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Non-empty subnodes must specify the 'pins' property.
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Valid values for qcom,pins are:
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gpio0-gpio68
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Supports mux, bias, and drive-strength
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sdc3_clk, sdc3_cmd, sdc3_data
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Supports bias and drive-strength
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Valid values for function are:
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mdio, mi2s, pdm, ssbi, spmi, audio_pcm, gpio, gsbi1, gsbi2, gsbi4, gsbi5,
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gsbi5_spi_cs1, gsbi5_spi_cs2, gsbi5_spi_cs3, gsbi6, gsbi7, nss_spi, sdc1,
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spdif, nand, tsif1, tsif2, usb_fs_n, usb_fs, usb2_hsic, rgmii2, sata,
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pcie1_rst, pcie1_prsnt, pcie1_pwren_n, pcie1_pwren, pcie1_pwrflt,
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pcie1_clk_req, pcie2_rst, pcie2_prsnt, pcie2_pwren_n, pcie2_pwren,
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pcie2_pwrflt, pcie2_clk_req, pcie3_rst, pcie3_prsnt, pcie3_pwren_n,
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pcie3_pwren, pcie3_pwrflt, pcie3_clk_req, ps_hold
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Example:
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pinmux: pinctrl@800000 {
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compatible = "qcom,ipq8064-pinctrl";
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reg = <0x800000 0x4000>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinmux 0 0 69>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <0 32 0x4>;
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pinctrl-names = "default";
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pinctrl-0 = <&gsbi5_uart_default>;
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gsbi5_uart_default: gsbi5_uart_default {
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mux {
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pins = "gpio18", "gpio19";
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function = "gsbi5";
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};
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tx {
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pins = "gpio18";
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drive-strength = <4>;
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bias-disable;
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};
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rx {
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pins = "gpio19";
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drive-strength = <2>;
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bias-pull-up;
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};
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};
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};
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