47 lines
1.9 KiB
Plaintext
47 lines
1.9 KiB
Plaintext
* Atmel I2S controller
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Required properties:
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- compatible: Should be "atmel,sama5d2-i2s".
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- reg: Should be the physical base address of the controller and the
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length of memory mapped region.
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- interrupts: Should contain the interrupt for the controller.
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- dmas: Should be one per channel name listed in the dma-names property,
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as described in atmel-dma.txt and dma.txt files.
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- dma-names: Two dmas have to be defined, "tx" and "rx".
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This IP also supports one shared channel for both rx and tx;
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if this mode is used, one "rx-tx" name must be used.
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- clocks: Must contain an entry for each entry in clock-names.
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Please refer to clock-bindings.txt.
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- clock-names: Should be one of each entry matching the clocks phandles list:
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- "pclk" (peripheral clock) Required.
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- "gclk" (generated clock) Optional (1).
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- "muxclk" (I2S mux clock) Optional (1).
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Optional properties:
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- pinctrl-0: Should specify pin control groups used for this controller.
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- princtrl-names: Should contain only one value - "default".
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(1) : Only the peripheral clock is required. The generated clock and the I2S
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mux clock are optional and should only be set together, when Master Mode
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is required.
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Example:
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i2s@f8050000 {
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compatible = "atmel,sama5d2-i2s";
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reg = <0xf8050000 0x300>;
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interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
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dmas = <&dma0
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(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
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AT91_XDMAC_DT_PERID(31))>,
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<&dma0
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(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
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AT91_XDMAC_DT_PERID(32))>;
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dma-names = "tx", "rx";
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clocks = <&i2s0_clk>, <&i2s0_gclk>, <&i2s0muxck>;
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clock-names = "pclk", "gclk", "muxclk";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2s0_default>;
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};
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