104 lines
2.8 KiB
C
104 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
#ifndef __ASM_BARRIER_H
|
|
#define __ASM_BARRIER_H
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
|
|
|
|
#if __LINUX_ARM_ARCH__ >= 7 || \
|
|
(__LINUX_ARM_ARCH__ == 6 && defined(CONFIG_CPU_32v6K))
|
|
#define sev() __asm__ __volatile__ ("sev" : : : "memory")
|
|
#define wfe() __asm__ __volatile__ ("wfe" : : : "memory")
|
|
#define wfi() __asm__ __volatile__ ("wfi" : : : "memory")
|
|
#else
|
|
#define wfe() do { } while (0)
|
|
#endif
|
|
|
|
#if __LINUX_ARM_ARCH__ >= 7
|
|
#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")
|
|
#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")
|
|
#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")
|
|
#ifdef CONFIG_THUMB2_KERNEL
|
|
#define CSDB ".inst.w 0xf3af8014"
|
|
#else
|
|
#define CSDB ".inst 0xe320f014"
|
|
#endif
|
|
#define csdb() __asm__ __volatile__(CSDB : : : "memory")
|
|
#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6
|
|
#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
|
|
: : "r" (0) : "memory")
|
|
#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
|
|
: : "r" (0) : "memory")
|
|
#define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \
|
|
: : "r" (0) : "memory")
|
|
#elif defined(CONFIG_CPU_FA526)
|
|
#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \
|
|
: : "r" (0) : "memory")
|
|
#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
|
|
: : "r" (0) : "memory")
|
|
#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
|
|
#else
|
|
#define isb(x) __asm__ __volatile__ ("" : : : "memory")
|
|
#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \
|
|
: : "r" (0) : "memory")
|
|
#define dmb(x) __asm__ __volatile__ ("" : : : "memory")
|
|
#endif
|
|
|
|
#ifndef CSDB
|
|
#define CSDB
|
|
#endif
|
|
#ifndef csdb
|
|
#define csdb()
|
|
#endif
|
|
|
|
#ifdef CONFIG_ARM_HEAVY_MB
|
|
extern void (*soc_mb)(void);
|
|
extern void arm_heavy_mb(void);
|
|
#define __arm_heavy_mb(x...) do { dsb(x); arm_heavy_mb(); } while (0)
|
|
#else
|
|
#define __arm_heavy_mb(x...) dsb(x)
|
|
#endif
|
|
|
|
#if defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)
|
|
#define mb() __arm_heavy_mb()
|
|
#define rmb() dsb()
|
|
#define wmb() __arm_heavy_mb(st)
|
|
#define dma_rmb() dmb(osh)
|
|
#define dma_wmb() dmb(oshst)
|
|
#else
|
|
#define mb() barrier()
|
|
#define rmb() barrier()
|
|
#define wmb() barrier()
|
|
#define dma_rmb() barrier()
|
|
#define dma_wmb() barrier()
|
|
#endif
|
|
|
|
#define __smp_mb() dmb(ish)
|
|
#define __smp_rmb() __smp_mb()
|
|
#define __smp_wmb() dmb(ishst)
|
|
|
|
#ifdef CONFIG_CPU_SPECTRE
|
|
static inline unsigned long array_index_mask_nospec(unsigned long idx,
|
|
unsigned long sz)
|
|
{
|
|
unsigned long mask;
|
|
|
|
asm volatile(
|
|
"cmp %1, %2\n"
|
|
" sbc %0, %1, %1\n"
|
|
CSDB
|
|
: "=r" (mask)
|
|
: "r" (idx), "Ir" (sz)
|
|
: "cc");
|
|
|
|
return mask;
|
|
}
|
|
#define array_index_mask_nospec array_index_mask_nospec
|
|
#endif
|
|
|
|
#include <asm-generic/barrier.h>
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
#endif /* __ASM_BARRIER_H */
|