152 lines
3.7 KiB
Plaintext
152 lines
3.7 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Freescale Layerscape-2080A family SoC.
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*
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* Copyright 2014-2016 Freescale Semiconductor, Inc.
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*
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* Abhimanyu Saini <abhimanyu.saini@nxp.com>
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* Bhupesh Sharma <bhupesh.sharma@freescale.com>
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*
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*/
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#include "fsl-ls208xa.dtsi"
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&cpu {
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x0>;
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clocks = <&clockgen 1 0>;
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cpu-idle-states = <&CPU_PW20>;
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next-level-cache = <&cluster0_l2>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x1>;
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clocks = <&clockgen 1 0>;
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cpu-idle-states = <&CPU_PW20>;
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next-level-cache = <&cluster0_l2>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x100>;
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clocks = <&clockgen 1 1>;
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cpu-idle-states = <&CPU_PW20>;
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next-level-cache = <&cluster1_l2>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@101 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x101>;
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clocks = <&clockgen 1 1>;
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cpu-idle-states = <&CPU_PW20>;
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next-level-cache = <&cluster1_l2>;
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#cooling-cells = <2>;
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};
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cpu4: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x200>;
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clocks = <&clockgen 1 2>;
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cpu-idle-states = <&CPU_PW20>;
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next-level-cache = <&cluster2_l2>;
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#cooling-cells = <2>;
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};
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cpu5: cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x201>;
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clocks = <&clockgen 1 2>;
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cpu-idle-states = <&CPU_PW20>;
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next-level-cache = <&cluster2_l2>;
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#cooling-cells = <2>;
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};
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cpu6: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x300>;
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clocks = <&clockgen 1 3>;
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next-level-cache = <&cluster3_l2>;
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cpu-idle-states = <&CPU_PW20>;
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#cooling-cells = <2>;
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};
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cpu7: cpu@301 {
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device_type = "cpu";
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compatible = "arm,cortex-a57";
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reg = <0x301>;
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clocks = <&clockgen 1 3>;
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cpu-idle-states = <&CPU_PW20>;
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next-level-cache = <&cluster3_l2>;
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#cooling-cells = <2>;
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};
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cluster0_l2: l2-cache0 {
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compatible = "cache";
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};
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cluster1_l2: l2-cache1 {
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compatible = "cache";
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};
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cluster2_l2: l2-cache2 {
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compatible = "cache";
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};
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cluster3_l2: l2-cache3 {
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compatible = "cache";
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};
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CPU_PW20: cpu-pw20 {
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compatible = "arm,idle-state";
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idle-state-name = "PW20";
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arm,psci-suspend-param = <0x00010000>;
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entry-latency-us = <2000>;
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exit-latency-us = <2000>;
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min-residency-us = <6000>;
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};
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};
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&pcie1 {
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reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
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0x10 0x00000000 0x0 0x00002000>; /* configuration space */
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ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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&pcie2 {
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reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
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0x12 0x00000000 0x0 0x00002000>; /* configuration space */
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ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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&pcie3 {
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reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
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0x14 0x00000000 0x0 0x00002000>; /* configuration space */
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ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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&pcie4 {
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reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */
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0x16 0x00000000 0x0 0x00002000>; /* configuration space */
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ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */
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0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
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};
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