501 lines
14 KiB
Plaintext
501 lines
14 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (C) 2016 Marvell Technology Group Ltd.
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*
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* Device Tree file for Marvell Armada CP110.
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*/
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#include <dt-bindings/interrupt-controller/mvebu-icu.h>
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#include "armada-common.dtsi"
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#define CP110_PCIEx_IO_BASE(iface) (CP110_PCIE_IO_BASE + (iface * 0x10000))
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#define CP110_PCIEx_MEM_BASE(iface) (CP110_PCIE_MEM_BASE + (iface * 0x1000000))
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#define CP110_PCIEx_CONF_BASE(iface) (CP110_PCIEx_MEM_BASE(iface) + 0xf00000)
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/ {
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/*
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* The contents of the node are defined below, in order to
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* save one indentation level
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*/
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CP110_NAME: CP110_NAME { };
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};
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&CP110_NAME {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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interrupt-parent = <&CP110_LABEL(icu)>;
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ranges;
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config-space@CP110_BASE {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges = <0x0 0x0 ADDRESSIFY(CP110_BASE) 0x2000000>;
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CP110_LABEL(ethernet): ethernet@0 {
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compatible = "marvell,armada-7k-pp22";
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reg = <0x0 0x100000>, <0x129000 0xb000>;
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clocks = <&CP110_LABEL(clk) 1 3>, <&CP110_LABEL(clk) 1 9>,
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<&CP110_LABEL(clk) 1 5>, <&CP110_LABEL(clk) 1 6>,
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<&CP110_LABEL(clk) 1 18>;
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clock-names = "pp_clk", "gop_clk",
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"mg_clk", "mg_core_clk", "axi_clk";
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marvell,system-controller = <&CP110_LABEL(syscon0)>;
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status = "disabled";
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dma-coherent;
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CP110_LABEL(eth0): eth0 {
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interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 43 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 47 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 51 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 55 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 129 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
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"tx-cpu3", "rx-shared", "link";
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port-id = <0>;
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gop-port-id = <0>;
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status = "disabled";
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};
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CP110_LABEL(eth1): eth1 {
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interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 44 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 48 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 52 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 56 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 128 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
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"tx-cpu3", "rx-shared", "link";
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port-id = <1>;
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gop-port-id = <2>;
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status = "disabled";
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};
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CP110_LABEL(eth2): eth2 {
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interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 45 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 49 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 53 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 57 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 127 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "tx-cpu0", "tx-cpu1", "tx-cpu2",
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"tx-cpu3", "rx-shared", "link";
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port-id = <2>;
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gop-port-id = <3>;
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status = "disabled";
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};
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};
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CP110_LABEL(comphy): phy@120000 {
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compatible = "marvell,comphy-cp110";
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reg = <0x120000 0x6000>;
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marvell,system-controller = <&CP110_LABEL(syscon0)>;
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#address-cells = <1>;
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#size-cells = <0>;
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CP110_LABEL(comphy0): phy@0 {
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reg = <0>;
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#phy-cells = <1>;
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};
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CP110_LABEL(comphy1): phy@1 {
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reg = <1>;
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#phy-cells = <1>;
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};
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CP110_LABEL(comphy2): phy@2 {
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reg = <2>;
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#phy-cells = <1>;
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};
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CP110_LABEL(comphy3): phy@3 {
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reg = <3>;
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#phy-cells = <1>;
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};
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CP110_LABEL(comphy4): phy@4 {
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reg = <4>;
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#phy-cells = <1>;
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};
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CP110_LABEL(comphy5): phy@5 {
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reg = <5>;
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#phy-cells = <1>;
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};
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};
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CP110_LABEL(mdio): mdio@12a200 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,orion-mdio";
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reg = <0x12a200 0x10>;
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clocks = <&CP110_LABEL(clk) 1 9>, <&CP110_LABEL(clk) 1 5>,
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<&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
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status = "disabled";
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};
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CP110_LABEL(xmdio): mdio@12a600 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "marvell,xmdio";
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reg = <0x12a600 0x10>;
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clocks = <&CP110_LABEL(clk) 1 5>,
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<&CP110_LABEL(clk) 1 6>, <&CP110_LABEL(clk) 1 18>;
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status = "disabled";
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};
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CP110_LABEL(icu): interrupt-controller@1e0000 {
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compatible = "marvell,cp110-icu";
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reg = <0x1e0000 0x440>;
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#interrupt-cells = <3>;
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interrupt-controller;
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msi-parent = <&gicp>;
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};
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CP110_LABEL(rtc): rtc@284000 {
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compatible = "marvell,armada-8k-rtc";
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reg = <0x284000 0x20>, <0x284080 0x24>;
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reg-names = "rtc", "rtc-soc";
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interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
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};
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CP110_LABEL(thermal): thermal@400078 {
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compatible = "marvell,armada-cp110-thermal";
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reg = <0x400078 0x4>,
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<0x400070 0x8>;
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};
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CP110_LABEL(syscon0): system-controller@440000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x440000 0x2000>;
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CP110_LABEL(clk): clock {
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compatible = "marvell,cp110-clock";
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#clock-cells = <2>;
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};
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CP110_LABEL(gpio1): gpio@100 {
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compatible = "marvell,armada-8k-gpio";
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offset = <0x100>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&CP110_LABEL(pinctrl) 0 0 32>;
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interrupt-controller;
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interrupts = <ICU_GRP_NSR 86 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 85 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 84 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 83 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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CP110_LABEL(gpio2): gpio@140 {
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compatible = "marvell,armada-8k-gpio";
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offset = <0x140>;
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ngpios = <31>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&CP110_LABEL(pinctrl) 0 32 31>;
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interrupt-controller;
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interrupts = <ICU_GRP_NSR 82 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 81 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 80 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 79 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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};
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CP110_LABEL(usb3_0): usb3@500000 {
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compatible = "marvell,armada-8k-xhci",
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"generic-xhci";
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reg = <0x500000 0x4000>;
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dma-coherent;
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interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core", "reg";
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clocks = <&CP110_LABEL(clk) 1 22>,
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<&CP110_LABEL(clk) 1 16>;
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status = "disabled";
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};
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CP110_LABEL(usb3_1): usb3@510000 {
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compatible = "marvell,armada-8k-xhci",
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"generic-xhci";
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reg = <0x510000 0x4000>;
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dma-coherent;
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interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core", "reg";
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clocks = <&CP110_LABEL(clk) 1 23>,
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<&CP110_LABEL(clk) 1 16>;
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status = "disabled";
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};
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CP110_LABEL(sata0): sata@540000 {
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compatible = "marvell,armada-8k-ahci",
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"generic-ahci";
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reg = <0x540000 0x30000>;
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dma-coherent;
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interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&CP110_LABEL(clk) 1 15>,
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<&CP110_LABEL(clk) 1 16>;
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status = "disabled";
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};
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CP110_LABEL(xor0): xor@6a0000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x6a0000 0x1000>, <0x6b0000 0x1000>;
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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clock-names = "core", "reg";
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clocks = <&CP110_LABEL(clk) 1 8>,
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<&CP110_LABEL(clk) 1 14>;
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};
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CP110_LABEL(xor1): xor@6c0000 {
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compatible = "marvell,armada-7k-xor", "marvell,xor-v2";
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reg = <0x6c0000 0x1000>, <0x6d0000 0x1000>;
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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clock-names = "core", "reg";
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clocks = <&CP110_LABEL(clk) 1 7>,
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<&CP110_LABEL(clk) 1 14>;
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};
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CP110_LABEL(spi0): spi@700600 {
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compatible = "marvell,armada-380-spi";
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reg = <0x700600 0x50>;
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#address-cells = <0x1>;
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#size-cells = <0x0>;
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clock-names = "core", "axi";
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clocks = <&CP110_LABEL(clk) 1 21>,
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<&CP110_LABEL(clk) 1 17>;
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status = "disabled";
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};
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CP110_LABEL(spi1): spi@700680 {
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compatible = "marvell,armada-380-spi";
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reg = <0x700680 0x50>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-names = "core", "axi";
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clocks = <&CP110_LABEL(clk) 1 21>,
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<&CP110_LABEL(clk) 1 17>;
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status = "disabled";
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};
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CP110_LABEL(i2c0): i2c@701000 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x701000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core", "reg";
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clocks = <&CP110_LABEL(clk) 1 21>,
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<&CP110_LABEL(clk) 1 17>;
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status = "disabled";
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};
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CP110_LABEL(i2c1): i2c@701100 {
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compatible = "marvell,mv78230-i2c";
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reg = <0x701100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core", "reg";
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clocks = <&CP110_LABEL(clk) 1 21>,
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<&CP110_LABEL(clk) 1 17>;
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status = "disabled";
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};
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CP110_LABEL(uart0): serial@702000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x702000 0x100>;
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reg-shift = <2>;
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interrupts = <ICU_GRP_NSR 122 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clock-names = "baudclk", "apb_pclk";
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clocks = <&CP110_LABEL(clk) 1 21>,
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<&CP110_LABEL(clk) 1 17>;
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status = "disabled";
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};
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CP110_LABEL(uart1): serial@702100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x702100 0x100>;
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reg-shift = <2>;
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interrupts = <ICU_GRP_NSR 123 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clock-names = "baudclk", "apb_pclk";
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clocks = <&CP110_LABEL(clk) 1 21>,
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<&CP110_LABEL(clk) 1 17>;
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status = "disabled";
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};
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CP110_LABEL(uart2): serial@702200 {
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compatible = "snps,dw-apb-uart";
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reg = <0x702200 0x100>;
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reg-shift = <2>;
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interrupts = <ICU_GRP_NSR 124 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clock-names = "baudclk", "apb_pclk";
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clocks = <&CP110_LABEL(clk) 1 21>,
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<&CP110_LABEL(clk) 1 17>;
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status = "disabled";
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};
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CP110_LABEL(uart3): serial@702300 {
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compatible = "snps,dw-apb-uart";
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reg = <0x702300 0x100>;
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reg-shift = <2>;
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interrupts = <ICU_GRP_NSR 125 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clock-names = "baudclk", "apb_pclk";
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clocks = <&CP110_LABEL(clk) 1 21>,
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<&CP110_LABEL(clk) 1 17>;
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status = "disabled";
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};
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CP110_LABEL(nand_controller): nand@720000 {
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/*
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* Due to the limitation of the pins available
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* this controller is only usable on the CPM
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* for A7K and on the CPS for A8K.
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*/
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compatible = "marvell,armada-8k-nand-controller",
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"marvell,armada370-nand-controller";
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reg = <0x720000 0x54>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core", "reg";
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clocks = <&CP110_LABEL(clk) 1 2>,
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<&CP110_LABEL(clk) 1 17>;
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marvell,system-controller = <&CP110_LABEL(syscon0)>;
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status = "disabled";
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};
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CP110_LABEL(trng): trng@760000 {
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compatible = "marvell,armada-8k-rng",
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"inside-secure,safexcel-eip76";
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reg = <0x760000 0x7d>;
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interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core", "reg";
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clocks = <&CP110_LABEL(clk) 1 25>,
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<&CP110_LABEL(clk) 1 17>;
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status = "okay";
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};
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CP110_LABEL(sdhci0): sdhci@780000 {
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compatible = "marvell,armada-cp110-sdhci";
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reg = <0x780000 0x300>;
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interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
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clock-names = "core", "axi";
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clocks = <&CP110_LABEL(clk) 1 4>, <&CP110_LABEL(clk) 1 18>;
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dma-coherent;
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status = "disabled";
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};
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CP110_LABEL(crypto): crypto@800000 {
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compatible = "inside-secure,safexcel-eip197b";
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reg = <0x800000 0x200000>;
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interrupts = <ICU_GRP_NSR 87 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
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<ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mem", "ring0", "ring1",
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"ring2", "ring3", "eip";
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clock-names = "core", "reg";
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clocks = <&CP110_LABEL(clk) 1 26>,
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<&CP110_LABEL(clk) 1 17>;
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dma-coherent;
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};
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};
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CP110_LABEL(pcie0): pcie@CP110_PCIE0_BASE {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 ADDRESSIFY(CP110_PCIE0_BASE) 0 0x10000>,
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<0 CP110_PCIEx_CONF_BASE(0) 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 CP110_PCIEx_IO_BASE(0) 0 CP110_PCIEx_IO_BASE(0) 0 0x10000
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/* non-prefetchable memory */
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0x82000000 0 CP110_PCIEx_MEM_BASE(0) 0 CP110_PCIEx_MEM_BASE(0) 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
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interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
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num-lanes = <1>;
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clock-names = "core", "reg";
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clocks = <&CP110_LABEL(clk) 1 13>, <&CP110_LABEL(clk) 1 14>;
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status = "disabled";
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};
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CP110_LABEL(pcie1): pcie@CP110_PCIE1_BASE {
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compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
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reg = <0 ADDRESSIFY(CP110_PCIE1_BASE) 0 0x10000>,
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<0 CP110_PCIEx_CONF_BASE(1) 0 0x80000>;
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reg-names = "ctrl", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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msi-parent = <&gic_v2m0>;
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|
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bus-range = <0 0xff>;
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ranges =
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/* downstream I/O */
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<0x81000000 0 CP110_PCIEx_IO_BASE(1) 0 CP110_PCIEx_IO_BASE(1) 0 0x10000
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|
/* non-prefetchable memory */
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|
0x82000000 0 CP110_PCIEx_MEM_BASE(1) 0 CP110_PCIEx_MEM_BASE(1) 0 0xf00000>;
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interrupt-map-mask = <0 0 0 0>;
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|
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
|
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interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
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|
|
|
num-lanes = <1>;
|
|
clock-names = "core", "reg";
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|
clocks = <&CP110_LABEL(clk) 1 11>, <&CP110_LABEL(clk) 1 14>;
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|
status = "disabled";
|
|
};
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|
|
|
CP110_LABEL(pcie2): pcie@CP110_PCIE2_BASE {
|
|
compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
|
|
reg = <0 ADDRESSIFY(CP110_PCIE2_BASE) 0 0x10000>,
|
|
<0 CP110_PCIEx_CONF_BASE(2) 0 0x80000>;
|
|
reg-names = "ctrl", "config";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
msi-parent = <&gic_v2m0>;
|
|
|
|
bus-range = <0 0xff>;
|
|
ranges =
|
|
/* downstream I/O */
|
|
<0x81000000 0 CP110_PCIEx_IO_BASE(2) 0 CP110_PCIEx_IO_BASE(2) 0 0x10000
|
|
/* non-prefetchable memory */
|
|
0x82000000 0 CP110_PCIEx_MEM_BASE(2) 0 CP110_PCIEx_MEM_BASE(2) 0 0xf00000>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &CP110_LABEL(icu) ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
num-lanes = <1>;
|
|
clock-names = "core", "reg";
|
|
clocks = <&CP110_LABEL(clk) 1 12>, <&CP110_LABEL(clk) 1 14>;
|
|
status = "disabled";
|
|
};
|
|
};
|