645 lines
19 KiB
C
645 lines
19 KiB
C
/***********************license start***************
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* Author: Cavium Networks
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*
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* Contact: support@caviumnetworks.com
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* This file is part of the OCTEON SDK
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*
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* Copyright (c) 2003-2008 Cavium Networks
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*
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* This file is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, Version 2, as
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* published by the Free Software Foundation.
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*
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* This file is distributed in the hope that it will be useful, but
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* AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
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* NONINFRINGEMENT. See the GNU General Public License for more
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* details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this file; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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* or visit http://www.gnu.org/licenses/.
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*
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* This file may also be available under a different license from Cavium.
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* Contact Cavium Networks for more information
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***********************license end**************************************/
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/**
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*
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* Interface to the hardware Packet Output unit.
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*
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* Starting with SDK 1.7.0, the PKO output functions now support
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* two types of locking. CVMX_PKO_LOCK_ATOMIC_TAG continues to
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* function similarly to previous SDKs by using POW atomic tags
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* to preserve ordering and exclusivity. As a new option, you
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* can now pass CVMX_PKO_LOCK_CMD_QUEUE which uses a ll/sc
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* memory based locking instead. This locking has the advantage
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* of not affecting the tag state but doesn't preserve packet
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* ordering. CVMX_PKO_LOCK_CMD_QUEUE is appropriate in most
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* generic code while CVMX_PKO_LOCK_CMD_QUEUE should be used
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* with hand tuned fast path code.
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*
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* Some of other SDK differences visible to the command command
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* queuing:
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* - PKO indexes are no longer stored in the FAU. A large
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* percentage of the FAU register block used to be tied up
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* maintaining PKO queue pointers. These are now stored in a
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* global named block.
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* - The PKO <b>use_locking</b> parameter can now have a global
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* effect. Since all application use the same named block,
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* queue locking correctly applies across all operating
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* systems when using CVMX_PKO_LOCK_CMD_QUEUE.
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* - PKO 3 word commands are now supported. Use
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* cvmx_pko_send_packet_finish3().
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*
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*/
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#ifndef __CVMX_PKO_H__
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#define __CVMX_PKO_H__
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#include <asm/octeon/cvmx-fpa.h>
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#include <asm/octeon/cvmx-pow.h>
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#include <asm/octeon/cvmx-cmd-queue.h>
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#include <asm/octeon/cvmx-pko-defs.h>
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/* Adjust the command buffer size by 1 word so that in the case of using only
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* two word PKO commands no command words stradle buffers. The useful values
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* for this are 0 and 1. */
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#define CVMX_PKO_COMMAND_BUFFER_SIZE_ADJUST (1)
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#define CVMX_PKO_MAX_OUTPUT_QUEUES_STATIC 256
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#define CVMX_PKO_MAX_OUTPUT_QUEUES ((OCTEON_IS_MODEL(OCTEON_CN31XX) || \
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OCTEON_IS_MODEL(OCTEON_CN3010) || OCTEON_IS_MODEL(OCTEON_CN3005) || \
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OCTEON_IS_MODEL(OCTEON_CN50XX)) ? 32 : \
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(OCTEON_IS_MODEL(OCTEON_CN58XX) || \
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OCTEON_IS_MODEL(OCTEON_CN56XX)) ? 256 : 128)
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#define CVMX_PKO_NUM_OUTPUT_PORTS 40
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/* use this for queues that are not used */
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#define CVMX_PKO_MEM_QUEUE_PTRS_ILLEGAL_PID 63
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#define CVMX_PKO_QUEUE_STATIC_PRIORITY 9
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#define CVMX_PKO_ILLEGAL_QUEUE 0xFFFF
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#define CVMX_PKO_MAX_QUEUE_DEPTH 0
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typedef enum {
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CVMX_PKO_SUCCESS,
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CVMX_PKO_INVALID_PORT,
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CVMX_PKO_INVALID_QUEUE,
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CVMX_PKO_INVALID_PRIORITY,
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CVMX_PKO_NO_MEMORY,
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CVMX_PKO_PORT_ALREADY_SETUP,
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CVMX_PKO_CMD_QUEUE_INIT_ERROR
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} cvmx_pko_status_t;
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/**
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* This enumeration represents the differnet locking modes supported by PKO.
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*/
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typedef enum {
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/*
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* PKO doesn't do any locking. It is the responsibility of the
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* application to make sure that no other core is accessing
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* the same queue at the same time
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*/
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CVMX_PKO_LOCK_NONE = 0,
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/*
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* PKO performs an atomic tagswitch to insure exclusive access
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* to the output queue. This will maintain packet ordering on
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* output.
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*/
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CVMX_PKO_LOCK_ATOMIC_TAG = 1,
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/*
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* PKO uses the common command queue locks to insure exclusive
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* access to the output queue. This is a memory based
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* ll/sc. This is the most portable locking mechanism.
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*/
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CVMX_PKO_LOCK_CMD_QUEUE = 2,
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} cvmx_pko_lock_t;
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typedef struct {
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uint32_t packets;
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uint64_t octets;
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uint64_t doorbell;
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} cvmx_pko_port_status_t;
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/**
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* This structure defines the address to use on a packet enqueue
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*/
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typedef union {
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uint64_t u64;
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struct {
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#ifdef __BIG_ENDIAN_BITFIELD
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/* Must CVMX_IO_SEG */
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uint64_t mem_space:2;
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/* Must be zero */
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uint64_t reserved:13;
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/* Must be one */
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uint64_t is_io:1;
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/* The ID of the device on the non-coherent bus */
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uint64_t did:8;
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/* Must be zero */
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uint64_t reserved2:4;
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/* Must be zero */
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uint64_t reserved3:18;
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/*
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* The hardware likes to have the output port in
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* addition to the output queue,
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*/
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uint64_t port:6;
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/*
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* The output queue to send the packet to (0-127 are
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* legal)
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*/
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uint64_t queue:9;
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/* Must be zero */
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uint64_t reserved4:3;
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#else
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uint64_t reserved4:3;
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uint64_t queue:9;
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uint64_t port:9;
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uint64_t reserved3:15;
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uint64_t reserved2:4;
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uint64_t did:8;
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uint64_t is_io:1;
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uint64_t reserved:13;
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uint64_t mem_space:2;
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#endif
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} s;
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} cvmx_pko_doorbell_address_t;
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/**
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* Structure of the first packet output command word.
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*/
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typedef union {
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uint64_t u64;
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struct {
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#ifdef __BIG_ENDIAN_BITFIELD
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/*
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* The size of the reg1 operation - could be 8, 16,
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* 32, or 64 bits.
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*/
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uint64_t size1:2;
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/*
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* The size of the reg0 operation - could be 8, 16,
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* 32, or 64 bits.
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*/
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uint64_t size0:2;
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/*
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* If set, subtract 1, if clear, subtract packet
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* size.
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*/
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uint64_t subone1:1;
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/*
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* The register, subtract will be done if reg1 is
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* non-zero.
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*/
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uint64_t reg1:11;
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/* If set, subtract 1, if clear, subtract packet size */
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uint64_t subone0:1;
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/* The register, subtract will be done if reg0 is non-zero */
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uint64_t reg0:11;
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/*
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* When set, interpret segment pointer and segment
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* bytes in little endian order.
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*/
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uint64_t le:1;
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/*
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* When set, packet data not allocated in L2 cache by
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* PKO.
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*/
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uint64_t n2:1;
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/*
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* If set and rsp is set, word3 contains a pointer to
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* a work queue entry.
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*/
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uint64_t wqp:1;
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/* If set, the hardware will send a response when done */
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uint64_t rsp:1;
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/*
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* If set, the supplied pkt_ptr is really a pointer to
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* a list of pkt_ptr's.
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*/
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uint64_t gather:1;
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/*
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* If ipoffp1 is non zero, (ipoffp1-1) is the number
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* of bytes to IP header, and the hardware will
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* calculate and insert the UDP/TCP checksum.
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*/
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uint64_t ipoffp1:7;
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/*
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* If set, ignore the I bit (force to zero) from all
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* pointer structures.
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*/
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uint64_t ignore_i:1;
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/*
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* If clear, the hardware will attempt to free the
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* buffers containing the packet.
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*/
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uint64_t dontfree:1;
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/*
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* The total number of segs in the packet, if gather
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* set, also gather list length.
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*/
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uint64_t segs:6;
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/* Including L2, but no trailing CRC */
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uint64_t total_bytes:16;
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#else
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uint64_t total_bytes:16;
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uint64_t segs:6;
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uint64_t dontfree:1;
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uint64_t ignore_i:1;
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uint64_t ipoffp1:7;
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uint64_t gather:1;
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uint64_t rsp:1;
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uint64_t wqp:1;
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uint64_t n2:1;
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uint64_t le:1;
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uint64_t reg0:11;
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uint64_t subone0:1;
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uint64_t reg1:11;
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uint64_t subone1:1;
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uint64_t size0:2;
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uint64_t size1:2;
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#endif
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} s;
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} cvmx_pko_command_word0_t;
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/* CSR typedefs have been moved to cvmx-csr-*.h */
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/**
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* Definition of internal state for Packet output processing
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*/
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typedef struct {
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/* ptr to start of buffer, offset kept in FAU reg */
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uint64_t *start_ptr;
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} cvmx_pko_state_elem_t;
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/**
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* Call before any other calls to initialize the packet
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* output system.
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*/
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extern void cvmx_pko_initialize_global(void);
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extern int cvmx_pko_initialize_local(void);
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/**
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* Enables the packet output hardware. It must already be
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* configured.
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*/
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extern void cvmx_pko_enable(void);
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/**
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* Disables the packet output. Does not affect any configuration.
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*/
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extern void cvmx_pko_disable(void);
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/**
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* Shutdown and free resources required by packet output.
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*/
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extern void cvmx_pko_shutdown(void);
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/**
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* Configure a output port and the associated queues for use.
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*
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* @port: Port to configure.
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* @base_queue: First queue number to associate with this port.
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* @num_queues: Number of queues t oassociate with this port
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* @priority: Array of priority levels for each queue. Values are
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* allowed to be 1-8. A value of 8 get 8 times the traffic
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* of a value of 1. There must be num_queues elements in the
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* array.
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*/
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extern cvmx_pko_status_t cvmx_pko_config_port(uint64_t port,
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uint64_t base_queue,
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uint64_t num_queues,
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const uint64_t priority[]);
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/**
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* Ring the packet output doorbell. This tells the packet
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* output hardware that "len" command words have been added
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* to its pending list. This command includes the required
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* CVMX_SYNCWS before the doorbell ring.
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*
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* @port: Port the packet is for
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* @queue: Queue the packet is for
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* @len: Length of the command in 64 bit words
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*/
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static inline void cvmx_pko_doorbell(uint64_t port, uint64_t queue,
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uint64_t len)
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{
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cvmx_pko_doorbell_address_t ptr;
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ptr.u64 = 0;
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ptr.s.mem_space = CVMX_IO_SEG;
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ptr.s.did = CVMX_OCT_DID_PKT_SEND;
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ptr.s.is_io = 1;
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ptr.s.port = port;
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ptr.s.queue = queue;
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/*
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* Need to make sure output queue data is in DRAM before
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* doorbell write.
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*/
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CVMX_SYNCWS;
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cvmx_write_io(ptr.u64, len);
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}
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/**
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* Prepare to send a packet. This may initiate a tag switch to
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* get exclusive access to the output queue structure, and
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* performs other prep work for the packet send operation.
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*
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* cvmx_pko_send_packet_finish() MUST be called after this function is called,
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* and must be called with the same port/queue/use_locking arguments.
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*
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* The use_locking parameter allows the caller to use three
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* possible locking modes.
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* - CVMX_PKO_LOCK_NONE
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* - PKO doesn't do any locking. It is the responsibility
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* of the application to make sure that no other core
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* is accessing the same queue at the same time.
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* - CVMX_PKO_LOCK_ATOMIC_TAG
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* - PKO performs an atomic tagswitch to insure exclusive
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* access to the output queue. This will maintain
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* packet ordering on output.
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* - CVMX_PKO_LOCK_CMD_QUEUE
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* - PKO uses the common command queue locks to insure
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* exclusive access to the output queue. This is a
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* memory based ll/sc. This is the most portable
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* locking mechanism.
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*
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* NOTE: If atomic locking is used, the POW entry CANNOT be
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* descheduled, as it does not contain a valid WQE pointer.
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*
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* @port: Port to send it on
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* @queue: Queue to use
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* @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
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* CVMX_PKO_LOCK_CMD_QUEUE
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*/
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static inline void cvmx_pko_send_packet_prepare(uint64_t port, uint64_t queue,
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cvmx_pko_lock_t use_locking)
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{
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if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG) {
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/*
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* Must do a full switch here to handle all cases. We
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* use a fake WQE pointer, as the POW does not access
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* this memory. The WQE pointer and group are only
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* used if this work is descheduled, which is not
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* supported by the
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* cvmx_pko_send_packet_prepare/cvmx_pko_send_packet_finish
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* combination. Note that this is a special case in
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* which these fake values can be used - this is not a
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* general technique.
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*/
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uint32_t tag =
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CVMX_TAG_SW_BITS_INTERNAL << CVMX_TAG_SW_SHIFT |
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CVMX_TAG_SUBGROUP_PKO << CVMX_TAG_SUBGROUP_SHIFT |
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(CVMX_TAG_SUBGROUP_MASK & queue);
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cvmx_pow_tag_sw_full((cvmx_wqe_t *) cvmx_phys_to_ptr(0x80), tag,
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CVMX_POW_TAG_TYPE_ATOMIC, 0);
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}
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}
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/**
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* Complete packet output. cvmx_pko_send_packet_prepare() must be
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* called exactly once before this, and the same parameters must be
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* passed to both cvmx_pko_send_packet_prepare() and
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* cvmx_pko_send_packet_finish().
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*
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* @port: Port to send it on
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* @queue: Queue to use
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* @pko_command:
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* PKO HW command word
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* @packet: Packet to send
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* @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
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* CVMX_PKO_LOCK_CMD_QUEUE
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*
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* Returns returns CVMX_PKO_SUCCESS on success, or error code on
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* failure of output
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*/
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static inline cvmx_pko_status_t cvmx_pko_send_packet_finish(
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uint64_t port,
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uint64_t queue,
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cvmx_pko_command_word0_t pko_command,
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union cvmx_buf_ptr packet,
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cvmx_pko_lock_t use_locking)
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{
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cvmx_cmd_queue_result_t result;
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if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
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cvmx_pow_tag_sw_wait();
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result = cvmx_cmd_queue_write2(CVMX_CMD_QUEUE_PKO(queue),
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(use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
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pko_command.u64, packet.u64);
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if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
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cvmx_pko_doorbell(port, queue, 2);
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return CVMX_PKO_SUCCESS;
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} else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
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|| (result == CVMX_CMD_QUEUE_FULL)) {
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return CVMX_PKO_NO_MEMORY;
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} else {
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return CVMX_PKO_INVALID_QUEUE;
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}
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}
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/**
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* Complete packet output. cvmx_pko_send_packet_prepare() must be
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* called exactly once before this, and the same parameters must be
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* passed to both cvmx_pko_send_packet_prepare() and
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* cvmx_pko_send_packet_finish().
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*
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* @port: Port to send it on
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* @queue: Queue to use
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* @pko_command:
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* PKO HW command word
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* @packet: Packet to send
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* @addr: Plysical address of a work queue entry or physical address
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* to zero on complete.
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* @use_locking: CVMX_PKO_LOCK_NONE, CVMX_PKO_LOCK_ATOMIC_TAG, or
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* CVMX_PKO_LOCK_CMD_QUEUE
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*
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* Returns returns CVMX_PKO_SUCCESS on success, or error code on
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* failure of output
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*/
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static inline cvmx_pko_status_t cvmx_pko_send_packet_finish3(
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uint64_t port,
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uint64_t queue,
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cvmx_pko_command_word0_t pko_command,
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union cvmx_buf_ptr packet,
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uint64_t addr,
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cvmx_pko_lock_t use_locking)
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{
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cvmx_cmd_queue_result_t result;
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if (use_locking == CVMX_PKO_LOCK_ATOMIC_TAG)
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cvmx_pow_tag_sw_wait();
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result = cvmx_cmd_queue_write3(CVMX_CMD_QUEUE_PKO(queue),
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(use_locking == CVMX_PKO_LOCK_CMD_QUEUE),
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pko_command.u64, packet.u64, addr);
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if (likely(result == CVMX_CMD_QUEUE_SUCCESS)) {
|
|
cvmx_pko_doorbell(port, queue, 3);
|
|
return CVMX_PKO_SUCCESS;
|
|
} else if ((result == CVMX_CMD_QUEUE_NO_MEMORY)
|
|
|| (result == CVMX_CMD_QUEUE_FULL)) {
|
|
return CVMX_PKO_NO_MEMORY;
|
|
} else {
|
|
return CVMX_PKO_INVALID_QUEUE;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Return the pko output queue associated with a port and a specific core.
|
|
* In normal mode (PKO lockless operation is disabled), the value returned
|
|
* is the base queue.
|
|
*
|
|
* @port: Port number
|
|
* @core: Core to get queue for
|
|
*
|
|
* Returns Core-specific output queue
|
|
*/
|
|
static inline int cvmx_pko_get_base_queue_per_core(int port, int core)
|
|
{
|
|
#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0
|
|
#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE0 16
|
|
#endif
|
|
#ifndef CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1
|
|
#define CVMX_HELPER_PKO_MAX_PORTS_INTERFACE1 16
|
|
#endif
|
|
|
|
if (port < CVMX_PKO_MAX_PORTS_INTERFACE0)
|
|
return port * CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + core;
|
|
else if (port >= 16 && port < 16 + CVMX_PKO_MAX_PORTS_INTERFACE1)
|
|
return CVMX_PKO_MAX_PORTS_INTERFACE0 *
|
|
CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 + (port -
|
|
16) *
|
|
CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + core;
|
|
else if ((port >= 32) && (port < 36))
|
|
return CVMX_PKO_MAX_PORTS_INTERFACE0 *
|
|
CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
|
|
CVMX_PKO_MAX_PORTS_INTERFACE1 *
|
|
CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 + (port -
|
|
32) *
|
|
CVMX_PKO_QUEUES_PER_PORT_PCI;
|
|
else if ((port >= 36) && (port < 40))
|
|
return CVMX_PKO_MAX_PORTS_INTERFACE0 *
|
|
CVMX_PKO_QUEUES_PER_PORT_INTERFACE0 +
|
|
CVMX_PKO_MAX_PORTS_INTERFACE1 *
|
|
CVMX_PKO_QUEUES_PER_PORT_INTERFACE1 +
|
|
4 * CVMX_PKO_QUEUES_PER_PORT_PCI + (port -
|
|
36) *
|
|
CVMX_PKO_QUEUES_PER_PORT_LOOP;
|
|
else
|
|
/* Given the limit on the number of ports we can map to
|
|
* CVMX_MAX_OUTPUT_QUEUES_STATIC queues (currently 256,
|
|
* divided among all cores), the remaining unmapped ports
|
|
* are assigned an illegal queue number */
|
|
return CVMX_PKO_ILLEGAL_QUEUE;
|
|
}
|
|
|
|
/**
|
|
* For a given port number, return the base pko output queue
|
|
* for the port.
|
|
*
|
|
* @port: Port number
|
|
* Returns Base output queue
|
|
*/
|
|
static inline int cvmx_pko_get_base_queue(int port)
|
|
{
|
|
if (OCTEON_IS_MODEL(OCTEON_CN68XX))
|
|
return port;
|
|
|
|
return cvmx_pko_get_base_queue_per_core(port, 0);
|
|
}
|
|
|
|
/**
|
|
* For a given port number, return the number of pko output queues.
|
|
*
|
|
* @port: Port number
|
|
* Returns Number of output queues
|
|
*/
|
|
static inline int cvmx_pko_get_num_queues(int port)
|
|
{
|
|
if (port < 16)
|
|
return CVMX_PKO_QUEUES_PER_PORT_INTERFACE0;
|
|
else if (port < 32)
|
|
return CVMX_PKO_QUEUES_PER_PORT_INTERFACE1;
|
|
else if (port < 36)
|
|
return CVMX_PKO_QUEUES_PER_PORT_PCI;
|
|
else if (port < 40)
|
|
return CVMX_PKO_QUEUES_PER_PORT_LOOP;
|
|
else
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* Get the status counters for a port.
|
|
*
|
|
* @port_num: Port number to get statistics for.
|
|
* @clear: Set to 1 to clear the counters after they are read
|
|
* @status: Where to put the results.
|
|
*/
|
|
static inline void cvmx_pko_get_port_status(uint64_t port_num, uint64_t clear,
|
|
cvmx_pko_port_status_t *status)
|
|
{
|
|
union cvmx_pko_reg_read_idx pko_reg_read_idx;
|
|
union cvmx_pko_mem_count0 pko_mem_count0;
|
|
union cvmx_pko_mem_count1 pko_mem_count1;
|
|
|
|
pko_reg_read_idx.u64 = 0;
|
|
pko_reg_read_idx.s.index = port_num;
|
|
cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
|
|
|
|
pko_mem_count0.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT0);
|
|
status->packets = pko_mem_count0.s.count;
|
|
if (clear) {
|
|
pko_mem_count0.s.count = port_num;
|
|
cvmx_write_csr(CVMX_PKO_MEM_COUNT0, pko_mem_count0.u64);
|
|
}
|
|
|
|
pko_mem_count1.u64 = cvmx_read_csr(CVMX_PKO_MEM_COUNT1);
|
|
status->octets = pko_mem_count1.s.count;
|
|
if (clear) {
|
|
pko_mem_count1.s.count = port_num;
|
|
cvmx_write_csr(CVMX_PKO_MEM_COUNT1, pko_mem_count1.u64);
|
|
}
|
|
|
|
if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
|
|
union cvmx_pko_mem_debug9 debug9;
|
|
pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
|
|
cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
|
|
debug9.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG9);
|
|
status->doorbell = debug9.cn38xx.doorbell;
|
|
} else {
|
|
union cvmx_pko_mem_debug8 debug8;
|
|
pko_reg_read_idx.s.index = cvmx_pko_get_base_queue(port_num);
|
|
cvmx_write_csr(CVMX_PKO_REG_READ_IDX, pko_reg_read_idx.u64);
|
|
debug8.u64 = cvmx_read_csr(CVMX_PKO_MEM_DEBUG8);
|
|
status->doorbell = debug8.cn50xx.doorbell;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Rate limit a PKO port to a max packets/sec. This function is only
|
|
* supported on CN57XX, CN56XX, CN55XX, and CN54XX.
|
|
*
|
|
* @port: Port to rate limit
|
|
* @packets_s: Maximum packet/sec
|
|
* @burst: Maximum number of packets to burst in a row before rate
|
|
* limiting cuts in.
|
|
*
|
|
* Returns Zero on success, negative on failure
|
|
*/
|
|
extern int cvmx_pko_rate_limit_packets(int port, int packets_s, int burst);
|
|
|
|
/**
|
|
* Rate limit a PKO port to a max bits/sec. This function is only
|
|
* supported on CN57XX, CN56XX, CN55XX, and CN54XX.
|
|
*
|
|
* @port: Port to rate limit
|
|
* @bits_s: PKO rate limit in bits/sec
|
|
* @burst: Maximum number of bits to burst before rate
|
|
* limiting cuts in.
|
|
*
|
|
* Returns Zero on success, negative on failure
|
|
*/
|
|
extern int cvmx_pko_rate_limit_bits(int port, uint64_t bits_s, int burst);
|
|
|
|
#endif /* __CVMX_PKO_H__ */
|