533 lines
13 KiB
Plaintext
533 lines
13 KiB
Plaintext
/*
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* Keymile KMETER1 Device Tree Source
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*
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* 2008-2011 DENX Software Engineering GmbH
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/dts-v1/;
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/ {
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model = "KMETER1";
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compatible = "keymile,KMETER1";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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ethernet0 = &enet_piggy2;
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ethernet1 = &enet_estar1;
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ethernet2 = &enet_estar2;
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ethernet3 = &enet_eth1;
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ethernet4 = &enet_eth2;
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ethernet5 = &enet_eth3;
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ethernet6 = &enet_eth4;
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serial0 = &serial0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,8360@0 {
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device_type = "cpu";
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reg = <0x0>;
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d-cache-line-size = <32>; // 32 bytes
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i-cache-line-size = <32>; // 32 bytes
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d-cache-size = <32768>; // L1, 32K
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i-cache-size = <32768>; // L1, 32K
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timebase-frequency = <0>; /* Filled in by U-Boot */
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bus-frequency = <0>; /* Filled in by U-Boot */
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clock-frequency = <0>; /* Filled in by U-Boot */
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};
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};
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memory {
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device_type = "memory";
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reg = <0 0>; /* Filled in by U-Boot */
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};
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soc8360@e0000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "fsl,mpc8360-immr", "simple-bus";
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ranges = <0x0 0xe0000000 0x00200000>;
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reg = <0xe0000000 0x00000200>;
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bus-frequency = <0>; /* Filled in by U-Boot */
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pmc: power@b00 {
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compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc";
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reg = <0xb00 0x100 0xa00 0x100>;
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interrupts = <80 0x8>;
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interrupt-parent = <&ipic>;
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};
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i2c@3000 {
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#address-cells = <1>;
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#size-cells = <0>;
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cell-index = <0>;
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compatible = "fsl,mpc8313-i2c","fsl-i2c";
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reg = <0x3000 0x100>;
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interrupts = <14 0x8>;
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interrupt-parent = <&ipic>;
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clock-frequency = <400000>;
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};
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serial0: serial@4500 {
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cell-index = <0>;
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device_type = "serial";
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compatible = "fsl,ns16550", "ns16550";
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reg = <0x4500 0x100>;
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clock-frequency = <264000000>;
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interrupts = <9 0x8>;
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interrupt-parent = <&ipic>;
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};
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dma@82a8 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,mpc8360-dma", "fsl,elo-dma";
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reg = <0x82a8 4>;
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ranges = <0 0x8100 0x1a8>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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cell-index = <0>;
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dma-channel@0 {
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
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reg = <0 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@80 {
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
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reg = <0x80 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@100 {
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
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reg = <0x100 0x80>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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dma-channel@180 {
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compatible = "fsl,mpc8360-dma-channel", "fsl,elo-dma-channel";
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reg = <0x180 0x28>;
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interrupt-parent = <&ipic>;
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interrupts = <71 8>;
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};
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};
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ipic: pic@700 {
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "fsl,pq2pro-pic", "fsl,ipic";
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interrupt-controller;
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reg = <0x700 0x100>;
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};
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par_io@1400 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x1400 0x100>;
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compatible = "fsl,mpc8360-par_io";
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num-ports = <7>;
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qe_pio_c: gpio-controller@30 {
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#gpio-cells = <2>;
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compatible = "fsl,mpc8360-qe-pario-bank",
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"fsl,mpc8323-qe-pario-bank";
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reg = <0x1430 0x18>;
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gpio-controller;
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};
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pio_ucc1: ucc_pin@0 {
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reg = <0>;
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0 /* MDC */
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0 3 1 0 1 0 /* TxD0 */
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0 4 1 0 1 0 /* TxD1 */
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0 5 1 0 1 0 /* TxD2 */
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0 6 1 0 1 0 /* TxD3 */
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0 9 2 0 1 0 /* RxD0 */
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0 10 2 0 1 0 /* RxD1 */
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0 11 2 0 1 0 /* RxD2 */
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0 12 2 0 1 0 /* RxD3 */
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0 7 1 0 1 0 /* TX_EN */
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0 8 1 0 1 0 /* TX_ER */
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0 15 2 0 1 0 /* RX_DV */
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0 16 2 0 1 0 /* RX_ER */
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0 0 2 0 1 0 /* RX_CLK */
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2 9 1 0 3 0 /* GTX_CLK - CLK10 */
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2 8 2 0 1 0 /* GTX125 - CLK9 */
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>;
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};
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pio_ucc2: ucc_pin@1 {
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reg = <1>;
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0 /* MDC */
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0 17 1 0 1 0 /* TxD0 */
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0 18 1 0 1 0 /* TxD1 */
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0 19 1 0 1 0 /* TxD2 */
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0 20 1 0 1 0 /* TxD3 */
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0 23 2 0 1 0 /* RxD0 */
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0 24 2 0 1 0 /* RxD1 */
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0 25 2 0 1 0 /* RxD2 */
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0 26 2 0 1 0 /* RxD3 */
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0 21 1 0 1 0 /* TX_EN */
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0 22 1 0 1 0 /* TX_ER */
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0 29 2 0 1 0 /* RX_DV */
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0 30 2 0 1 0 /* RX_ER */
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0 31 2 0 1 0 /* RX_CLK */
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2 2 1 0 2 0 /* GTX_CLK - CLK3 */
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2 3 2 0 1 0 /* GTX125 - CLK4 */
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>;
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};
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pio_ucc4: ucc_pin@3 {
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reg = <3>;
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0 /* MDC */
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1 14 1 0 1 0 /* TxD0 (PB14, out, f1) */
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1 15 1 0 1 0 /* TxD1 (PB15, out, f1) */
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1 20 2 0 1 0 /* RxD0 (PB20, in, f1) */
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1 21 2 0 1 0 /* RxD1 (PB21, in, f1) */
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1 18 1 0 1 0 /* TX_EN (PB18, out, f1) */
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1 26 2 0 1 0 /* RX_DV (PB26, in, f1) */
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1 27 2 0 1 0 /* RX_ER (PB27, in, f1) */
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2 16 2 0 1 0 /* UCC4_RMII_CLK (CLK17) */
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>;
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};
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pio_ucc5: ucc_pin@4 {
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reg = <4>;
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0 /* MDC */
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3 0 1 0 1 0 /* TxD0 (PD0, out, f1) */
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3 1 1 0 1 0 /* TxD1 (PD1, out, f1) */
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3 6 2 0 1 0 /* RxD0 (PD6, in, f1) */
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3 7 2 0 1 0 /* RxD1 (PD7, in, f1) */
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3 4 1 0 1 0 /* TX_EN (PD4, out, f1) */
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3 12 2 0 1 0 /* RX_DV (PD12, in, f1) */
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3 13 2 0 1 0 /* RX_ER (PD13, in, f1) */
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>;
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};
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pio_ucc6: ucc_pin@5 {
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reg = <5>;
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0 /* MDC */
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3 14 1 0 1 0 /* TxD0 (PD14, out, f1) */
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3 15 1 0 1 0 /* TxD1 (PD15, out, f1) */
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3 20 2 0 1 0 /* RxD0 (PD20, in, f1) */
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3 21 2 0 1 0 /* RxD1 (PD21, in, f1) */
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3 18 1 0 1 0 /* TX_EN (PD18, out, f1) */
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3 26 2 0 1 0 /* RX_DV (PD26, in, f1) */
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3 27 2 0 1 0 /* RX_ER (PD27, in, f1) */
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>;
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};
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pio_ucc7: ucc_pin@6 {
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reg = <6>;
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0 /* MDC */
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4 0 1 0 1 0 /* TxD0 (PE0, out, f1) */
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4 1 1 0 1 0 /* TxD1 (PE1, out, f1) */
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4 6 2 0 1 0 /* RxD0 (PE6, in, f1) */
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4 7 2 0 1 0 /* RxD1 (PE7, in, f1) */
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4 4 1 0 1 0 /* TX_EN (PE4, out, f1) */
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4 12 2 0 1 0 /* RX_DV (PE12, in, f1) */
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4 13 2 0 1 0 /* RX_ER (PE13, in, f1) */
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>;
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};
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pio_ucc8: ucc_pin@7 {
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reg = <7>;
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0 1 3 0 2 0 /* MDIO */
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0 2 1 0 1 0 /* MDC */
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4 14 1 0 2 0 /* TxD0 (PE14, out, f2) */
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4 15 1 0 1 0 /* TxD1 (PE15, out, f1) */
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4 20 2 0 1 0 /* RxD0 (PE20, in, f1) */
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4 21 2 0 1 0 /* RxD1 (PE21, in, f1) */
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4 18 1 0 1 0 /* TX_EN (PE18, out, f1) */
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4 26 2 0 1 0 /* RX_DV (PE26, in, f1) */
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4 27 2 0 1 0 /* RX_ER (PE27, in, f1) */
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2 15 2 0 1 0 /* UCCx_RMII_CLK (CLK16) */
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>;
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};
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};
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qe@100000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe";
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ranges = <0x0 0x100000 0x100000>;
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reg = <0x100000 0x480>;
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clock-frequency = <0>; /* Filled in by U-Boot */
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brg-frequency = <0>; /* Filled in by U-Boot */
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bus-frequency = <0>; /* Filled in by U-Boot */
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muram@10000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,qe-muram", "fsl,cpm-muram";
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ranges = <0x0 0x00010000 0x0000c000>;
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data-only@0 {
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compatible = "fsl,qe-muram-data",
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"fsl,cpm-muram-data";
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reg = <0x0 0xc000>;
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};
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};
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/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
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enet_estar1: ucc@2000 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <1>;
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reg = <0x2000 0x200>;
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interrupts = <32>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk9";
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phy-handle = <&phy_estar1>;
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phy-connection-type = "rgmii-id";
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pio-handle = <&pio_ucc1>;
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};
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/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
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enet_estar2: ucc@3000 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <2>;
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reg = <0x3000 0x200>;
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interrupts = <33>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk4";
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phy-handle = <&phy_estar2>;
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phy-connection-type = "rgmii-id";
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pio-handle = <&pio_ucc2>;
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};
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/* Piggy2 (UCC4, MDIO 0x00, RMII) */
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enet_piggy2: ucc@3200 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <4>;
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reg = <0x3200 0x200>;
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interrupts = <35>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk17";
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phy-handle = <&phy_piggy2>;
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phy-connection-type = "rmii";
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pio-handle = <&pio_ucc4>;
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};
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/* Eth-1 (UCC5, MDIO 0x08, RMII) */
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enet_eth1: ucc@2400 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <5>;
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reg = <0x2400 0x200>;
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interrupts = <40>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk16";
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phy-handle = <&phy_eth1>;
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phy-connection-type = "rmii";
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pio-handle = <&pio_ucc5>;
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};
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/* Eth-2 (UCC6, MDIO 0x09, RMII) */
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enet_eth2: ucc@3400 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <6>;
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reg = <0x3400 0x200>;
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interrupts = <41>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk16";
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phy-handle = <&phy_eth2>;
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phy-connection-type = "rmii";
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pio-handle = <&pio_ucc6>;
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};
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/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
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enet_eth3: ucc@2600 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <7>;
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reg = <0x2600 0x200>;
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interrupts = <42>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk16";
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phy-handle = <&phy_eth3>;
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phy-connection-type = "rmii";
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pio-handle = <&pio_ucc7>;
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};
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/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
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enet_eth4: ucc@3600 {
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device_type = "network";
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compatible = "ucc_geth";
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cell-index = <8>;
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reg = <0x3600 0x200>;
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interrupts = <43>;
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interrupt-parent = <&qeic>;
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local-mac-address = [ 00 00 00 00 00 00 ];
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rx-clock-name = "none";
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tx-clock-name = "clk16";
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phy-handle = <&phy_eth4>;
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phy-connection-type = "rmii";
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pio-handle = <&pio_ucc8>;
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};
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mdio@3320 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3320 0x18>;
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compatible = "fsl,ucc-mdio";
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/* Piggy2 (UCC4, MDIO 0x00, RMII) */
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phy_piggy2: ethernet-phy@0 {
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reg = <0x0>;
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};
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/* Eth-1 (UCC5, MDIO 0x08, RMII) */
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phy_eth1: ethernet-phy@8 {
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reg = <0x08>;
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};
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/* Eth-2 (UCC6, MDIO 0x09, RMII) */
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phy_eth2: ethernet-phy@9 {
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reg = <0x09>;
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};
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/* Eth-3 (UCC7, MDIO 0x0a, RMII) */
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phy_eth3: ethernet-phy@a {
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reg = <0x0a>;
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};
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/* Eth-4 (UCC8, MDIO 0x0b, RMII) */
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phy_eth4: ethernet-phy@b {
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reg = <0x0b>;
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};
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/* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
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phy_estar1: ethernet-phy@10 {
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interrupt-parent = <&ipic>;
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interrupts = <17 0x8>;
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reg = <0x10>;
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};
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/* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
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phy_estar2: ethernet-phy@11 {
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interrupt-parent = <&ipic>;
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interrupts = <18 0x8>;
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reg = <0x11>;
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};
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};
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qeic: interrupt-controller@80 {
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interrupt-controller;
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compatible = "fsl,qe-ic";
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#address-cells = <0>;
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#interrupt-cells = <1>;
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reg = <0x80 0x80>;
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big-endian;
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interrupts = <
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|
32 0x8
|
|
33 0x8
|
|
34 0x8
|
|
35 0x8
|
|
40 0x8
|
|
41 0x8
|
|
42 0x8
|
|
43 0x8
|
|
>;
|
|
interrupt-parent = <&ipic>;
|
|
};
|
|
};
|
|
};
|
|
|
|
localbus@e0005000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus",
|
|
"simple-bus";
|
|
reg = <0xe0005000 0xd8>;
|
|
ranges = <0 0 0xf0000000 0x04000000 /* LB 0 */
|
|
1 0 0xe8000000 0x01000000 /* LB 1 */
|
|
3 0 0xa0000000 0x10000000>; /* LB 3 */
|
|
|
|
flash@0,0 {
|
|
compatible = "cfi-flash";
|
|
reg = <0 0 0x04000000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
bank-width = <2>;
|
|
partition@0 { /* 768KB */
|
|
label = "u-boot";
|
|
reg = <0 0xC0000>;
|
|
};
|
|
partition@c0000 { /* 128KB */
|
|
label = "env";
|
|
reg = <0xC0000 0x20000>;
|
|
};
|
|
partition@e0000 { /* 128KB */
|
|
label = "envred";
|
|
reg = <0xE0000 0x20000>;
|
|
};
|
|
partition@100000 { /* 64512KB */
|
|
label = "ubi0";
|
|
reg = <0x100000 0x3F00000>;
|
|
};
|
|
};
|
|
};
|
|
};
|