6db4831e98
Android 14
80 lines
1.8 KiB
C
80 lines
1.8 KiB
C
/*
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* arch/sh/kernel/cpu/sh5/clock-sh5.c
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*
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* SH-5 support for the clock framework
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*
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* Copyright (C) 2008 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <asm/clock.h>
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#include <asm/io.h>
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static int ifc_table[] = { 2, 4, 6, 8, 10, 12, 16, 24 };
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/* Clock, Power and Reset Controller */
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#define CPRC_BLOCK_OFF 0x01010000
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#define CPRC_BASE (PHYS_PERIPHERAL_BLOCK + CPRC_BLOCK_OFF)
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static unsigned long cprc_base;
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static void master_clk_init(struct clk *clk)
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{
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int idx = (__raw_readl(cprc_base + 0x00) >> 6) & 0x0007;
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clk->rate *= ifc_table[idx];
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}
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static struct sh_clk_ops sh5_master_clk_ops = {
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.init = master_clk_init,
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};
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static unsigned long module_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readw(cprc_base) >> 12) & 0x0007;
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return clk->parent->rate / ifc_table[idx];
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}
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static struct sh_clk_ops sh5_module_clk_ops = {
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.recalc = module_clk_recalc,
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};
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static unsigned long bus_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readw(cprc_base) >> 3) & 0x0007;
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return clk->parent->rate / ifc_table[idx];
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}
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static struct sh_clk_ops sh5_bus_clk_ops = {
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.recalc = bus_clk_recalc,
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};
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static unsigned long cpu_clk_recalc(struct clk *clk)
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{
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int idx = (__raw_readw(cprc_base) & 0x0007);
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return clk->parent->rate / ifc_table[idx];
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}
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static struct sh_clk_ops sh5_cpu_clk_ops = {
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.recalc = cpu_clk_recalc,
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};
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static struct sh_clk_ops *sh5_clk_ops[] = {
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&sh5_master_clk_ops,
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&sh5_module_clk_ops,
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&sh5_bus_clk_ops,
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&sh5_cpu_clk_ops,
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};
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void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
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{
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cprc_base = (unsigned long)ioremap_nocache(CPRC_BASE, 1024);
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BUG_ON(!cprc_base);
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if (idx < ARRAY_SIZE(sh5_clk_ops))
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*ops = sh5_clk_ops[idx];
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}
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