228 lines
6.3 KiB
C
228 lines
6.3 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PLL clock descriptions for TI DA850/OMAP-L138/AM18XX
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*
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* Copyright (C) 2018 David Lechner <david@lechnology.com>
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*/
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#include <linux/bitops.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/davinci.h>
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#include <linux/clkdev.h>
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#include <linux/device.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/mfd/da8xx-cfgchip.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of.h>
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#include <linux/types.h>
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#include "pll.h"
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#define OCSEL_OCSRC_OSCIN 0x14
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#define OCSEL_OCSRC_PLL0_SYSCLK(n) (0x16 + (n))
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#define OCSEL_OCSRC_PLL1_OBSCLK 0x1e
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#define OCSEL_OCSRC_PLL1_SYSCLK(n) (0x16 + (n))
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static const struct davinci_pll_clk_info da850_pll0_info = {
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.name = "pll0",
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.unlock_reg = CFGCHIP(0),
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.unlock_mask = CFGCHIP0_PLL_MASTER_LOCK,
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.pllm_mask = GENMASK(4, 0),
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.pllm_min = 4,
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.pllm_max = 32,
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.pllout_min_rate = 300000000,
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.pllout_max_rate = 600000000,
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.flags = PLL_HAS_CLKMODE | PLL_HAS_PREDIV | PLL_HAS_POSTDIV |
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PLL_HAS_EXTCLKSRC,
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};
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/*
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* NB: Technically, the clocks flagged as SYSCLK_FIXED_DIV are "fixed ratio",
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* meaning that we could change the divider as long as we keep the correct
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* ratio between all of the clocks, but we don't support that because there is
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* currently not a need for it.
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*/
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SYSCLK(1, pll0_sysclk1, pll0_pllen, 5, SYSCLK_FIXED_DIV);
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SYSCLK(2, pll0_sysclk2, pll0_pllen, 5, SYSCLK_FIXED_DIV);
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SYSCLK(3, pll0_sysclk3, pll0_pllen, 5, 0);
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SYSCLK(4, pll0_sysclk4, pll0_pllen, 5, SYSCLK_FIXED_DIV);
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SYSCLK(5, pll0_sysclk5, pll0_pllen, 5, 0);
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SYSCLK(6, pll0_sysclk6, pll0_pllen, 5, SYSCLK_ARM_RATE | SYSCLK_FIXED_DIV);
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SYSCLK(7, pll0_sysclk7, pll0_pllen, 5, 0);
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static const char * const da850_pll0_obsclk_parent_names[] = {
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"oscin",
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"pll0_sysclk1",
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"pll0_sysclk2",
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"pll0_sysclk3",
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"pll0_sysclk4",
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"pll0_sysclk5",
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"pll0_sysclk6",
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"pll0_sysclk7",
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"pll1_obsclk",
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};
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static u32 da850_pll0_obsclk_table[] = {
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OCSEL_OCSRC_OSCIN,
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OCSEL_OCSRC_PLL0_SYSCLK(1),
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OCSEL_OCSRC_PLL0_SYSCLK(2),
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OCSEL_OCSRC_PLL0_SYSCLK(3),
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OCSEL_OCSRC_PLL0_SYSCLK(4),
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OCSEL_OCSRC_PLL0_SYSCLK(5),
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OCSEL_OCSRC_PLL0_SYSCLK(6),
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OCSEL_OCSRC_PLL0_SYSCLK(7),
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OCSEL_OCSRC_PLL1_OBSCLK,
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};
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static const struct davinci_pll_obsclk_info da850_pll0_obsclk_info = {
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.name = "pll0_obsclk",
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.parent_names = da850_pll0_obsclk_parent_names,
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.num_parents = ARRAY_SIZE(da850_pll0_obsclk_parent_names),
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.table = da850_pll0_obsclk_table,
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.ocsrc_mask = GENMASK(4, 0),
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};
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int da850_pll0_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &da850_pll0_info, "ref_clk", base, cfgchip);
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk1, base);
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clk_register_clkdev(clk, "pll0_sysclk1", "da850-psc0");
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk2, base);
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clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc0");
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clk_register_clkdev(clk, "pll0_sysclk2", "da850-psc1");
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clk_register_clkdev(clk, "pll0_sysclk2", "da850-async3-clksrc");
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk3, base);
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clk_register_clkdev(clk, "pll0_sysclk3", "da850-async1-clksrc");
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk4, base);
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clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc0");
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clk_register_clkdev(clk, "pll0_sysclk4", "da850-psc1");
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davinci_pll_sysclk_register(dev, &pll0_sysclk5, base);
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clk = davinci_pll_sysclk_register(dev, &pll0_sysclk6, base);
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clk_register_clkdev(clk, "pll0_sysclk6", "da850-psc0");
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davinci_pll_sysclk_register(dev, &pll0_sysclk7, base);
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davinci_pll_auxclk_register(dev, "pll0_auxclk", base);
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clk = clk_register_fixed_factor(dev, "async2", "pll0_auxclk",
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CLK_IS_CRITICAL, 1, 1);
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clk_register_clkdev(clk, NULL, "i2c_davinci.1");
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clk_register_clkdev(clk, "timer0", NULL);
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clk_register_clkdev(clk, NULL, "davinci-wdt");
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davinci_pll_obsclk_register(dev, &da850_pll0_obsclk_info, base);
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return 0;
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}
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static const struct davinci_pll_sysclk_info *da850_pll0_sysclk_info[] = {
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&pll0_sysclk1,
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&pll0_sysclk2,
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&pll0_sysclk3,
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&pll0_sysclk4,
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&pll0_sysclk5,
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&pll0_sysclk6,
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&pll0_sysclk7,
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NULL
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};
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void of_da850_pll0_init(struct device_node *node)
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{
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void __iomem *base;
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struct regmap *cfgchip;
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base = of_iomap(node, 0);
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if (!base) {
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pr_err("%s: ioremap failed\n", __func__);
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return;
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}
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cfgchip = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
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of_davinci_pll_init(NULL, node, &da850_pll0_info,
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&da850_pll0_obsclk_info,
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da850_pll0_sysclk_info, 7, base, cfgchip);
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}
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static const struct davinci_pll_clk_info da850_pll1_info = {
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.name = "pll1",
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.unlock_reg = CFGCHIP(3),
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.unlock_mask = CFGCHIP3_PLL1_MASTER_LOCK,
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.pllm_mask = GENMASK(4, 0),
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.pllm_min = 4,
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.pllm_max = 32,
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.pllout_min_rate = 300000000,
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.pllout_max_rate = 600000000,
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.flags = PLL_HAS_POSTDIV,
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};
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SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
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SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, 0);
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SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, 0);
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static const char * const da850_pll1_obsclk_parent_names[] = {
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"oscin",
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"pll1_sysclk1",
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"pll1_sysclk2",
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"pll1_sysclk3",
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};
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static u32 da850_pll1_obsclk_table[] = {
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OCSEL_OCSRC_OSCIN,
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OCSEL_OCSRC_PLL1_SYSCLK(1),
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OCSEL_OCSRC_PLL1_SYSCLK(2),
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OCSEL_OCSRC_PLL1_SYSCLK(3),
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};
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static const struct davinci_pll_obsclk_info da850_pll1_obsclk_info = {
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.name = "pll1_obsclk",
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.parent_names = da850_pll1_obsclk_parent_names,
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.num_parents = ARRAY_SIZE(da850_pll1_obsclk_parent_names),
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.table = da850_pll1_obsclk_table,
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.ocsrc_mask = GENMASK(4, 0),
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};
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int da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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struct clk *clk;
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davinci_pll_clk_register(dev, &da850_pll1_info, "oscin", base, cfgchip);
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davinci_pll_sysclk_register(dev, &pll1_sysclk1, base);
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clk = davinci_pll_sysclk_register(dev, &pll1_sysclk2, base);
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clk_register_clkdev(clk, "pll1_sysclk2", "da850-async3-clksrc");
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davinci_pll_sysclk_register(dev, &pll1_sysclk3, base);
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davinci_pll_obsclk_register(dev, &da850_pll1_obsclk_info, base);
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return 0;
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}
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static const struct davinci_pll_sysclk_info *da850_pll1_sysclk_info[] = {
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&pll1_sysclk1,
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&pll1_sysclk2,
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&pll1_sysclk3,
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NULL
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};
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int of_da850_pll1_init(struct device *dev, void __iomem *base, struct regmap *cfgchip)
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{
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return of_davinci_pll_init(dev, dev->of_node, &da850_pll1_info,
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&da850_pll1_obsclk_info,
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da850_pll1_sysclk_info, 3, base, cfgchip);
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}
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