437 lines
11 KiB
C
437 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2021 MediaTek Inc.
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* Author: Owen Chen <owen.chen@mediatek.com>
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*/
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include <dt-bindings/clock/mt6893-clk.h>
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#define MT_CCF_BRINGUP 1
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/* Regular Number Definition */
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#define INV_OFS -1
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#define INV_BIT -1
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static const struct mtk_gate_regs apu0_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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#define GATE_APU0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apu0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_DUMMY_0(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apu0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_dummy, \
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}
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static const struct mtk_gate apu0_clks[] = {
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GATE_DUMMY_0(CLK_APU0_APU, "apu0_apu",
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"dsp1_ck"/* parent */, 0),
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GATE_DUMMY_0(CLK_APU0_AXI_M, "apu0_axi_m",
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"dsp1_ck"/* parent */, 1),
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GATE_DUMMY_0(CLK_APU0_JTAG, "apu0_jtag",
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"dsp1_ck"/* parent */, 2),
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};
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static const struct mtk_clk_desc apu0_mcd = {
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.clks = apu0_clks,
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.num_clks = CLK_APU0_NR_CLK,
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};
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static const struct mtk_gate_regs apu1_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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#define GATE_APU1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apu1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_DUMMY_1(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apu1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_dummy, \
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}
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static const struct mtk_gate apu1_clks[] = {
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GATE_DUMMY_1(CLK_APU1_APU, "apu1_apu",
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"dsp2_ck"/* parent */, 0),
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GATE_DUMMY_1(CLK_APU1_AXI_M, "apu1_axi_m",
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"dsp2_ck"/* parent */, 1),
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GATE_DUMMY_1(CLK_APU1_JTAG, "apu1_jtag",
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"dsp2_ck"/* parent */, 2),
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};
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static const struct mtk_clk_desc apu1_mcd = {
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.clks = apu1_clks,
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.num_clks = CLK_APU1_NR_CLK,
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};
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static const struct mtk_gate_regs apu2_cg_regs = {
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.set_ofs = 0x104,
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.clr_ofs = 0x108,
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.sta_ofs = 0x100,
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};
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#define GATE_APU2(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apu2_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_DUMMY_2(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apu2_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_dummy, \
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}
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static const struct mtk_gate apu2_clks[] = {
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GATE_DUMMY_2(CLK_APU2_APU, "apu2_apu",
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"dsp3_ck"/* parent */, 0),
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GATE_DUMMY_2(CLK_APU2_AXI_M, "apu2_axi_m",
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"dsp3_ck"/* parent */, 1),
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GATE_DUMMY_2(CLK_APU2_JTAG, "apu2_jtag",
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"dsp3_ck"/* parent */, 2),
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};
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static const struct mtk_clk_desc apu2_mcd = {
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.clks = apu2_clks,
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.num_clks = CLK_APU2_NR_CLK,
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};
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static const struct mtk_gate_regs apuv_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_APUV(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apuv_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_DUMMY_V(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apuv_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_dummy, \
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}
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static const struct mtk_gate apuv_clks[] = {
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GATE_DUMMY_V(CLK_APUV_AHB, "apuv_ahb",
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"ipu_if_ck"/* parent */, 0),
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GATE_DUMMY_V(CLK_APUV_AXI, "apuv_axi",
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"ipu_if_ck"/* parent */, 1),
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GATE_DUMMY_V(CLK_APUV_ADL, "apuv_adl",
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"ipu_if_ck"/* parent */, 2),
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GATE_DUMMY_V(CLK_APUV_QOS, "apuv_qos",
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"ipu_if_ck"/* parent */, 3),
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};
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static const struct mtk_clk_desc apuv_mcd = {
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.clks = apuv_clks,
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.num_clks = CLK_APUV_NR_CLK,
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};
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static const struct mtk_gate_regs apuc_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_APUC(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apuc_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_DUMMY_C(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apuc_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_dummy, \
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}
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static const struct mtk_gate apuc_clks[] = {
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GATE_DUMMY_C(CLK_APUC_AHB, "apuc_ahb",
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"dsp_ck"/* parent */, 1),
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GATE_DUMMY_C(CLK_APUC_AXI, "apuc_axi",
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"dsp_ck"/* parent */, 2),
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GATE_DUMMY_C(CLK_APUC_ISP, "apuc_isp",
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"dsp_ck"/* parent */, 3),
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GATE_DUMMY_C(CLK_APUC_CAM_ADL, "apuc_cam_adl",
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"dsp_ck"/* parent */, 4),
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GATE_DUMMY_C(CLK_APUC_IMG_ADL, "apuc_img_adl",
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"dsp_ck"/* parent */, 5),
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GATE_DUMMY_C(CLK_APUC_EMI_26M, "apuc_emi_26m",
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"dsp_ck"/* parent */, 6),
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GATE_DUMMY_C(CLK_APUC_VPU_UDI, "apuc_vpu_udi",
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"dsp_ck"/* parent */, 7),
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GATE_DUMMY_C(CLK_APUC_EDMA_0, "apuc_edma_0",
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"dsp_ck"/* parent */, 8),
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GATE_DUMMY_C(CLK_APUC_EDMA_1, "apuc_edma_1",
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"dsp_ck"/* parent */, 9),
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GATE_DUMMY_C(CLK_APUC_EDMAL_0, "apuc_edmal_0",
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"dsp_ck"/* parent */, 10),
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GATE_DUMMY_C(CLK_APUC_EDMAL_1, "apuc_edmal_1",
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"dsp_ck"/* parent */, 11),
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GATE_DUMMY_C(CLK_APUC_MNOC, "apuc_mnoc",
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"dsp_ck"/* parent */, 12),
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GATE_DUMMY_C(CLK_APUC_TCM, "apuc_tcm",
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"dsp_ck"/* parent */, 13),
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GATE_DUMMY_C(CLK_APUC_MD32, "apuc_md32",
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"dsp_ck"/* parent */, 14),
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GATE_DUMMY_C(CLK_APUC_IOMMU_0, "apuc_iommu_0",
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"dsp7_ck"/* parent */, 15),
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GATE_DUMMY_C(CLK_APUC_IOMMU_1, "apuc_iommu_1",
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"dsp7_ck"/* parent */, 16),
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GATE_DUMMY_C(CLK_APUC_MD32_32K, "apuc_md32_32k",
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"dsp_ck"/* parent */, 17),
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};
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static const struct mtk_clk_desc apuc_mcd = {
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.clks = apuc_clks,
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.num_clks = CLK_APUC_NR_CLK,
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};
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static const struct mtk_gate_regs apum0_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_APUM0(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apum0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_DUMMY_M0(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apum0_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_dummy, \
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}
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static const struct mtk_gate apum0_clks[] = {
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG0, "apum0_mdla_cg0",
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"dsp6_ck"/* parent */, 0),
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG1, "apum0_mdla_cg1",
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"dsp6_ck"/* parent */, 1),
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG2, "apum0_mdla_cg2",
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"dsp6_ck"/* parent */, 2),
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG3, "apum0_mdla_cg3",
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"dsp6_ck"/* parent */, 3),
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG4, "apum0_mdla_cg4",
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"dsp6_ck"/* parent */, 4),
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG5, "apum0_mdla_cg5",
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"dsp6_ck"/* parent */, 5),
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG6, "apum0_mdla_cg6",
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"dsp6_ck"/* parent */, 6),
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG7, "apum0_mdla_cg7",
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"dsp6_ck"/* parent */, 7),
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG8, "apum0_mdla_cg8",
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"dsp6_ck"/* parent */, 8),
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG9, "apum0_mdla_cg9",
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"dsp6_ck"/* parent */, 9),
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG10, "apum0_mdla_cg10",
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"dsp6_ck"/* parent */, 10),
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG11, "apum0_mdla_cg11",
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"dsp6_ck"/* parent */, 11),
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GATE_DUMMY_M0(CLK_APUM0_MDLA_CG12, "apum0_mdla_cg12",
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"dsp6_ck"/* parent */, 12),
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GATE_DUMMY_M0(CLK_APUM0_APB, "apum0_apb",
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"dsp6_ck"/* parent */, 13),
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GATE_DUMMY_M0(CLK_APUM0_AXI_M, "apum0_axi_m",
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"dsp6_ck"/* parent */, 14),
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};
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static const struct mtk_clk_desc apum0_mcd = {
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.clks = apum0_clks,
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.num_clks = CLK_APUM0_NR_CLK,
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};
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static const struct mtk_gate_regs apum1_cg_regs = {
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.set_ofs = 0x4,
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.clr_ofs = 0x8,
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.sta_ofs = 0x0,
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};
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#define GATE_APUM1(_id, _name, _parent, _shift) { \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apum1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr, \
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}
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#define GATE_DUMMY_M1(_id, _name, _parent, _shift) {\
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &apum1_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_setclr_dummy, \
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}
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static const struct mtk_gate apum1_clks[] = {
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG0, "apum1_mdla_cg0",
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"dsp6_ck"/* parent */, 0),
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG1, "apum1_mdla_cg1",
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"dsp6_ck"/* parent */, 1),
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG2, "apum1_mdla_cg2",
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"dsp6_ck"/* parent */, 2),
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG3, "apum1_mdla_cg3",
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"dsp6_ck"/* parent */, 3),
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG4, "apum1_mdla_cg4",
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"dsp6_ck"/* parent */, 4),
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG5, "apum1_mdla_cg5",
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"dsp6_ck"/* parent */, 5),
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG6, "apum1_mdla_cg6",
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"dsp6_ck"/* parent */, 6),
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG7, "apum1_mdla_cg7",
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"dsp6_ck"/* parent */, 7),
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG8, "apum1_mdla_cg8",
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"dsp6_ck"/* parent */, 8),
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG9, "apum1_mdla_cg9",
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"dsp6_ck"/* parent */, 9),
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG10, "apum1_mdla_cg10",
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"dsp6_ck"/* parent */, 10),
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG11, "apum1_mdla_cg11",
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"dsp6_ck"/* parent */, 11),
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GATE_DUMMY_M1(CLK_APUM1_MDLA_CG12, "apum1_mdla_cg12",
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"dsp6_ck"/* parent */, 12),
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GATE_DUMMY_M1(CLK_APUM1_APB, "apum1_apb",
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"dsp6_ck"/* parent */, 13),
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GATE_DUMMY_M1(CLK_APUM1_AXI_M, "apum1_axi_m",
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"dsp6_ck"/* parent */, 14),
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};
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static const struct mtk_clk_desc apum1_mcd = {
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.clks = apum1_clks,
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.num_clks = CLK_APUM1_NR_CLK,
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};
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static const struct of_device_id of_match_clk_mt6893_apu[] = {
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{
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.compatible = "mediatek,mt6893-apu0",
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.data = &apu0_mcd,
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}, {
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.compatible = "mediatek,mt6893-apu1",
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.data = &apu1_mcd,
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}, {
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.compatible = "mediatek,mt6893-apu2",
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.data = &apu2_mcd,
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}, {
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.compatible = "mediatek,mt6893-apu_vcore",
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.data = &apuv_mcd,
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}, {
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.compatible = "mediatek,mt6893-apu_conn",
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.data = &apuc_mcd,
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}, {
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.compatible = "mediatek,mt6893-apu_mdla0",
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.data = &apum0_mcd,
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}, {
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.compatible = "mediatek,mt6893-apu_mdla1",
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.data = &apum1_mcd,
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}, {
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/* sentinel */
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}
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};
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static int clk_mt6893_apu_grp_probe(struct platform_device *pdev)
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{
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int r;
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#if MT_CCF_BRINGUP
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pr_notice("%s: %s init begin\n", __func__, pdev->name);
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#endif
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r = mtk_clk_simple_probe(pdev);
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if (r)
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dev_err(&pdev->dev,
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"could not register clock provider: %s: %d\n",
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pdev->name, r);
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#if MT_CCF_BRINGUP
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pr_notice("%s: %s init end\n", __func__, pdev->name);
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#endif
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return r;
|
|
}
|
|
|
|
static struct platform_driver clk_mt6893_apu_drv = {
|
|
.probe = clk_mt6893_apu_grp_probe,
|
|
.driver = {
|
|
.name = "clk-mt6893-apu",
|
|
.of_match_table = of_match_clk_mt6893_apu,
|
|
},
|
|
};
|
|
|
|
static int __init clk_mt6893_apu_init(void)
|
|
{
|
|
return platform_driver_register(&clk_mt6893_apu_drv);
|
|
}
|
|
|
|
static void __exit clk_mt6893_apu_exit(void)
|
|
{
|
|
platform_driver_unregister(&clk_mt6893_apu_drv);
|
|
}
|
|
|
|
postcore_initcall(clk_mt6893_apu_init);
|
|
module_exit(clk_mt6893_apu_exit);
|
|
MODULE_LICENSE("GPL");
|