160 lines
3.9 KiB
C
160 lines
3.9 KiB
C
/*
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* Copyright 2016 Maxime Ripard
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*
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/iopoll.h>
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#include <linux/slab.h>
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#include "ccu_common.h"
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#include "ccu_gate.h"
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#include "ccu_reset.h"
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static DEFINE_SPINLOCK(ccu_lock);
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void ccu_helper_wait_for_lock(struct ccu_common *common, u32 lock)
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{
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void __iomem *addr;
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u32 reg;
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if (!lock)
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return;
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if (common->features & CCU_FEATURE_LOCK_REG)
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addr = common->base + common->lock_reg;
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else
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addr = common->base + common->reg;
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WARN_ON(readl_relaxed_poll_timeout(addr, reg, reg & lock, 100, 70000));
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}
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/*
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* This clock notifier is called when the frequency of a PLL clock is
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* changed. In common PLL designs, changes to the dividers take effect
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* almost immediately, while changes to the multipliers (implemented
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* as dividers in the feedback loop) take a few cycles to work into
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* the feedback loop for the PLL to stablize.
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*
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* Sometimes when the PLL clock rate is changed, the decrease in the
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* divider is too much for the decrease in the multiplier to catch up.
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* The PLL clock rate will spike, and in some cases, might lock up
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* completely.
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*
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* This notifier callback will gate and then ungate the clock,
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* effectively resetting it, so it proceeds to work. Care must be
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* taken to reparent consumers to other temporary clocks during the
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* rate change, and that this notifier callback must be the first
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* to be registered.
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*/
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static int ccu_pll_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct ccu_pll_nb *pll = to_ccu_pll_nb(nb);
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int ret = 0;
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if (event != POST_RATE_CHANGE)
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goto out;
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ccu_gate_helper_disable(pll->common, pll->enable);
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ret = ccu_gate_helper_enable(pll->common, pll->enable);
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if (ret)
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goto out;
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ccu_helper_wait_for_lock(pll->common, pll->lock);
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out:
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return notifier_from_errno(ret);
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}
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int ccu_pll_notifier_register(struct ccu_pll_nb *pll_nb)
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{
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pll_nb->clk_nb.notifier_call = ccu_pll_notifier_cb;
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return clk_notifier_register(pll_nb->common->hw.clk,
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&pll_nb->clk_nb);
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}
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int sunxi_ccu_probe(struct device_node *node, void __iomem *reg,
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const struct sunxi_ccu_desc *desc)
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{
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struct ccu_reset *reset;
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int i, ret;
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for (i = 0; i < desc->num_ccu_clks; i++) {
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struct ccu_common *cclk = desc->ccu_clks[i];
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if (!cclk)
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continue;
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cclk->base = reg;
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cclk->lock = &ccu_lock;
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}
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for (i = 0; i < desc->hw_clks->num ; i++) {
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struct clk_hw *hw = desc->hw_clks->hws[i];
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if (!hw)
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continue;
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ret = clk_hw_register(NULL, hw);
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if (ret) {
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pr_err("Couldn't register clock %d - %s\n",
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i, clk_hw_get_name(hw));
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goto err_clk_unreg;
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}
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}
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ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
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desc->hw_clks);
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if (ret)
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goto err_clk_unreg;
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reset = kzalloc(sizeof(*reset), GFP_KERNEL);
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if (!reset) {
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ret = -ENOMEM;
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goto err_alloc_reset;
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}
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reset->rcdev.of_node = node;
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reset->rcdev.ops = &ccu_reset_ops;
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reset->rcdev.owner = THIS_MODULE;
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reset->rcdev.nr_resets = desc->num_resets;
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reset->base = reg;
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reset->lock = &ccu_lock;
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reset->reset_map = desc->resets;
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ret = reset_controller_register(&reset->rcdev);
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if (ret)
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goto err_of_clk_unreg;
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return 0;
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err_of_clk_unreg:
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kfree(reset);
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err_alloc_reset:
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of_clk_del_provider(node);
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err_clk_unreg:
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while (--i >= 0) {
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struct clk_hw *hw = desc->hw_clks->hws[i];
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if (!hw)
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continue;
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clk_hw_unregister(hw);
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}
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return ret;
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}
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