419 lines
12 KiB
C
419 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/spmi.h>
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#include <linux/regmap.h>
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#include <linux/of_platform.h>
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#include <linux/interrupt.h>
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#include <linux/of_irq.h>
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#include <dt-bindings/mfd/mt6362.h>
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#define MT6362_IRQ_SET (0x0D)
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#define MT6362_REG_TM_PASCODE1 (0x07)
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#define MT6362_REG_SPMIM_RCS1 (0x68)
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#define MT6362_REG_SPMIM_RCS2 (0x69)
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#define MT6362_CHG_IRQ0 (0xD0)
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#define MT6362_PD_IRQ (0xDF)
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#define MT6362_IRQ_REGS (MT6362_PD_IRQ - MT6362_CHG_IRQ0 + 1)
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#define MT6362_CHG_MASK0 (0xF0)
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#define MT6362_INT_RETRIG BIT(2)
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#define MT6362_REGMAP_IRQ_REG(_irq_evt) \
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REGMAP_IRQ_REG(_irq_evt, (_irq_evt) / 8, BIT((_irq_evt) % 8))
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#define MT6362_SPMIMST_RCSCLR
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#define MT6362_SPMIMST_STARTADDR (0x10029000)
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#define MT6362_SPMIMST_ENDADDR (0x100290FF)
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#define MT6362_REG_SPMIMST_RCSCLR (0x28)
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#define MT6362_MSK_SPMIMST_RCSCLR (0xFF00)
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struct mt6362_data {
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struct spmi_device *sdev;
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struct device *dev;
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struct regmap *regmap;
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struct regmap_irq_chip_data *irq_data;
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struct regmap_irq_chip irq_chip;
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unsigned int last_access_reg;
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ktime_t last_access_time;
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int irq;
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#ifdef MT6362_SPMIMST_RCSCLR
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__iomem void *spmimst_base;
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#endif /* MT6362_SPMIMST_RCSCLR */
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};
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struct init_table {
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u16 addr;
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u8 mask;
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u8 val;
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bool hidden_flag;
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};
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static const struct init_table mt6362_init_table[] = {
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/* PMIC PART */
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{0X120, 0X77, 0X55, false},
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{0X130, 0X77, 0X55, false},
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{0X140, 0X77, 0X22, false},
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/* BUCK PART */
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{0X21D, 0X77, 0X55, false},
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{0X221, 0X77, 0X55, false},
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{0X223, 0X77, 0X55, false},
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/* LDO PART */
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{0X310, 0X77, 0X11, false},
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};
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static const struct regmap_irq spmi_regmap_irqs[] = {
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MT6362_REGMAP_IRQ_REG(MT6362_FL_PWR_RDY),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_DETACH),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_RECHG),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_CHG_DONE),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_FL_BK_CHG),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_IEOC),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_CHG_RDY),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_VBUS_GD),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_VBUS_OV),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED2_STRB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED1_STRB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_CHG_BATOV),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_CHG_SYSOV),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_CHG_TOUT),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_CHG_BUSUV),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_CHG_THREG),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_CHG_AICR),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_CHG_MIVR),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_SYS_SHORT),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_SYS_MIN),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_AICC_DONE),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_PE_DONE),
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MT6362_REGMAP_IRQ_REG(MT6362_PP_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FT_DIG_THR),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_WDT),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_OTG_FAULT),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_OTG_BAT_LBP),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_OTG_CC),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_BC12_HVDCP),
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MT6362_REGMAP_IRQ_REG(MT6362_FL_BC12_DN),
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MT6362_REGMAP_IRQ_REG(MT6362_INT_CHRDET_UV),
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MT6362_REGMAP_IRQ_REG(MT6362_INT_CHRDET_OV),
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MT6362_REGMAP_IRQ_REG(MT6362_INT_CHRDET_EXT),
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MT6362_REGMAP_IRQ_REG(MT6362_ADC_DONEI),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED_STRBPIN_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED_TORPIN_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED_TX_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED_LVF_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED_LBP_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED_CHGVINOVP_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED2_SHORT_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED1_SHORT_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED2_STRB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED1_STRB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED2_STRB_TO_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED1_STRB_TO_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED2_TOR_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_FLED1_TOR_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_APWDTRST_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_EN_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_QONB_RST_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_MRSTB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_VDDAOV_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_SYSUV_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_OTP0_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_OTP1_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_OTP2_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_OTP3_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_OTP4_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_OTP5_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_BUCK1_OC_SDN_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_BUCK2_OC_SDN_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_BUCK3_OC_SDN_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_BUCK4_OC_SDN_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_BUCK5_OC_SDN_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_BUCK6_OC_SDN_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_BUCK1_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_BUCK2_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_BUCK3_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_BUCK4_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_BUCK5_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_BUCK6_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO1_OC_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO2_OC_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO3_OC_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO4_OC_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO5_OC_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO6_OC_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO7_OC_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_VDIG18_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO1_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO2_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO3_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO4_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO5_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO6_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_LDO7_PGB_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_USBID_EVT),
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MT6362_REGMAP_IRQ_REG(MT6362_PD_EVT),
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};
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#ifdef MT6362_SPMIMST_RCSCLR
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static inline void mt6362_clear_spmimst_rcs(struct mt6362_data *data)
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{
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writel(MT6362_MSK_SPMIMST_RCSCLR,
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(data->spmimst_base + MT6362_REG_SPMIMST_RCSCLR));
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}
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#endif /* MT6362_SPMIMST_RCSCLR */
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static int mt6362_handle_post_irq(void *irq_drv_data)
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{
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struct mt6362_data *data = irq_drv_data;
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struct regmap *regmap = data->regmap;
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#ifdef MT6362_SPMIMST_RCSCLR
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mt6362_clear_spmimst_rcs(data);
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#endif /* MT6362_SPMIMST_RCSCLR */
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return regmap_update_bits(regmap, MT6362_IRQ_SET, MT6362_INT_RETRIG,
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MT6362_INT_RETRIG);
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}
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static const struct regmap_irq_chip spmi_regmap_irq_chip = {
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.name = "mt6362_spmi",
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.irqs = spmi_regmap_irqs,
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.num_irqs = ARRAY_SIZE(spmi_regmap_irqs),
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.num_regs = MT6362_IRQ_REGS,
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.status_base = MT6362_CHG_IRQ0,
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.mask_base = MT6362_CHG_MASK0,
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.ack_base = MT6362_CHG_IRQ0,
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.init_ack_masked = true,
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.use_ack = true,
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.handle_post_irq = mt6362_handle_post_irq,
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};
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static int mt6362_spmi_reg_read(void *context,
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unsigned int reg, unsigned int *val)
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{
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struct mt6362_data *data = context;
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ktime_t current_time, avail_access_time;
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u8 regval = 0;
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int ret;
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if (reg == data->last_access_reg) {
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avail_access_time = ktime_add_us(data->last_access_time, 3);
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current_time = ktime_get();
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if (ktime_before(current_time, avail_access_time)) {
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/* used for usec time ceil */
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avail_access_time = ktime_add_ns(avail_access_time,
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NSEC_PER_USEC - 1);
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udelay(ktime_us_delta(avail_access_time, current_time));
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}
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}
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ret = spmi_ext_register_readl(data->sdev, reg, ®val, 1);
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if (ret < 0)
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return ret;
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*val = regval;
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return 0;
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}
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static int mt6362_spmi_reg_write(void *context,
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unsigned int reg, unsigned int val)
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{
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struct mt6362_data *data = context;
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int ret;
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ret = spmi_ext_register_writel(data->sdev, reg, (u8 *)&val, 1);
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if (ret)
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return ret;
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data->last_access_reg = reg;
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data->last_access_time = ktime_get();
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return 0;
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}
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static const struct regmap_config spmi_regmap_config = {
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.reg_bits = 16,
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.val_bits = 8,
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.max_register = 0x7ff,
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.fast_io = true,
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.use_single_rw = true,
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.reg_read = mt6362_spmi_reg_read,
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.reg_write = mt6362_spmi_reg_write,
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};
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#ifdef CONFIG_FPGA_EARLY_PORTING
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static int mt6362_spmi_rcs_init(struct mt6362_data *data)
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{
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struct regmap *regmap = data->regmap;
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int ret;
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dev_info(dev, "%s\n", __func__);
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/* rcs_enable[7], rcs_a[6], rcs_cmd[5:4], rcs_id[3:0] */
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ret = regmap_write(regmap, MT6362_REG_SPMIM_RCS1, 0x91);
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if (ret < 0)
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return ret;
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/* rcs_addr */
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return regmap_write(regmap, MT6362_REG_SPMIM_RCS2, 0x09);
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}
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#endif /* CONFIG_FPGA_EARLY_PORTING */
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static int mt6362_enable_hidden_mode(struct mt6362_data *data, bool en)
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{
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return regmap_write(data->regmap,
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MT6362_REG_TM_PASCODE1, en ? 0x69 : 0);
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}
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static int mt6362_init_setting(struct mt6362_data *data)
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{
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int i, ret;
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/* initial setting */
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for (i = 0; i < ARRAY_SIZE(mt6362_init_table); i++) {
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if (mt6362_init_table[i].hidden_flag) {
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ret = mt6362_enable_hidden_mode(data, true);
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if (ret < 0)
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return ret;
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}
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ret = regmap_update_bits(data->regmap,
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mt6362_init_table[i].addr,
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mt6362_init_table[i].mask,
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mt6362_init_table[i].val);
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if (mt6362_init_table[i].hidden_flag)
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mt6362_enable_hidden_mode(data, false);
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if (ret < 0)
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return ret;
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}
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return ret;
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}
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#ifdef MT6362_SPMIMST_RCSCLR
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static struct resource spmimst_resource = {
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.start = MT6362_SPMIMST_STARTADDR,
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.end = MT6362_SPMIMST_ENDADDR,
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.flags = IORESOURCE_MEM,
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.name = "spmimst",
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};
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#endif /* MT6362_SPMIMST_RCSCLR */
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static int mt6362_probe(struct spmi_device *sdev)
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{
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struct mt6362_data *data;
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struct regmap *regmap;
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struct device_node *np = sdev->dev.of_node;
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int rv;
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data = devm_kzalloc(&sdev->dev, sizeof(*data), GFP_KERNEL);
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if (!data)
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return -ENOMEM;
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data->sdev = sdev;
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data->dev = &sdev->dev;
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data->last_access_reg = U32_MAX;
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spmi_device_set_drvdata(sdev, data);
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regmap = devm_regmap_init(&sdev->dev, NULL, data, &spmi_regmap_config);
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if (IS_ERR(regmap))
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return PTR_ERR(regmap);
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data->regmap = regmap;
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#ifdef CONFIG_FPGA_EARLY_PORTING
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rv = mt6362_spmi_rcs_init(data);
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if (rv < 0) {
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dev_err(&sdev->dev, "%s: spmi rcs init failed\n", __func__);
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return rv;
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}
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#endif /* CONFIG_FPGA_EARLY_PORTING */
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rv = mt6362_init_setting(data);
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if (rv) {
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dev_err(&sdev->dev, "Failed to set initial setting(%d)\n", rv);
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return rv;
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}
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#ifdef MT6362_SPMIMST_RCSCLR
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data->spmimst_base = devm_ioremap(&sdev->dev, spmimst_resource.start,
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resource_size(&spmimst_resource));
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if (!data->spmimst_base) {
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dev_notice(&sdev->dev,
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"Failed to ioremap spmi master address\n");
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return -EINVAL;
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}
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mt6362_clear_spmimst_rcs(data);
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#endif /* MT6362_SPMIMST_RCSCLR */
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data->irq = of_irq_get(np, 0);
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if (data->irq < 0) {
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dev_err(&sdev->dev, "Failed to get irq(%d)\n", data->irq);
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return data->irq;
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}
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memcpy(&data->irq_chip, &spmi_regmap_irq_chip, sizeof(data->irq_chip));
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data->irq_chip.irq_drv_data = data;
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rv = devm_regmap_add_irq_chip(&sdev->dev, regmap, data->irq,
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IRQF_ONESHOT, 0, &data->irq_chip,
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&data->irq_data);
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if (rv) {
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dev_err(&sdev->dev, "Failed to add irq chip(%d)\n", rv);
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return rv;
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}
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rv = devm_of_platform_populate(&sdev->dev);
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if (rv) {
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dev_err(&sdev->dev, "Failed to populate children(%d)\n", rv);
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return rv;
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}
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device_init_wakeup(&sdev->dev, true);
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return 0;
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}
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static int __maybe_unused mt6362_suspend(struct device *dev)
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{
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struct mt6362_data *data = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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enable_irq_wake(data->irq);
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disable_irq(data->irq);
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dev_info(dev, "%s: done\n", __func__);
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return 0;
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}
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static int __maybe_unused mt6362_resume(struct device *dev)
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{
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struct mt6362_data *data = dev_get_drvdata(dev);
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if (device_may_wakeup(dev))
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disable_irq_wake(data->irq);
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enable_irq(data->irq);
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dev_info(dev, "%s: done\n", __func__);
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return 0;
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}
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static SIMPLE_DEV_PM_OPS(mt6362_pm_ops, mt6362_suspend, mt6362_resume);
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static const struct of_device_id __maybe_unused mt6362_ofid_tbls[] = {
|
|
{ .compatible = "mediatek,mt6362", },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mt6362_of_id);
|
|
|
|
static struct spmi_driver mt6362_driver = {
|
|
.driver = {
|
|
.name = "mt6362",
|
|
.of_match_table = of_match_ptr(mt6362_ofid_tbls),
|
|
.pm = &mt6362_pm_ops,
|
|
},
|
|
.probe = mt6362_probe,
|
|
};
|
|
module_spmi_driver(mt6362_driver);
|
|
|
|
MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
|
|
MODULE_DESCRIPTION("MT6362 SPMI PMIC Driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_VERSION("1.0.0");
|