261 lines
7.9 KiB
C
261 lines
7.9 KiB
C
/*
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* Copyright (c) 2005-2011 Atheros Communications Inc.
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* Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef _PCI_H_
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#define _PCI_H_
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#include <linux/interrupt.h>
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#include "hw.h"
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#include "ce.h"
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#include "ahb.h"
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/*
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* maximum number of bytes that can be
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* handled atomically by DiagRead/DiagWrite
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*/
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#define DIAG_TRANSFER_LIMIT 2048
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struct bmi_xfer {
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bool tx_done;
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bool rx_done;
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bool wait_for_resp;
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u32 resp_len;
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};
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/*
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* PCI-specific Target state
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*
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* NOTE: Structure is shared between Host software and Target firmware!
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*
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* Much of this may be of interest to the Host so
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* HOST_INTEREST->hi_interconnect_state points here
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* (and all members are 32-bit quantities in order to
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* facilitate Host access). In particular, Host software is
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* required to initialize pipe_cfg_addr and svc_to_pipe_map.
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*/
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struct pcie_state {
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/* Pipe configuration Target address */
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/* NB: ce_pipe_config[CE_COUNT] */
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u32 pipe_cfg_addr;
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/* Service to pipe map Target address */
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/* NB: service_to_pipe[PIPE_TO_CE_MAP_CN] */
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u32 svc_to_pipe_map;
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/* number of MSI interrupts requested */
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u32 msi_requested;
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/* number of MSI interrupts granted */
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u32 msi_granted;
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/* Message Signalled Interrupt address */
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u32 msi_addr;
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/* Base data */
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u32 msi_data;
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/*
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* Data for firmware interrupt;
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* MSI data for other interrupts are
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* in various SoC registers
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*/
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u32 msi_fw_intr_data;
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/* PCIE_PWR_METHOD_* */
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u32 power_mgmt_method;
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/* PCIE_CONFIG_FLAG_* */
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u32 config_flags;
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};
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/* PCIE_CONFIG_FLAG definitions */
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#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
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/* Per-pipe state. */
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struct ath10k_pci_pipe {
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/* Handle of underlying Copy Engine */
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struct ath10k_ce_pipe *ce_hdl;
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/* Our pipe number; facilitiates use of pipe_info ptrs. */
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u8 pipe_num;
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/* Convenience back pointer to hif_ce_state. */
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struct ath10k *hif_ce_state;
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size_t buf_sz;
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/* protects compl_free and num_send_allowed */
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spinlock_t pipe_lock;
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};
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struct ath10k_pci_supp_chip {
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u32 dev_id;
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u32 rev_id;
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};
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enum ath10k_pci_irq_mode {
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ATH10K_PCI_IRQ_AUTO = 0,
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ATH10K_PCI_IRQ_LEGACY = 1,
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ATH10K_PCI_IRQ_MSI = 2,
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};
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struct ath10k_pci {
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struct pci_dev *pdev;
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struct device *dev;
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struct ath10k *ar;
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void __iomem *mem;
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size_t mem_len;
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/* Operating interrupt mode */
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enum ath10k_pci_irq_mode oper_irq_mode;
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struct ath10k_pci_pipe pipe_info[CE_COUNT_MAX];
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/* Copy Engine used for Diagnostic Accesses */
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struct ath10k_ce_pipe *ce_diag;
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struct ath10k_ce ce;
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struct timer_list rx_post_retry;
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/* Due to HW quirks it is recommended to disable ASPM during device
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* bootup. To do that the original PCI-E Link Control is stored before
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* device bootup is executed and re-programmed later.
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*/
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u16 link_ctl;
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/* Protects ps_awake and ps_wake_refcount */
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spinlock_t ps_lock;
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/* The device has a special powersave-oriented register. When device is
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* considered asleep it drains less power and driver is forbidden from
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* accessing most MMIO registers. If host were to access them without
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* waking up the device might scribble over host memory or return
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* 0xdeadbeef readouts.
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*/
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unsigned long ps_wake_refcount;
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/* Waking up takes some time (up to 2ms in some cases) so it can be bad
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* for latency. To mitigate this the device isn't immediately allowed
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* to sleep after all references are undone - instead there's a grace
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* period after which the powersave register is updated unless some
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* activity to/from device happened in the meantime.
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*
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* Also see comments on ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC.
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*/
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struct timer_list ps_timer;
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/* MMIO registers are used to communicate with the device. With
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* intensive traffic accessing powersave register would be a bit
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* wasteful overhead and would needlessly stall CPU. It is far more
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* efficient to rely on a variable in RAM and update it only upon
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* powersave register state changes.
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*/
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bool ps_awake;
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/* pci power save, disable for QCA988X and QCA99X0.
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* Writing 'false' to this variable avoids frequent locking
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* on MMIO read/write.
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*/
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bool pci_ps;
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/* Chip specific pci reset routine used to do a safe reset */
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int (*pci_soft_reset)(struct ath10k *ar);
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/* Chip specific pci full reset function */
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int (*pci_hard_reset)(struct ath10k *ar);
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/* chip specific methods for converting target CPU virtual address
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* space to CE address space
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*/
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u32 (*targ_cpu_to_ce_addr)(struct ath10k *ar, u32 addr);
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/* Keep this entry in the last, memory for struct ath10k_ahb is
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* allocated (ahb support enabled case) in the continuation of
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* this struct.
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*/
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struct ath10k_ahb ahb[0];
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};
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static inline struct ath10k_pci *ath10k_pci_priv(struct ath10k *ar)
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{
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return (struct ath10k_pci *)ar->drv_priv;
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}
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#define ATH10K_PCI_RX_POST_RETRY_MS 50
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#define ATH_PCI_RESET_WAIT_MAX 10 /* ms */
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#define PCIE_WAKE_TIMEOUT 30000 /* 30ms */
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#define PCIE_WAKE_LATE_US 10000 /* 10ms */
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#define BAR_NUM 0
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#define CDC_WAR_MAGIC_STR 0xceef0000
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#define CDC_WAR_DATA_CE 4
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/* Wait up to this many Ms for a Diagnostic Access CE operation to complete */
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#define DIAG_ACCESS_CE_TIMEOUT_MS 10
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void ath10k_pci_write32(struct ath10k *ar, u32 offset, u32 value);
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void ath10k_pci_soc_write32(struct ath10k *ar, u32 addr, u32 val);
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void ath10k_pci_reg_write32(struct ath10k *ar, u32 addr, u32 val);
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u32 ath10k_pci_read32(struct ath10k *ar, u32 offset);
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u32 ath10k_pci_soc_read32(struct ath10k *ar, u32 addr);
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u32 ath10k_pci_reg_read32(struct ath10k *ar, u32 addr);
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int ath10k_pci_hif_tx_sg(struct ath10k *ar, u8 pipe_id,
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struct ath10k_hif_sg_item *items, int n_items);
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int ath10k_pci_hif_diag_read(struct ath10k *ar, u32 address, void *buf,
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size_t buf_len);
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int ath10k_pci_diag_write_mem(struct ath10k *ar, u32 address,
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const void *data, int nbytes);
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int ath10k_pci_hif_exchange_bmi_msg(struct ath10k *ar, void *req, u32 req_len,
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void *resp, u32 *resp_len);
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int ath10k_pci_hif_map_service_to_pipe(struct ath10k *ar, u16 service_id,
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u8 *ul_pipe, u8 *dl_pipe);
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void ath10k_pci_hif_get_default_pipe(struct ath10k *ar, u8 *ul_pipe,
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u8 *dl_pipe);
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void ath10k_pci_hif_send_complete_check(struct ath10k *ar, u8 pipe,
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int force);
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u16 ath10k_pci_hif_get_free_queue_number(struct ath10k *ar, u8 pipe);
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void ath10k_pci_hif_power_down(struct ath10k *ar);
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int ath10k_pci_alloc_pipes(struct ath10k *ar);
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void ath10k_pci_free_pipes(struct ath10k *ar);
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void ath10k_pci_free_pipes(struct ath10k *ar);
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void ath10k_pci_rx_replenish_retry(struct timer_list *t);
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void ath10k_pci_ce_deinit(struct ath10k *ar);
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void ath10k_pci_init_napi(struct ath10k *ar);
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int ath10k_pci_init_pipes(struct ath10k *ar);
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int ath10k_pci_init_config(struct ath10k *ar);
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void ath10k_pci_rx_post(struct ath10k *ar);
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void ath10k_pci_flush(struct ath10k *ar);
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void ath10k_pci_enable_legacy_irq(struct ath10k *ar);
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bool ath10k_pci_irq_pending(struct ath10k *ar);
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void ath10k_pci_disable_and_clear_legacy_irq(struct ath10k *ar);
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void ath10k_pci_irq_msi_fw_mask(struct ath10k *ar);
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int ath10k_pci_wait_for_target_init(struct ath10k *ar);
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int ath10k_pci_setup_resource(struct ath10k *ar);
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void ath10k_pci_release_resource(struct ath10k *ar);
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/* QCA6174 is known to have Tx/Rx issues when SOC_WAKE register is poked too
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* frequently. To avoid this put SoC to sleep after a very conservative grace
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* period. Adjust with great care.
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*/
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#define ATH10K_PCI_SLEEP_GRACE_PERIOD_MSEC 60
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#endif /* _PCI_H_ */
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