466 lines
23 KiB
C
466 lines
23 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _HARDWARE_MANAGER_H_
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#define _HARDWARE_MANAGER_H_
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struct pp_hwmgr;
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struct pp_hw_power_state;
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struct pp_power_state;
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enum amd_dpm_forced_level;
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struct PP_TemperatureRange;
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struct phm_fan_speed_info {
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uint32_t min_percent;
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uint32_t max_percent;
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uint32_t min_rpm;
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uint32_t max_rpm;
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bool supports_percent_read;
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bool supports_percent_write;
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bool supports_rpm_read;
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bool supports_rpm_write;
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};
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/* Automatic Power State Throttling */
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enum PHM_AutoThrottleSource
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{
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PHM_AutoThrottleSource_Thermal,
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PHM_AutoThrottleSource_External
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};
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typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
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enum phm_platform_caps {
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PHM_PlatformCaps_AtomBiosPpV1 = 0,
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PHM_PlatformCaps_PowerPlaySupport,
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PHM_PlatformCaps_ACOverdriveSupport,
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PHM_PlatformCaps_BacklightSupport,
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PHM_PlatformCaps_ThermalController,
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PHM_PlatformCaps_BiosPowerSourceControl,
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PHM_PlatformCaps_DisableVoltageTransition,
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PHM_PlatformCaps_DisableEngineTransition,
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PHM_PlatformCaps_DisableMemoryTransition,
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PHM_PlatformCaps_DynamicPowerManagement,
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PHM_PlatformCaps_EnableASPML0s,
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PHM_PlatformCaps_EnableASPML1,
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PHM_PlatformCaps_OD5inACSupport,
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PHM_PlatformCaps_OD5inDCSupport,
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PHM_PlatformCaps_SoftStateOD5,
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PHM_PlatformCaps_NoOD5Support,
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PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
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PHM_PlatformCaps_ActivityReporting,
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PHM_PlatformCaps_EnableBackbias,
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PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
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PHM_PlatformCaps_ShowPowerBudgetWarning,
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PHM_PlatformCaps_PowerBudgetWaiverAvailable,
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PHM_PlatformCaps_GFXClockGatingSupport,
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PHM_PlatformCaps_MMClockGatingSupport,
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PHM_PlatformCaps_AutomaticDCTransition,
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PHM_PlatformCaps_GeminiPrimary,
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PHM_PlatformCaps_MemorySpreadSpectrumSupport,
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PHM_PlatformCaps_EngineSpreadSpectrumSupport,
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PHM_PlatformCaps_StepVddc,
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PHM_PlatformCaps_DynamicPCIEGen2Support,
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PHM_PlatformCaps_SMC,
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PHM_PlatformCaps_FaultyInternalThermalReading, /* Internal thermal controller reports faulty temperature value when DAC2 is active */
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PHM_PlatformCaps_EnableVoltageControl, /* indicates voltage can be controlled */
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PHM_PlatformCaps_EnableSideportControl, /* indicates Sideport can be controlled */
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PHM_PlatformCaps_VideoPlaybackEEUNotification, /* indicates EEU notification of video start/stop is required */
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PHM_PlatformCaps_TurnOffPll_ASPML1, /* PCIE Turn Off PLL in ASPM L1 */
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PHM_PlatformCaps_EnableHTLinkControl, /* indicates HT Link can be controlled by ACPI or CLMC overridden/automated mode. */
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PHM_PlatformCaps_PerformanceStateOnly, /* indicates only performance power state to be used on current system. */
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PHM_PlatformCaps_ExclusiveModeAlwaysHigh, /* In Exclusive (3D) mode always stay in High state. */
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PHM_PlatformCaps_DisableMGClockGating, /* to disable Medium Grain Clock Gating or not */
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PHM_PlatformCaps_DisableMGCGTSSM, /* TO disable Medium Grain Clock Gating Shader Complex control */
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PHM_PlatformCaps_UVDAlwaysHigh, /* In UVD mode always stay in High state */
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PHM_PlatformCaps_DisablePowerGating, /* to disable power gating */
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PHM_PlatformCaps_CustomThermalPolicy, /* indicates only performance power state to be used on current system. */
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PHM_PlatformCaps_StayInBootState, /* Stay in Boot State, do not do clock/voltage or PCIe Lane and Gen switching (RV7xx and up). */
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PHM_PlatformCaps_SMCAllowSeparateSWThermalState, /* SMC use separate SW thermal state, instead of the default SMC thermal policy. */
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PHM_PlatformCaps_MultiUVDStateSupport, /* Powerplay state table supports multi UVD states. */
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PHM_PlatformCaps_EnableSCLKDeepSleepForUVD, /* With HW ECOs, we don't need to disable SCLK Deep Sleep for UVD state. */
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PHM_PlatformCaps_EnableMCUHTLinkControl, /* Enable HT link control by MCU */
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PHM_PlatformCaps_ABM, /* ABM support.*/
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PHM_PlatformCaps_KongThermalPolicy, /* A thermal policy specific for Kong */
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PHM_PlatformCaps_SwitchVDDNB, /* if the users want to switch VDDNB */
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PHM_PlatformCaps_ULPS, /* support ULPS mode either through ACPI state or ULPS state */
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PHM_PlatformCaps_NativeULPS, /* hardware capable of ULPS state (other than through the ACPI state) */
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PHM_PlatformCaps_EnableMVDDControl, /* indicates that memory voltage can be controlled */
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PHM_PlatformCaps_ControlVDDCI, /* Control VDDCI separately from VDDC. */
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PHM_PlatformCaps_DisableDCODT, /* indicates if DC ODT apply or not */
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PHM_PlatformCaps_DynamicACTiming, /* if the SMC dynamically re-programs MC SEQ register values */
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PHM_PlatformCaps_EnableThermalIntByGPIO, /* enable throttle control through GPIO */
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PHM_PlatformCaps_BootStateOnAlert, /* Go to boot state on alerts, e.g. on an AC->DC transition. */
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PHM_PlatformCaps_DontWaitForVBlankOnAlert, /* Do NOT wait for VBLANK during an alert (e.g. AC->DC transition). */
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PHM_PlatformCaps_Force3DClockSupport, /* indicates if the platform supports force 3D clock. */
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PHM_PlatformCaps_MicrocodeFanControl, /* Fan is controlled by the SMC microcode. */
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PHM_PlatformCaps_AdjustUVDPriorityForSP,
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PHM_PlatformCaps_DisableLightSleep, /* Light sleep for evergreen family. */
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PHM_PlatformCaps_DisableMCLS, /* MC Light sleep */
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PHM_PlatformCaps_RegulatorHot, /* Enable throttling on 'regulator hot' events. */
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PHM_PlatformCaps_BACO, /* Support Bus Alive Chip Off mode */
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PHM_PlatformCaps_DisableDPM, /* Disable DPM, supported from Llano */
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PHM_PlatformCaps_DynamicM3Arbiter, /* support dynamically change m3 arbitor parameters */
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PHM_PlatformCaps_SclkDeepSleep, /* support sclk deep sleep */
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PHM_PlatformCaps_DynamicPatchPowerState, /* this ASIC supports to patch power state dynamically */
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PHM_PlatformCaps_ThermalAutoThrottling, /* enabling auto thermal throttling, */
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PHM_PlatformCaps_SumoThermalPolicy, /* A thermal policy specific for Sumo */
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PHM_PlatformCaps_PCIEPerformanceRequest, /* support to change RC voltage */
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PHM_PlatformCaps_BLControlledByGPU, /* support varibright */
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PHM_PlatformCaps_PowerContainment, /* support DPM2 power containment (AKA TDP clamping) */
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PHM_PlatformCaps_SQRamping, /* support DPM2 SQ power throttle */
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PHM_PlatformCaps_CAC, /* support Capacitance * Activity power estimation */
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PHM_PlatformCaps_NIChipsets, /* Northern Island and beyond chipsets */
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PHM_PlatformCaps_TrinityChipsets, /* Trinity chipset */
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PHM_PlatformCaps_EvergreenChipsets, /* Evergreen family chipset */
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PHM_PlatformCaps_PowerControl, /* Cayman and beyond chipsets */
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PHM_PlatformCaps_DisableLSClockGating, /* to disable Light Sleep control for HDP memories */
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PHM_PlatformCaps_BoostState, /* this ASIC supports boost state */
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PHM_PlatformCaps_UserMaxClockForMultiDisplays, /* indicates if max memory clock is used for all status when multiple displays are connected */
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PHM_PlatformCaps_RegWriteDelay, /* indicates if back to back reg write delay is required */
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PHM_PlatformCaps_NonABMSupportInPPLib, /* ABM is not supported in PPLIB, (moved from PPLIB to DAL) */
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PHM_PlatformCaps_GFXDynamicMGPowerGating, /* Enable Dynamic MG PowerGating on Trinity */
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PHM_PlatformCaps_DisableSMUUVDHandshake, /* Disable SMU UVD Handshake */
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PHM_PlatformCaps_DTE, /* Support Digital Temperature Estimation */
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PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE, /* This is for the feature requested by David B., and Tonny W.*/
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PHM_PlatformCaps_UVDPowerGating, /* enable UVD power gating, supported from Llano */
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PHM_PlatformCaps_UVDDynamicPowerGating, /* enable UVD Dynamic power gating, supported from UVD5 */
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PHM_PlatformCaps_VCEPowerGating, /* Enable VCE power gating, supported for TN and later ASICs */
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PHM_PlatformCaps_SamuPowerGating, /* Enable SAMU power gating, supported for KV and later ASICs */
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PHM_PlatformCaps_UVDDPM, /* UVD clock DPM */
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PHM_PlatformCaps_VCEDPM, /* VCE clock DPM */
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PHM_PlatformCaps_SamuDPM, /* SAMU clock DPM */
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PHM_PlatformCaps_AcpDPM, /* ACP clock DPM */
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PHM_PlatformCaps_SclkDeepSleepAboveLow, /* Enable SCLK Deep Sleep on all DPM states */
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PHM_PlatformCaps_DynamicUVDState, /* Dynamic UVD State */
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PHM_PlatformCaps_WantSAMClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */
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PHM_PlatformCaps_WantUVDClkWithDummyBackEnd, /* Set UVD Clk With Dummy Back End */
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PHM_PlatformCaps_WantVCEClkWithDummyBackEnd, /* Set VCE Clk With Dummy Back End */
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PHM_PlatformCaps_WantACPClkWithDummyBackEnd, /* Set SAM Clk With Dummy Back End */
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PHM_PlatformCaps_OD6inACSupport, /* indicates that the ASIC/back end supports OD6 */
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PHM_PlatformCaps_OD6inDCSupport, /* indicates that the ASIC/back end supports OD6 in DC */
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PHM_PlatformCaps_EnablePlatformPowerManagement, /* indicates that Platform Power Management feature is supported */
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PHM_PlatformCaps_SurpriseRemoval, /* indicates that surprise removal feature is requested */
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PHM_PlatformCaps_NewCACVoltage, /* indicates new CAC voltage table support */
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PHM_PlatformCaps_DiDtSupport, /* for dI/dT feature */
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PHM_PlatformCaps_DBRamping, /* for dI/dT feature */
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PHM_PlatformCaps_TDRamping, /* for dI/dT feature */
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PHM_PlatformCaps_TCPRamping, /* for dI/dT feature */
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PHM_PlatformCaps_DBRRamping, /* for dI/dT feature */
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PHM_PlatformCaps_DiDtEDCEnable, /* for dI/dT feature */
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PHM_PlatformCaps_GCEDC, /* for dI/dT feature */
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PHM_PlatformCaps_PSM, /* for dI/dT feature */
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PHM_PlatformCaps_EnableSMU7ThermalManagement, /* SMC will manage thermal events */
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PHM_PlatformCaps_FPS, /* FPS support */
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PHM_PlatformCaps_ACP, /* ACP support */
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PHM_PlatformCaps_SclkThrottleLowNotification, /* SCLK Throttle Low Notification */
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PHM_PlatformCaps_XDMAEnabled, /* XDMA engine is enabled */
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PHM_PlatformCaps_UseDummyBackEnd, /* use dummy back end */
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PHM_PlatformCaps_EnableDFSBypass, /* Enable DFS bypass */
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PHM_PlatformCaps_VddNBDirectRequest,
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PHM_PlatformCaps_PauseMMSessions,
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PHM_PlatformCaps_UnTabledHardwareInterface, /* Tableless/direct call hardware interface for CI and newer ASICs */
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PHM_PlatformCaps_SMU7, /* indicates that vpuRecoveryBegin without SMU shutdown */
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PHM_PlatformCaps_RevertGPIO5Polarity, /* indicates revert GPIO5 plarity table support */
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PHM_PlatformCaps_Thermal2GPIO17, /* indicates thermal2GPIO17 table support */
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PHM_PlatformCaps_ThermalOutGPIO, /* indicates ThermalOutGPIO support, pin number is assigned by VBIOS */
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PHM_PlatformCaps_DisableMclkSwitchingForFrameLock, /* Disable memory clock switch during Framelock */
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PHM_PlatformCaps_ForceMclkHigh, /* Disable memory clock switching by forcing memory clock high */
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PHM_PlatformCaps_VRHotGPIOConfigurable, /* indicates VR_HOT GPIO configurable */
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PHM_PlatformCaps_TempInversion, /* enable Temp Inversion feature */
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PHM_PlatformCaps_IOIC3,
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PHM_PlatformCaps_ConnectedStandby,
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PHM_PlatformCaps_EVV,
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PHM_PlatformCaps_EnableLongIdleBACOSupport,
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PHM_PlatformCaps_CombinePCCWithThermalSignal,
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PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
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PHM_PlatformCaps_StablePState,
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PHM_PlatformCaps_OD6PlusinACSupport,
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PHM_PlatformCaps_OD6PlusinDCSupport,
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PHM_PlatformCaps_ODThermalLimitUnlock,
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PHM_PlatformCaps_ReducePowerLimit,
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PHM_PlatformCaps_ODFuzzyFanControlSupport,
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PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
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PHM_PlatformCaps_ControlVDDGFX,
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PHM_PlatformCaps_BBBSupported,
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PHM_PlatformCaps_DisableVoltageIsland,
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PHM_PlatformCaps_FanSpeedInTableIsRPM,
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PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
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PHM_PlatformCaps_IcelandULPSSWWorkAround,
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PHM_PlatformCaps_FPSEnhancement,
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PHM_PlatformCaps_LoadPostProductionFirmware,
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PHM_PlatformCaps_VpuRecoveryInProgress,
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PHM_PlatformCaps_Falcon_QuickTransition,
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PHM_PlatformCaps_AVFS,
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PHM_PlatformCaps_ClockStretcher,
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PHM_PlatformCaps_TablelessHardwareInterface,
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PHM_PlatformCaps_EnableDriverEVV,
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PHM_PlatformCaps_SPLLShutdownSupport,
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PHM_PlatformCaps_VirtualBatteryState,
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PHM_PlatformCaps_IgnoreForceHighClockRequestsInAPUs,
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PHM_PlatformCaps_DisableMclkSwitchForVR,
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PHM_PlatformCaps_SMU8,
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PHM_PlatformCaps_VRHotPolarityHigh,
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PHM_PlatformCaps_IPS_UlpsExclusive,
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PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme,
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PHM_PlatformCaps_GeminiAsymmetricPower,
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PHM_PlatformCaps_OCLPowerOptimization,
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PHM_PlatformCaps_MaxPCIEBandWidth,
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PHM_PlatformCaps_PerfPerWattOptimizationSupport,
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PHM_PlatformCaps_UVDClientMCTuning,
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PHM_PlatformCaps_ODNinACSupport,
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PHM_PlatformCaps_ODNinDCSupport,
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PHM_PlatformCaps_UMDPState,
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PHM_PlatformCaps_AutoWattmanSupport,
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PHM_PlatformCaps_AutoWattmanEnable_CCCState,
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PHM_PlatformCaps_FreeSyncActive,
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PHM_PlatformCaps_EnableShadowPstate,
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PHM_PlatformCaps_customThermalManagement,
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PHM_PlatformCaps_staticFanControl,
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PHM_PlatformCaps_Virtual_System,
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PHM_PlatformCaps_LowestUclkReservedForUlv,
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PHM_PlatformCaps_EnableBoostState,
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PHM_PlatformCaps_AVFSSupport,
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PHM_PlatformCaps_ThermalPolicyDelay,
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PHM_PlatformCaps_CustomFanControlSupport,
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PHM_PlatformCaps_BAMACO,
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PHM_PlatformCaps_Max
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};
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#define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)
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/* Number of uint32_t entries used by CAPS table */
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#define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
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((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))
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struct pp_hw_descriptor {
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uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
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};
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enum PHM_PerformanceLevelDesignation {
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PHM_PerformanceLevelDesignation_Activity,
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PHM_PerformanceLevelDesignation_PowerContainment
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};
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typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation;
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struct PHM_PerformanceLevel {
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uint32_t coreClock;
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uint32_t memory_clock;
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uint32_t vddc;
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uint32_t vddci;
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uint32_t nonLocalMemoryFreq;
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uint32_t nonLocalMemoryWidth;
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};
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typedef struct PHM_PerformanceLevel PHM_PerformanceLevel;
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/* Function for setting a platform cap */
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static inline void phm_cap_set(uint32_t *caps,
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enum phm_platform_caps c)
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{
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caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL <<
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(c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
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}
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static inline void phm_cap_unset(uint32_t *caps,
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enum phm_platform_caps c)
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{
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caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
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}
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static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
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{
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return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
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(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
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}
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#define PP_CAP(c) phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (c))
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#define PP_PCIEGenInvalid 0xffff
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enum PP_PCIEGen {
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PP_PCIEGen1 = 0, /* PCIE 1.0 - Transfer rate of 2.5 GT/s */
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PP_PCIEGen2, /*PCIE 2.0 - Transfer rate of 5.0 GT/s */
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PP_PCIEGen3 /*PCIE 3.0 - Transfer rate of 8.0 GT/s */
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};
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typedef enum PP_PCIEGen PP_PCIEGen;
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#define PP_Min_PCIEGen PP_PCIEGen1
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#define PP_Max_PCIEGen PP_PCIEGen3
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#define PP_Min_PCIELane 1
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#define PP_Max_PCIELane 16
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enum phm_clock_Type {
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PHM_DispClock = 1,
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PHM_SClock,
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PHM_MemClock
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};
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#define MAX_NUM_CLOCKS 16
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struct PP_Clocks {
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uint32_t engineClock;
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uint32_t memoryClock;
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uint32_t BusBandwidth;
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uint32_t engineClockInSR;
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uint32_t dcefClock;
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uint32_t dcefClockInSR;
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};
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struct pp_clock_info {
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uint32_t min_mem_clk;
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uint32_t max_mem_clk;
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uint32_t min_eng_clk;
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uint32_t max_eng_clk;
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uint32_t min_bus_bandwidth;
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uint32_t max_bus_bandwidth;
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};
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struct phm_platform_descriptor {
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uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
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uint32_t vbiosInterruptId;
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struct PP_Clocks overdriveLimit;
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struct PP_Clocks clockStep;
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uint32_t hardwareActivityPerformanceLevels;
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uint32_t minimumClocksReductionPercentage;
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uint32_t minOverdriveVDDC;
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uint32_t maxOverdriveVDDC;
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uint32_t overdriveVDDCStep;
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uint32_t hardwarePerformanceLevels;
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uint16_t powerBudget;
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uint32_t TDPLimit;
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uint32_t nearTDPLimit;
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uint32_t nearTDPLimitAdjusted;
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uint32_t SQRampingThreshold;
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uint32_t CACLeakage;
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uint16_t TDPODLimit;
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uint32_t TDPAdjustment;
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bool TDPAdjustmentPolarity;
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uint16_t LoadLineSlope;
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uint32_t VidMinLimit;
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uint32_t VidMaxLimit;
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uint32_t VidStep;
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uint32_t VidAdjustment;
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bool VidAdjustmentPolarity;
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};
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struct phm_clocks {
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uint32_t num_of_entries;
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uint32_t clock[MAX_NUM_CLOCKS];
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};
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#define DPMTABLE_OD_UPDATE_SCLK 0x00000001
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#define DPMTABLE_OD_UPDATE_MCLK 0x00000002
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#define DPMTABLE_UPDATE_SCLK 0x00000004
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#define DPMTABLE_UPDATE_MCLK 0x00000008
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#define DPMTABLE_OD_UPDATE_VDDC 0x00000010
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#define DPMTABLE_UPDATE_SOCCLK 0x00000020
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struct phm_odn_performance_level {
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uint32_t clock;
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uint32_t vddc;
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bool enabled;
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};
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struct phm_odn_clock_levels {
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uint32_t size;
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uint32_t options;
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uint32_t flags;
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uint32_t num_of_pl;
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/* variable-sized array, specify by num_of_pl. */
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struct phm_odn_performance_level entries[8];
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};
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extern int phm_disable_clock_power_gatings(struct pp_hwmgr *hwmgr);
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extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
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extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
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extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
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extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
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extern int phm_disable_dynamic_state_management(struct pp_hwmgr *hwmgr);
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extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
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extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
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extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
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const struct pp_hw_power_state *pcurrent_state,
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const struct pp_hw_power_state *pnew_power_state);
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extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
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struct pp_power_state *adjusted_ps,
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const struct pp_power_state *current_ps);
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extern int phm_apply_clock_adjust_rules(struct pp_hwmgr *hwmgr);
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extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
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extern int phm_pre_display_configuration_changed(struct pp_hwmgr *hwmgr);
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extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
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extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
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extern int phm_register_irq_handlers(struct pp_hwmgr *hwmgr);
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extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr);
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extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
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extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
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extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
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const struct pp_hw_power_state *pstate1,
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const struct pp_hw_power_state *pstate2,
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bool *equal);
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extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
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const struct amd_pp_display_configuration *display_config);
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extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
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struct amd_pp_simple_clock_info *info);
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extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
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extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
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|
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extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
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PHM_PerformanceLevelDesignation designation, uint32_t index,
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PHM_PerformanceLevel *level);
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|
|
|
extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
|
|
struct pp_clock_info *pclock_info,
|
|
PHM_PerformanceLevelDesignation designation);
|
|
|
|
extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
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|
|
|
extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
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|
|
|
extern int phm_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
|
|
enum amd_pp_clock_type type,
|
|
struct pp_clock_levels_with_latency *clocks);
|
|
extern int phm_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
|
|
enum amd_pp_clock_type type,
|
|
struct pp_clock_levels_with_voltage *clocks);
|
|
extern int phm_set_watermarks_for_clocks_ranges(struct pp_hwmgr *hwmgr,
|
|
void *clock_ranges);
|
|
extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
|
|
struct pp_display_clock_request *clock);
|
|
|
|
extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
|
|
extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);
|
|
#endif /* _HARDWARE_MANAGER_H_ */
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