471 lines
14 KiB
C
471 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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#include <drm/drmP.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/soc/mediatek/mtk-cmdq.h>
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#include "mtk_drm_crtc.h"
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#include "mtk_drm_ddp_comp.h"
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#include "mtk_drm_drv.h"
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#include "mtk_log.h"
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#include "mtk_dump.h"
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#define DMDP_AAL_EN 0x0000
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#define DMDP_AAL_CFG 0x0020
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#define DMDP_AAL_CFG_MAIN 0x0200
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#define DMDP_AAL_SIZE 0x0030
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#define DMDP_AAL_OUTPUT_SIZE 0x0034
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#define DMDP_AAL_SHADOW_CTRL 0x0F0
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#define AAL_BYPASS_SHADOW BIT(0)
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#define AAL_READ_WRK_REG BIT(2)
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#define DMDP_AAL_DRE_BITPLUS_00 0x048C
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#define DMDP_AAL_DRE_BILATERAL 0x053C
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#define DMDP_AAL_Y2R_00 0x04BC
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#define DMDP_AAL_R2Y_00 0x04D4
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#define AAL_EN BIT(0)
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struct mtk_dmdp_aal_data {
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bool support_shadow;
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u32 block_info_00_mask;
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};
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struct mtk_dmdp_aal {
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struct mtk_ddp_comp ddp_comp;
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struct drm_crtc *crtc;
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const struct mtk_dmdp_aal_data *data;
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};
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static inline struct mtk_dmdp_aal *comp_to_dmdp_aal(struct mtk_ddp_comp *comp)
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{
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return container_of(comp, struct mtk_dmdp_aal, ddp_comp);
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}
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static void mtk_aal_write_mask(void __iomem *address, u32 data, u32 mask)
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{
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u32 value = data;
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if (mask != ~0) {
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value = readl(address);
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value &= ~mask;
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data &= mask;
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value |= data;
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}
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writel(value, address);
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}
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static void mtk_dmdp_aal_start(struct mtk_ddp_comp *comp,
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struct cmdq_pkt *handle)
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{
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DDPINFO("%s\n", __func__);
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cmdq_pkt_write(handle, comp->cmdq_base, comp->regs_pa + DMDP_AAL_EN,
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AAL_EN, ~0);
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}
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static void mtk_dmdp_aal_stop(struct mtk_ddp_comp *comp,
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struct cmdq_pkt *handle)
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{
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DDPINFO("%s\n", __func__);
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cmdq_pkt_write(handle, comp->cmdq_base, comp->regs_pa + DMDP_AAL_EN,
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0x0, ~0);
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}
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static void mtk_dmdp_aal_bypass(struct mtk_ddp_comp *comp, int bypass,
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struct cmdq_pkt *handle)
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{
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DDPINFO("%s : bypass = %d\n", __func__, bypass);
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cmdq_pkt_write(handle, comp->cmdq_base, comp->regs_pa + DMDP_AAL_EN,
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AAL_EN, ~0);
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cmdq_pkt_write(handle, comp->cmdq_base, comp->regs_pa + DMDP_AAL_CFG,
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0x400003, ~0);
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cmdq_pkt_write(handle, comp->cmdq_base,
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comp->regs_pa + DMDP_AAL_CFG_MAIN, 0, ~0);
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cmdq_pkt_write(handle, comp->cmdq_base,
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comp->regs_pa + DMDP_AAL_DRE_BILATERAL, 0, ~0);
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}
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static void mtk_dmdp_aal_config(struct mtk_ddp_comp *comp,
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struct mtk_ddp_config *cfg, struct cmdq_pkt *handle)
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{
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unsigned int val = 0;
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int width = cfg->w, height = cfg->h;
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if (comp->mtk_crtc->is_dual_pipe)
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width = cfg->w / 2;
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else
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width = cfg->w;
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val = (width << 16) | height;
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DDPINFO("%s: 0x%08x\n", __func__, val);
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cmdq_pkt_write(handle, comp->cmdq_base, comp->regs_pa + DMDP_AAL_CFG,
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0, 1);
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cmdq_pkt_write(handle, comp->cmdq_base, comp->regs_pa + DMDP_AAL_SIZE,
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val, ~0);
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cmdq_pkt_write(handle, comp->cmdq_base,
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comp->regs_pa + DMDP_AAL_OUTPUT_SIZE, val, ~0);
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cmdq_pkt_write(handle, comp->cmdq_base,
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comp->regs_pa + DMDP_AAL_DRE_BILATERAL, 0, ~0);
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cmdq_pkt_write(handle, comp->cmdq_base,
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comp->regs_pa + DMDP_AAL_DRE_BITPLUS_00, 0, ~0);
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cmdq_pkt_write(handle, comp->cmdq_base,
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comp->regs_pa + DMDP_AAL_Y2R_00, 0, ~0);
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cmdq_pkt_write(handle, comp->cmdq_base,
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comp->regs_pa + DMDP_AAL_R2Y_00, 0, ~0);
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}
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void mtk_dmdp_aal_first_cfg(struct mtk_ddp_comp *comp,
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struct mtk_ddp_config *cfg, struct cmdq_pkt *handle)
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{
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DDPINFO("%s\n", __func__);
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cmdq_pkt_write(handle, comp->cmdq_base, comp->regs_pa + DMDP_AAL_CFG,
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0x00400022, ~0);
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mtk_dmdp_aal_config(comp, cfg, handle);
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mtk_dmdp_aal_start(comp, handle);
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}
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static atomic_t g_aal_initialed = ATOMIC_INIT(0);
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struct aal_backup { /* structure for backup AAL register value */
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unsigned int DRE_MAPPING;
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unsigned int DRE_BLOCK_INFO_00;
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unsigned int DRE_BLOCK_INFO_01;
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unsigned int DRE_BLOCK_INFO_02;
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unsigned int DRE_BLOCK_INFO_04;
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unsigned int DRE_BLOCK_INFO_05;
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unsigned int DRE_BLOCK_INFO_06;
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unsigned int DRE_BLOCK_INFO_07;
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unsigned int DRE_CHROMA_HIST_00;
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unsigned int DRE_CHROMA_HIST_01;
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unsigned int DRE_ALPHA_BLEND_00;
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unsigned int SRAM_CFG;
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unsigned int DUAL_PIPE_INFO_00;
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unsigned int DUAL_PIPE_INFO_01;
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unsigned int TILE_00;
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unsigned int DRE0_TILE_00;
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unsigned int DRE1_TILE_00;
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unsigned int TILE_01;
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unsigned int TILE_02;
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};
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static struct aal_backup g_aal_backup;
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#define DMDP_AAL_SRAM_CFG (0x0c4)
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#define DMDP_AAL_TILE_02 (0x0F4)
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#define DMDP_AAL_DRE_BLOCK_INFO_07 (0x0f8)
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#define DMDP_AAL_DRE_MAPPING_00 (0x3b4)
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#define DMDP_AAL_DRE_BLOCK_INFO_00 (0x468)
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#define DMDP_AAL_DRE_BLOCK_INFO_01 (0x46c)
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#define DMDP_AAL_DRE_BLOCK_INFO_02 (0x470)
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#define DMDP_AAL_DRE_BLOCK_INFO_03 (0x474)
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#define DMDP_AAL_DRE_BLOCK_INFO_04 (0x478)
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#define DMDP_AAL_DRE_CHROMA_HIST_00 (0x480)
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#define DMDP_AAL_DRE_CHROMA_HIST_01 (0x484)
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#define DMDP_AAL_DRE_ALPHA_BLEND_00 (0x488)
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#define DMDP_AAL_DRE_BLOCK_INFO_05 (0x4b4)
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#define DMDP_AAL_DRE_BLOCK_INFO_06 (0x4b8)
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#define DMDP_AAL_DUAL_PIPE_INFO_00 (0x4d0)
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#define DMDP_AAL_DUAL_PIPE_INFO_01 (0x4d4)
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#define DMDP_AAL_TILE_00 (0x4EC)
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#define DMDP_AAL_TILE_01 (0x4F0)
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static void ddp_aal_dre3_backup(struct mtk_ddp_comp *comp)
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{
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g_aal_backup.DRE_BLOCK_INFO_00 =
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readl(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_00);
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g_aal_backup.DRE_BLOCK_INFO_01 =
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readl(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_01);
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g_aal_backup.DRE_BLOCK_INFO_02 =
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readl(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_02);
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g_aal_backup.DRE_BLOCK_INFO_04 =
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readl(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_04);
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g_aal_backup.DRE_CHROMA_HIST_00 =
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readl(comp->regs + DMDP_AAL_DRE_CHROMA_HIST_00);
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g_aal_backup.DRE_CHROMA_HIST_01 =
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readl(comp->regs + DMDP_AAL_DRE_CHROMA_HIST_01);
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g_aal_backup.DRE_ALPHA_BLEND_00 =
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readl(comp->regs + DMDP_AAL_DRE_ALPHA_BLEND_00);
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g_aal_backup.DRE_BLOCK_INFO_05 =
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readl(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_05);
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g_aal_backup.DRE_BLOCK_INFO_06 =
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readl(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_06);
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g_aal_backup.DRE_BLOCK_INFO_07 =
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readl(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_07);
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g_aal_backup.SRAM_CFG =
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readl(comp->regs + DMDP_AAL_SRAM_CFG);
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g_aal_backup.DUAL_PIPE_INFO_00 =
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readl(comp->regs + DMDP_AAL_DUAL_PIPE_INFO_00);
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g_aal_backup.DUAL_PIPE_INFO_01 =
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readl(comp->regs + DMDP_AAL_DUAL_PIPE_INFO_01);
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g_aal_backup.TILE_01 =
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readl(comp->regs + DMDP_AAL_TILE_01);
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g_aal_backup.TILE_02 =
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readl(comp->regs + DMDP_AAL_TILE_02);
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if (comp->mtk_crtc->is_dual_pipe) {
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if (comp->id == DDP_COMPONENT_DMDP_AAL0)
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g_aal_backup.DRE0_TILE_00 =
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readl(comp->regs + DMDP_AAL_TILE_00);
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else if (comp->id == DDP_COMPONENT_DMDP_AAL1)
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g_aal_backup.DRE1_TILE_00 =
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readl(comp->regs + DMDP_AAL_TILE_00);
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} else
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g_aal_backup.TILE_00 =
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readl(comp->regs + DMDP_AAL_TILE_00);
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}
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static void ddp_aal_dre_backup(struct mtk_ddp_comp *comp)
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{
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g_aal_backup.DRE_MAPPING =
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readl(comp->regs + DMDP_AAL_DRE_MAPPING_00);
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}
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static void mtk_dmdp_aal_backup(struct mtk_ddp_comp *comp)
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{
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DDPINFO("%s\n", __func__);
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ddp_aal_dre_backup(comp);
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ddp_aal_dre3_backup(comp);
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atomic_set(&g_aal_initialed, 1);
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}
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static void ddp_aal_dre3_restore(struct mtk_ddp_comp *comp)
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{
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struct mtk_dmdp_aal *dmdp_aal = comp_to_dmdp_aal(comp);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_00,
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g_aal_backup.DRE_BLOCK_INFO_00 &
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(dmdp_aal->data->block_info_00_mask),
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dmdp_aal->data->block_info_00_mask);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_01,
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g_aal_backup.DRE_BLOCK_INFO_01, ~0);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_02,
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g_aal_backup.DRE_BLOCK_INFO_02, ~0);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_04,
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g_aal_backup.DRE_BLOCK_INFO_04 & (0x3FF << 13), 0x3FF << 13);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_DRE_CHROMA_HIST_00,
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g_aal_backup.DRE_CHROMA_HIST_00, ~0);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_DRE_CHROMA_HIST_01,
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g_aal_backup.DRE_CHROMA_HIST_01 & 0x1FFFFFFF, 0x1FFFFFFF);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_DRE_ALPHA_BLEND_00,
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g_aal_backup.DRE_ALPHA_BLEND_00, ~0);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_05,
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g_aal_backup.DRE_BLOCK_INFO_05, ~0);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_06,
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g_aal_backup.DRE_BLOCK_INFO_06, ~0);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_DRE_BLOCK_INFO_07,
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g_aal_backup.DRE_BLOCK_INFO_07, ~0);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_SRAM_CFG,
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g_aal_backup.SRAM_CFG, 0x1);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_DUAL_PIPE_INFO_00,
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g_aal_backup.DUAL_PIPE_INFO_00, ~0);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_DUAL_PIPE_INFO_01,
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g_aal_backup.DUAL_PIPE_INFO_01, ~0);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_TILE_01,
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g_aal_backup.TILE_01, ~0);
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mtk_aal_write_mask(comp->regs + DMDP_AAL_TILE_02,
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g_aal_backup.TILE_02, ~0);
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if (comp->mtk_crtc->is_dual_pipe) {
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if (comp->id == DDP_COMPONENT_DMDP_AAL0)
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mtk_aal_write_mask(comp->regs + DMDP_AAL_TILE_00,
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g_aal_backup.DRE0_TILE_00, ~0);
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else if (comp->id == DDP_COMPONENT_DMDP_AAL1)
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mtk_aal_write_mask(comp->regs + DMDP_AAL_TILE_00,
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g_aal_backup.DRE1_TILE_00, ~0);
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} else
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mtk_aal_write_mask(comp->regs + DMDP_AAL_TILE_00,
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g_aal_backup.TILE_00, ~0);
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}
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static void ddp_aal_dre_restore(struct mtk_ddp_comp *comp)
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{
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writel(g_aal_backup.DRE_MAPPING,
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comp->regs + DMDP_AAL_DRE_MAPPING_00);
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}
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static void mtk_dmdp_aal_restore(struct mtk_ddp_comp *comp)
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{
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if (atomic_read(&g_aal_initialed) != 1)
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return;
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DDPINFO("%s\n", __func__);
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ddp_aal_dre_restore(comp);
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ddp_aal_dre3_restore(comp);
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}
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static void mtk_dmdp_aal_prepare(struct mtk_ddp_comp *comp)
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{
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#if defined(CONFIG_DRM_MTK_SHADOW_REGISTER_SUPPORT)
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struct mtk_dmdp_aal *dmdp_aal = comp_to_dmdp_aal(comp);
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#endif
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pr_notice("%s\n", __func__);
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mtk_ddp_comp_clk_prepare(comp);
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#if defined(CONFIG_DRM_MTK_SHADOW_REGISTER_SUPPORT)
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if (dmdp_aal->data->support_shadow) {
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/* Enable shadow register and read shadow register */
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mtk_ddp_write_mask_cpu(comp, 0x0,
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DMDP_AAL_SHADOW_CTRL, AAL_BYPASS_SHADOW);
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} else {
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/* Bypass shadow register and read shadow register */
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mtk_ddp_write_mask_cpu(comp, AAL_BYPASS_SHADOW,
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DMDP_AAL_SHADOW_CTRL, AAL_BYPASS_SHADOW);
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}
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#else
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#if defined(CONFIG_MACH_MT6873)
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/* Bypass shadow register and read shadow register */
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mtk_ddp_write_mask_cpu(comp, AAL_BYPASS_SHADOW,
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DMDP_AAL_SHADOW_CTRL, AAL_BYPASS_SHADOW);
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#endif
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#endif
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mtk_dmdp_aal_restore(comp);
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}
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static void mtk_dmdp_aal_unprepare(struct mtk_ddp_comp *comp)
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{
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pr_notice("%s\n", __func__);
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mtk_dmdp_aal_backup(comp);
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mtk_ddp_comp_clk_unprepare(comp);
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}
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static const struct mtk_ddp_comp_funcs mtk_dmdp_aal_funcs = {
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.config = mtk_dmdp_aal_config,
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.first_cfg = mtk_dmdp_aal_first_cfg,
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.start = mtk_dmdp_aal_start,
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.stop = mtk_dmdp_aal_stop,
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.bypass = mtk_dmdp_aal_bypass,
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.prepare = mtk_dmdp_aal_prepare,
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.unprepare = mtk_dmdp_aal_unprepare,
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};
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static int mtk_dmdp_aal_bind(struct device *dev, struct device *master,
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void *data)
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{
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struct mtk_dmdp_aal *priv = dev_get_drvdata(dev);
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struct drm_device *drm_dev = data;
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int ret;
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DDPINFO("%s\n", __func__);
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ret = mtk_ddp_comp_register(drm_dev, &priv->ddp_comp);
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if (ret < 0) {
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DDPMSG("Failed to register component %s: %d\n",
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dev->of_node->full_name, ret);
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return ret;
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}
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return 0;
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}
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static void mtk_dmdp_aal_unbind(struct device *dev, struct device *master,
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void *data)
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{
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struct mtk_dmdp_aal *priv = dev_get_drvdata(dev);
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struct drm_device *drm_dev = data;
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mtk_ddp_comp_unregister(drm_dev, &priv->ddp_comp);
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}
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static const struct component_ops mtk_dmdp_aal_component_ops = {
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.bind = mtk_dmdp_aal_bind, .unbind = mtk_dmdp_aal_unbind,
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};
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void mtk_dmdp_aal_dump(struct mtk_ddp_comp *comp)
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{
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void __iomem *baddr = comp->regs;
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DDPDUMP("== %s REGS ==\n", mtk_dump_comp_str(comp));
|
|
mtk_cust_dump_reg(baddr, 0x0, 0x20, 0x30, 0x4D8);
|
|
mtk_cust_dump_reg(baddr, 0x200, 0xf4, 0xf8, 0x468);
|
|
mtk_cust_dump_reg(baddr, 0x46c, 0x470, 0x474, 0x478);
|
|
mtk_cust_dump_reg(baddr, 0x4ec, 0x4f0, 0x528, 0x52c);
|
|
}
|
|
|
|
static int mtk_dmdp_aal_probe(struct platform_device *pdev)
|
|
{
|
|
struct device *dev = &pdev->dev;
|
|
struct mtk_dmdp_aal *priv;
|
|
enum mtk_ddp_comp_id comp_id;
|
|
int ret;
|
|
|
|
DDPMSG("%s\n", __func__);
|
|
|
|
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
if (priv == NULL)
|
|
return -ENOMEM;
|
|
|
|
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DMDP_AAL);
|
|
if ((int)comp_id < 0) {
|
|
DDPMSG("Failed to identify by alias: %d\n", comp_id);
|
|
return comp_id;
|
|
}
|
|
|
|
ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
|
|
&mtk_dmdp_aal_funcs);
|
|
if (ret != 0) {
|
|
DDPMSG("Failed to initialize component: %d\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
priv->data = of_device_get_match_data(dev);
|
|
platform_set_drvdata(pdev, priv);
|
|
|
|
pm_runtime_enable(dev);
|
|
|
|
ret = component_add(dev, &mtk_dmdp_aal_component_ops);
|
|
if (ret != 0) {
|
|
DDPMSG("Failed to add component: %d\n", ret);
|
|
pm_runtime_disable(dev);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mtk_dmdp_aal_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &mtk_dmdp_aal_component_ops);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
return 0;
|
|
}
|
|
|
|
static const struct mtk_dmdp_aal_data mt6885_dmdp_aal_driver_data = {
|
|
.support_shadow = false,
|
|
.block_info_00_mask = 0x3FFFFFF,
|
|
};
|
|
|
|
static const struct mtk_dmdp_aal_data mt6873_dmdp_aal_driver_data = {
|
|
.support_shadow = false,
|
|
.block_info_00_mask = 0x3FFF3FFF,
|
|
};
|
|
|
|
static const struct of_device_id mtk_dmdp_aal_driver_dt_match[] = {
|
|
{ .compatible = "mediatek,mt6885-dmdp-aal",
|
|
.data = &mt6885_dmdp_aal_driver_data},
|
|
{ .compatible = "mediatek,mt6873-dmdp-aal",
|
|
.data = &mt6873_dmdp_aal_driver_data},
|
|
{},
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, mtk_dmdp_aal_driver_dt_match);
|
|
|
|
struct platform_driver mtk_dmdp_aal_driver = {
|
|
.probe = mtk_dmdp_aal_probe,
|
|
.remove = mtk_dmdp_aal_remove,
|
|
.driver = {
|
|
|
|
.name = "mediatek-dmdp-aal",
|
|
.owner = THIS_MODULE,
|
|
.of_match_table = mtk_dmdp_aal_driver_dt_match,
|
|
},
|
|
};
|