86 lines
2.1 KiB
C
86 lines
2.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2020 MediaTek Inc.
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*/
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#ifndef __CIRQ_SYS_H__
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#define __CIRQ_SYS_H__
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#define MT_EDGE_SENSITIVE 0
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#define MT_LEVEL_SENSITIVE 1
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/*
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* Define hardware register
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*/
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#define CIRQ_STA_BASE (SYS_CIRQ_BASE + 0x000)
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#define CIRQ_ACK_BASE (SYS_CIRQ_BASE + 0x040)
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#define CIRQ_MASK_BASE (SYS_CIRQ_BASE + 0x080)
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#define CIRQ_MASK_SET_BASE (SYS_CIRQ_BASE + 0x0C0)
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#define CIRQ_MASK_CLR_BASE (SYS_CIRQ_BASE + 0x100)
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#define CIRQ_SENS_BASE (SYS_CIRQ_BASE + 0x140)
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#define CIRQ_SENS_SET_BASE (SYS_CIRQ_BASE + 0x180)
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#define CIRQ_SENS_CLR_BASE (SYS_CIRQ_BASE + 0x1C0)
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#define CIRQ_POL_BASE (SYS_CIRQ_BASE + 0x200)
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#define CIRQ_POL_SET_BASE (SYS_CIRQ_BASE + 0x240)
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#define CIRQ_POL_CLR_BASE (SYS_CIRQ_BASE + 0x280)
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#define CIRQ_CON (SYS_CIRQ_BASE + 0x300)
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/*
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* Register placement
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*/
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#define CIRQ_CON_EN_BITS (0)
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#define CIRQ_CON_EDGE_ONLY_BITS (1)
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#define CIRQ_CON_FLUSH_BITS (2)
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#define CIRQ_CON_EVENT_BITS (31)
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#define CIRQ_CON_BITS_MASK (0x7)
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/*
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* Register setting
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*/
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#define CIRQ_CON_EN (0x1)
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#define CIRQ_CON_EDGE_ONLY (0x1)
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#define CIRQ_CON_FLUSH (0x1)
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/*
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* Define constant
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*/
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#define CIRQ_CTRL_REG_NUM ((CIRQ_IRQ_NUM + 31) / 32)
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#define MT_CIRQ_POL_NEG (0)
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#define MT_CIRQ_POL_POS (1)
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/*
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* Define macro
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*/
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#define IRQ_TO_CIRQ_NUM(irq) \
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((irq) - (GIC_PRIVATE_SIGNALS + CIRQ_SPI_START))
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#define CIRQ_TO_IRQ_NUM(cirq) \
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((cirq) + (GIC_PRIVATE_SIGNALS + CIRQ_SPI_START))
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#define print_func() pr_debug("[CIRQ] in %s\n", __func__)
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/* #define __CHECK_IRQ_TYPE */
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extern void __iomem *GIC_DIST_BASE;
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extern void __iomem *GIC_CPU_BASE;
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extern void __iomem *INT_POL_CTL0;
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#ifndef GIC_PRIVATE_SIGNALS
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#define GIC_PRIVATE_SIGNALS (32)
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#endif
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/*
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* Define function prototypes.
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*/
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void mt_cirq_enable(void);
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void mt_cirq_disable(void);
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void mt_cirq_clone_gic(void);
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void mt_cirq_sw_reset(void);
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void mt_cirq_flush(void);
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int mt_cirq_test(void);
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void mt_cirq_dump_reg(void);
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void set_wakeup_sources(u32 *list, u32 num_events);
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#endif /*!__CIRQ_H__ */
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