458 lines
12 KiB
Plaintext
458 lines
12 KiB
Plaintext
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (c) 2019 MediaTek Inc.
|
|
*/
|
|
|
|
&main_pmic {
|
|
compatible = "mediatek,mt6357-pmic";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
mediatek,num-pmic-irqs = <145>;
|
|
mediatek,pmic-irqs =
|
|
<INT_VPROC_OC SP_BUCK>,
|
|
<INT_VCORE_OC SP_BUCK>,
|
|
<INT_VMODEM_OC SP_BUCK>,
|
|
<INT_VS1_OC SP_BUCK>,
|
|
<INT_VPA_OC SP_BUCK>,
|
|
<INT_VCORE_PREOC SP_BUCK>,
|
|
<INT_VFE28_OC SP_LDO>,
|
|
<INT_VXO22_OC SP_LDO>,
|
|
<INT_VRF18_OC SP_LDO>,
|
|
<INT_VRF12_OC SP_LDO>,
|
|
<INT_VEFUSE_OC SP_LDO>,
|
|
<INT_VCN33_OC SP_LDO>,
|
|
<INT_VCN28_OC SP_LDO>,
|
|
<INT_VCN18_OC SP_LDO>,
|
|
<INT_VCAMA_OC SP_LDO>,
|
|
<INT_VCAMD_OC SP_LDO>,
|
|
<INT_VCAMIO_OC SP_LDO>,
|
|
<INT_VLDO28_OC SP_LDO>,
|
|
<INT_VUSB33_OC SP_LDO>,
|
|
<INT_VAUX18_OC SP_LDO>,
|
|
<INT_VAUD28_OC SP_LDO>,
|
|
<INT_VIO28_OC SP_LDO>,
|
|
<INT_VIO18_OC SP_LDO>,
|
|
<INT_VSRAM_PROC_OC SP_LDO>,
|
|
<INT_VSRAM_OTHERS_OC SP_LDO>,
|
|
<INT_VIBR_OC SP_LDO>,
|
|
<INT_VDRAM_OC SP_LDO>,
|
|
<INT_VMC_OC SP_LDO>,
|
|
<INT_VMCH_OC SP_LDO>,
|
|
<INT_VEMC_OC SP_LDO>,
|
|
<INT_VSIM1_OC SP_LDO>,
|
|
<INT_VSIM2_OC SP_LDO>,
|
|
<INT_PWRKEY SP_PSC>,
|
|
<INT_HOMEKEY SP_PSC>,
|
|
<INT_PWRKEY_R SP_PSC>,
|
|
<INT_HOMEKEY_R SP_PSC>,
|
|
<INT_NI_LBAT_INT SP_PSC>,
|
|
<INT_CHRDET SP_PSC>,
|
|
<INT_CHRDET_EDGE SP_PSC>,
|
|
<INT_VCDT_HV_DET SP_PSC>,
|
|
<INT_WATCHDOG SP_PSC>,
|
|
<INT_VBATON_UNDET SP_PSC>,
|
|
<INT_BVALID_DET SP_PSC>,
|
|
<INT_OV SP_PSC>,
|
|
<INT_RTC SP_SCK>,
|
|
<INT_FG_BAT0_H SP_BM>,
|
|
<INT_FG_BAT0_L SP_BM>,
|
|
<INT_FG_CUR_H SP_BM>,
|
|
<INT_FG_CUR_L SP_BM>,
|
|
<INT_FG_ZCV SP_BM>,
|
|
<INT_BATON_LV SP_BM>,
|
|
<INT_BATON_HT SP_BM>,
|
|
<INT_BAT_H SP_HK>,
|
|
<INT_BAT_L SP_HK>,
|
|
<INT_AUXADC_IMP SP_HK>,
|
|
<INT_NAG_C_DLTV SP_HK>,
|
|
<INT_AUDIO SP_AUD>,
|
|
<INT_ACCDET SP_AUD>,
|
|
<INT_ACCDET_EINT0 SP_AUD>,
|
|
<INT_ACCDET_EINT1 SP_AUD>,
|
|
<INT_SPI_CMD_ALERT SP_MISC>;
|
|
interrupt-names =
|
|
"vproc_oc",
|
|
"vcore_oc",
|
|
"vmodem_oc",
|
|
"vs1_oc",
|
|
"vpa_oc",
|
|
"vcore_preoc",
|
|
"vfe28_oc",
|
|
"vxo22_oc",
|
|
"vrf18_oc",
|
|
"vrf12_oc",
|
|
"vefuse_oc",
|
|
"vcn33_oc",
|
|
"vcn28_oc",
|
|
"vcn18_oc",
|
|
"vcama_oc",
|
|
"vcamd_oc",
|
|
"vcamio_oc",
|
|
"vldo28_oc",
|
|
"vusb33_oc",
|
|
"vaux18_oc",
|
|
"vaud28_oc",
|
|
"vio28_oc",
|
|
"vio18_oc",
|
|
"vsram_proc_oc",
|
|
"vsram_others_oc",
|
|
"vibr_oc",
|
|
"vdram_oc",
|
|
"vmc_oc",
|
|
"vmch_oc",
|
|
"vemc_oc",
|
|
"vsim1_oc",
|
|
"vsim2_oc",
|
|
"pwrkey",
|
|
"homekey",
|
|
"pwrkey_r",
|
|
"homekey_r",
|
|
"ni_lbat_int",
|
|
"chrdet",
|
|
"chrdet_edge",
|
|
"vcdt_hv_det",
|
|
"watchdog",
|
|
"vbaton_undet",
|
|
"bvalid_det",
|
|
"ov",
|
|
"rtc",
|
|
"fg_bat0_h",
|
|
"fg_bat0_l",
|
|
"fg_cur_h",
|
|
"fg_cur_l",
|
|
"fg_zcv",
|
|
"baton_lv",
|
|
"baton_ht",
|
|
"bat_h",
|
|
"bat_l",
|
|
"auxadc_imp",
|
|
"nag_c_dltv",
|
|
"audio",
|
|
"accdet",
|
|
"accdet_eint0",
|
|
"accdet_eint1",
|
|
"spi_cmd_alert";
|
|
|
|
pmic: mt-pmic {
|
|
compatible = "mediatek,mt-pmic";
|
|
interrupts = <INT_PWRKEY IRQ_TYPE_LEVEL_HIGH>,
|
|
<INT_PWRKEY_R IRQ_TYPE_LEVEL_HIGH>,
|
|
<INT_HOMEKEY IRQ_TYPE_LEVEL_HIGH>,
|
|
<INT_HOMEKEY_R IRQ_TYPE_LEVEL_HIGH>,
|
|
<INT_BAT_H IRQ_TYPE_LEVEL_HIGH>,
|
|
<INT_BAT_L IRQ_TYPE_LEVEL_HIGH>,
|
|
<INT_FG_CUR_H IRQ_TYPE_LEVEL_HIGH>,
|
|
<INT_FG_CUR_L IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "pwrkey",
|
|
"pwrkey_r",
|
|
"homekey",
|
|
"homekey_r",
|
|
"bat_h",
|
|
"bat_l",
|
|
"fg_cur_h",
|
|
"fg_cur_l";
|
|
};
|
|
|
|
pmic_auxadc: mt635x-auxadc {
|
|
compatible = "mediatek,mt6357-auxadc";
|
|
#io-channel-cells = <1>;
|
|
|
|
batadc {
|
|
channel = <AUXADC_BATADC>;
|
|
resistance-ratio = <3 1>;
|
|
avg-num = <128>;
|
|
};
|
|
isense {
|
|
channel = <AUXADC_ISENSE>;
|
|
resistance-ratio = <3 1>;
|
|
avg-num = <128>;
|
|
};
|
|
vcdt {
|
|
channel = <AUXADC_VCDT>;
|
|
};
|
|
bat_temp {
|
|
channel = <AUXADC_BAT_TEMP>;
|
|
resistance-ratio = <1 1>;
|
|
};
|
|
chip_temp {
|
|
channel = <AUXADC_CHIP_TEMP>;
|
|
};
|
|
vcore_temp {
|
|
channel = <AUXADC_VCORE_TEMP>;
|
|
};
|
|
vproc_temp {
|
|
channel = <AUXADC_VPROC_TEMP>;
|
|
};
|
|
accdet {
|
|
channel = <AUXADC_ACCDET>;
|
|
};
|
|
tsx_temp {
|
|
channel = <AUXADC_TSX_TEMP>;
|
|
avg-num = <128>;
|
|
};
|
|
hpofs_cal {
|
|
channel = <AUXADC_HPOFS_CAL>;
|
|
avg-num = <256>;
|
|
};
|
|
dcxo_temp {
|
|
channel = <AUXADC_DCXO_TEMP>;
|
|
avg-num = <16>;
|
|
};
|
|
vbif {
|
|
channel = <AUXADC_VBIF>;
|
|
resistance-ratio = <1 1>;
|
|
};
|
|
};
|
|
|
|
mtk_ts_pmic: mtk_ts_pmic {
|
|
compatible = "mediatek,mtk_ts_pmic";
|
|
io-channels =
|
|
<&pmic_auxadc AUXADC_CHIP_TEMP>,
|
|
<&pmic_auxadc AUXADC_VCORE_TEMP>,
|
|
<&pmic_auxadc AUXADC_VPROC_TEMP>;
|
|
io-channel-names =
|
|
"pmic_chip_temp",
|
|
"pmic_buck1_temp",
|
|
"pmic_buck2_temp";
|
|
interconnects = <&pmic_auxadc 1>;
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
buck_regulators {
|
|
mt_pmic_vs1_buck_reg: buck_vs1 {
|
|
regulator-name = "vs1";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <2200000>;
|
|
regulator-ramp-delay = <12500>;
|
|
regulator-enable-ramp-delay = <220>;
|
|
};
|
|
mt_pmic_vmodem_buck_reg: buck_vmodem {
|
|
regulator-name = "vmodem";
|
|
regulator-min-microvolt = <500000>;
|
|
regulator-max-microvolt = <1193750>;
|
|
regulator-ramp-delay = <6250>;
|
|
regulator-enable-ramp-delay = <220>;
|
|
};
|
|
mt_pmic_vcore_buck_reg: buck_vcore {
|
|
regulator-name = "vcore";
|
|
regulator-min-microvolt = <518750>;
|
|
regulator-max-microvolt = <1312500>;
|
|
regulator-ramp-delay = <6250>;
|
|
regulator-enable-ramp-delay = <220>;
|
|
};
|
|
mt_pmic_vproc_buck_reg: buck_vproc {
|
|
regulator-name = "vproc";
|
|
regulator-min-microvolt = <518750>;
|
|
regulator-max-microvolt = <1312500>;
|
|
regulator-ramp-delay = <6250>;
|
|
regulator-enable-ramp-delay = <220>;
|
|
};
|
|
mt_pmic_vpa_buck_reg: buck_vpa {
|
|
regulator-name = "vpa";
|
|
regulator-min-microvolt = <500000>;
|
|
regulator-max-microvolt = <3650000>;
|
|
regulator-ramp-delay = <50000>;
|
|
regulator-enable-ramp-delay = <220>;
|
|
};
|
|
}; /* End of buck_regulators */
|
|
|
|
pmic_clock_buffer: pmic_clock_buffer {
|
|
compatible = "mediatek,mt6357-clkbuf";
|
|
mediatek,clkbuf-quantity = <7>;
|
|
mediatek,clkbuf-config = <2 0 0 0 0 0 0>;
|
|
mediatek,clkbuf-driving-current = <1 1 1 1 1 1 1>;
|
|
};
|
|
|
|
pmic_dcxo: pmic_dcxo {
|
|
compatible = "mediatek,mt6357-dcxo";
|
|
default-capid = <0x00>;
|
|
};
|
|
|
|
ldo_regulators {
|
|
mt_pmic_vfe28_ldo_reg: ldo_vfe28 {
|
|
regulator-name = "vfe28";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vxo22_ldo_reg: ldo_vxo22 {
|
|
regulator-name = "vxo22";
|
|
regulator-min-microvolt = <2200000>;
|
|
regulator-max-microvolt = <2400000>;
|
|
regulator-enable-ramp-delay = <110>;
|
|
};
|
|
mt_pmic_vrf18_ldo_reg: ldo_vrf18 {
|
|
regulator-name = "vrf18";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-enable-ramp-delay = <110>;
|
|
};
|
|
mt_pmic_vrf12_ldo_reg: ldo_vrf12 {
|
|
regulator-name = "vrf12";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-enable-ramp-delay = <110>;
|
|
};
|
|
mt_pmic_vefuse_ldo_reg: ldo_vefuse {
|
|
regulator-name = "vefuse";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vcn33_bt_ldo_reg: ldo_vcn33_bt {
|
|
regulator-name = "vcn33_bt";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3500000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vcn33_wifi_ldo_reg: ldo_vcn33_wifi {
|
|
regulator-name = "vcn33_wifi";
|
|
regulator-min-microvolt = <3300000>;
|
|
regulator-max-microvolt = <3500000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vcn28_ldo_reg: ldo_vcn28 {
|
|
regulator-name = "vcn28";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vcn18_ldo_reg: ldo_vcn18 {
|
|
regulator-name = "vcn18";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vcama_ldo_reg: ldo_vcama {
|
|
regulator-name = "vcama";
|
|
regulator-min-microvolt = <2500000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vcamd_ldo_reg: ldo_vcamd {
|
|
regulator-name = "vcamd";
|
|
regulator-min-microvolt = <1000000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vcamio_ldo_reg: ldo_vcamio {
|
|
regulator-name = "vcamio";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vldo28_ldo_reg: ldo_vldo28 {
|
|
regulator-name = "vldo28";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <3000000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vsram_others_ldo_reg: ldo_vsram_others {
|
|
regulator-name = "vsram_others";
|
|
regulator-min-microvolt = <518750>;
|
|
regulator-max-microvolt = <1312500>;
|
|
regulator-ramp-delay = <6250>;
|
|
regulator-enable-ramp-delay = <110>;
|
|
};
|
|
mt_pmic_vsram_proc_ldo_reg: ldo_vsram_proc {
|
|
regulator-name = "vsram_proc";
|
|
regulator-min-microvolt = <518750>;
|
|
regulator-max-microvolt = <1312500>;
|
|
regulator-ramp-delay = <6250>;
|
|
regulator-enable-ramp-delay = <110>;
|
|
};
|
|
mt_pmic_vaux18_ldo_reg: ldo_vaux18 {
|
|
regulator-name = "vaux18";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vaud28_ldo_reg: ldo_vaud28 {
|
|
regulator-name = "vaud28";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vio28_ldo_reg: ldo_vio28 {
|
|
regulator-name = "vio28";
|
|
regulator-min-microvolt = <2800000>;
|
|
regulator-max-microvolt = <2800000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vio18_ldo_reg: ldo_vio18 {
|
|
regulator-name = "vio18";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <1800000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vdram_ldo_reg: ldo_vdram {
|
|
regulator-name = "vdram";
|
|
regulator-min-microvolt = <1100000>;
|
|
regulator-max-microvolt = <1200000>;
|
|
regulator-enable-ramp-delay = <3300>;
|
|
};
|
|
mt_pmic_vmc_ldo_reg: ldo_vmc {
|
|
regulator-name = "vmc";
|
|
regulator-min-microvolt = <1800000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-enable-ramp-delay = <44>;
|
|
};
|
|
mt_pmic_vmch_ldo_reg: ldo_vmch {
|
|
regulator-name = "vmch";
|
|
regulator-min-microvolt = <2900000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-enable-ramp-delay = <44>;
|
|
};
|
|
mt_pmic_vemc_ldo_reg: ldo_vemc {
|
|
regulator-name = "vemc";
|
|
regulator-min-microvolt = <2900000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-enable-ramp-delay = <44>;
|
|
};
|
|
mt_pmic_vsim1_ldo_reg: ldo_vsim1 {
|
|
regulator-name = "vsim1";
|
|
regulator-min-microvolt = <1700000>;
|
|
regulator-max-microvolt = <3100000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vsim2_ldo_reg: ldo_vsim2 {
|
|
regulator-name = "vsim2";
|
|
regulator-min-microvolt = <1700000>;
|
|
regulator-max-microvolt = <3100000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
mt_pmic_vibr_ldo_reg: ldo_vibr {
|
|
regulator-name = "vibr";
|
|
regulator-min-microvolt = <1200000>;
|
|
regulator-max-microvolt = <3300000>;
|
|
regulator-enable-ramp-delay = <44>;
|
|
};
|
|
mt_pmic_vusb33_ldo_reg: ldo_vusb33 {
|
|
regulator-name = "vusb33";
|
|
regulator-min-microvolt = <3000000>;
|
|
regulator-max-microvolt = <3100000>;
|
|
regulator-enable-ramp-delay = <264>;
|
|
};
|
|
}; /* End of ldo_regulators */
|
|
mt6357_misc: mt6357_misc {
|
|
compatible = "mediatek,mt6357-misc";
|
|
base = <0x580>;
|
|
apply-lpsd-solution;
|
|
dcxo-switch;
|
|
};
|
|
mt6357_rtc: mt6357_rtc {
|
|
compatible = "mediatek,mt6357-rtc";
|
|
bootmode = <&chosen>;
|
|
interrupts = <INT_RTC IRQ_TYPE_NONE>;
|
|
interrupt-names = "rtc";
|
|
base = <0x580>;
|
|
apply-lpsd-solution;
|
|
};
|
|
pmic_efuse: pmic_efuse {
|
|
compatible = "mediatek,mt6357-efuse";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
};/* End of main_pmic */
|
|
|