3781 lines
89 KiB
Plaintext
3781 lines
89 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (c) 2019 MediaTek Inc.
|
|
*
|
|
*/
|
|
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/interrupt-controller/irq.h>
|
|
#include <dt-bindings/pinctrl/mt6765-pinfunc.h>
|
|
#include <dt-bindings/mmc/mt6765-msdc.h>
|
|
#include <dt-bindings/clock/mt6765-clk.h>
|
|
#include <dt-bindings/iio/mt635x-auxadc.h>
|
|
#include <dt-bindings/gce/mt6765-gce.h>
|
|
#include <dt-bindings/soc/mediatek,boot-mode.h>
|
|
#include <dt-bindings/phy/phy.h>
|
|
#include <generated/autoconf.h>
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
model = "MT6765";
|
|
compatible = "mediatek,MT6765";
|
|
interrupt-parent = <&sysirq>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
/* chosen */
|
|
chosen: chosen {
|
|
bootargs = "console=tty0 console=ttyS0,921600n1 vmalloc=400M \
|
|
slub_debug=OFZPU page_owner=on \
|
|
swiotlb=noforce androidboot.hardware=mt6765 \
|
|
maxcpus=8 loop.max_part=7 \
|
|
firmware_class.path=/vendor/firmware";
|
|
};
|
|
|
|
regulator_vibrator {
|
|
compatible = "regulator-vibrator";
|
|
min-volt = <2300000>;
|
|
max-volt = <3200000>;
|
|
min-limit = <15>;
|
|
max-limit = <15000>;
|
|
vib-supply = <&mt_pmic_vibr_ldo_reg>;
|
|
};
|
|
|
|
cluster0_opp: opp_table0 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
opp0 {
|
|
opp-hz = /bits/ 64 <900000000>;
|
|
opp-microvolt = <600000>;
|
|
};
|
|
opp1 {
|
|
opp-hz = /bits/ 64 <979000000>;
|
|
opp-microvolt = <618750>;
|
|
};
|
|
opp2 {
|
|
opp-hz = /bits/ 64 <1085000000>;
|
|
opp-microvolt = <643750>;
|
|
};
|
|
opp3 {
|
|
opp-hz = /bits/ 64 <1218000000>;
|
|
opp-microvolt = <675000>;
|
|
};
|
|
opp4 {
|
|
opp-hz = /bits/ 64 <1351000000>;
|
|
opp-microvolt = <706250>;
|
|
};
|
|
opp5 {
|
|
opp-hz = /bits/ 64 <1484000000>;
|
|
opp-microvolt = <737500>;
|
|
};
|
|
opp6 {
|
|
opp-hz = /bits/ 64 <1617000000>;
|
|
opp-microvolt = <768750>;
|
|
};
|
|
opp7 {
|
|
opp-hz = /bits/ 64 <1750000000>;
|
|
opp-microvolt = <800000>;
|
|
};
|
|
opp8 {
|
|
opp-hz = /bits/ 64 <1814000000>;
|
|
opp-microvolt = <837500>;
|
|
};
|
|
opp9 {
|
|
opp-hz = /bits/ 64 <1879000000>;
|
|
opp-microvolt = <875000>;
|
|
};
|
|
opp10 {
|
|
opp-hz = /bits/ 64 <1944000000>;
|
|
opp-microvolt = <912500>;
|
|
};
|
|
opp11 {
|
|
opp-hz = /bits/ 64 <2009000000>;
|
|
opp-microvolt = <950000>;
|
|
};
|
|
opp12 {
|
|
opp-hz = /bits/ 64 <2074000000>;
|
|
opp-microvolt = <987500>;
|
|
};
|
|
opp13 {
|
|
opp-hz = /bits/ 64 <2139000000>;
|
|
opp-microvolt = <1025000>;
|
|
};
|
|
opp14 {
|
|
opp-hz = /bits/ 64 <2215000000>;
|
|
opp-microvolt = <1068750>;
|
|
};
|
|
opp15 {
|
|
opp-hz = /bits/ 64 <2301000000>;
|
|
opp-microvolt = <1118750>;
|
|
};
|
|
};
|
|
|
|
cluster1_opp: opp_table1 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
opp0 {
|
|
opp-hz = /bits/ 64 <400000000>;
|
|
opp-microvolt = <600000>;
|
|
};
|
|
opp1 {
|
|
opp-hz = /bits/ 64 <501000000>;
|
|
opp-microvolt = <631250>;
|
|
};
|
|
opp2 {
|
|
opp-hz = /bits/ 64 <542000000>;
|
|
opp-microvolt = <643750>;
|
|
};
|
|
opp3 {
|
|
opp-hz = /bits/ 64 <643000000>;
|
|
opp-microvolt = <675000>;
|
|
};
|
|
opp4 {
|
|
opp-hz = /bits/ 64 <745000000>;
|
|
opp-microvolt = <706250>;
|
|
};
|
|
opp5 {
|
|
opp-hz = /bits/ 64 <846000000>;
|
|
opp-microvolt = <737500>;
|
|
};
|
|
opp6 {
|
|
opp-hz = /bits/ 64 <948000000>;
|
|
opp-microvolt = <768750>;
|
|
};
|
|
opp7 {
|
|
opp-hz = /bits/ 64 <1050000000>;
|
|
opp-microvolt = <800000>;
|
|
};
|
|
opp8 {
|
|
opp-hz = /bits/ 64 <1138000000>;
|
|
opp-microvolt = <837500>;
|
|
};
|
|
opp9 {
|
|
opp-hz = /bits/ 64 <1226000000>;
|
|
opp-microvolt = <875000>;
|
|
};
|
|
opp10 {
|
|
opp-hz = /bits/ 64 <1314000000>;
|
|
opp-microvolt = <912500>;
|
|
};
|
|
opp11 {
|
|
opp-hz = /bits/ 64 <1402000000>;
|
|
opp-microvolt = <950000>;
|
|
};
|
|
opp12 {
|
|
opp-hz = /bits/ 64 <1491000000>;
|
|
opp-microvolt = <987500>;
|
|
};
|
|
opp13 {
|
|
opp-hz = /bits/ 64 <1579000000>;
|
|
opp-microvolt = <1025000>;
|
|
};
|
|
opp14 {
|
|
opp-hz = /bits/ 64 <1682000000>;
|
|
opp-microvolt = <1068740>;
|
|
};
|
|
opp15 {
|
|
opp-hz = /bits/ 64 <1800000000>;
|
|
opp-microvolt = <1118750>;
|
|
};
|
|
};
|
|
|
|
cci_opp: opp_table2 {
|
|
compatible = "operating-points-v2";
|
|
opp-shared;
|
|
opp00 {
|
|
opp-hz = /bits/ 64 <300000000>;
|
|
opp-microvolt = <600000>;
|
|
};
|
|
opp01 {
|
|
opp-hz = /bits/ 64 <339000000>;
|
|
opp-microvolt = <618750>;
|
|
};
|
|
opp02 {
|
|
opp-hz = /bits/ 64 <392000000>;
|
|
opp-microvolt = <643750>;
|
|
};
|
|
opp03 {
|
|
opp-hz = /bits/ 64 <459000000>;
|
|
opp-microvolt = <675000>;
|
|
};
|
|
opp04 {
|
|
opp-hz = /bits/ 64 <525000000>;
|
|
opp-microvolt = <706250>;
|
|
};
|
|
opp05 {
|
|
opp-hz = /bits/ 64 <592000000>;
|
|
opp-microvolt = <737500>;
|
|
};
|
|
opp06 {
|
|
opp-hz = /bits/ 64 <658000000>;
|
|
opp-microvolt = <768750>;
|
|
};
|
|
opp07 {
|
|
opp-hz = /bits/ 64 <724000000>;
|
|
opp-microvolt = <800000>;
|
|
};
|
|
opp08 {
|
|
opp-hz = /bits/ 64 <76300000>;
|
|
opp-microvolt = <837500>;
|
|
};
|
|
opp09 {
|
|
opp-hz = /bits/ 64 <80100000>;
|
|
opp-microvolt = <875000>;
|
|
};
|
|
opp10 {
|
|
opp-hz = /bits/ 64 <84000000>;
|
|
opp-microvolt = <912500>;
|
|
};
|
|
opp11 {
|
|
opp-hz = /bits/ 64 <87800000>;
|
|
opp-microvolt = <950000>;
|
|
};
|
|
opp12 {
|
|
opp-hz = /bits/ 64 <917000000>;
|
|
opp-microvolt = <987500>;
|
|
};
|
|
opp13 {
|
|
opp-hz = /bits/ 64 <955000000>;
|
|
opp-microvolt = <1025000>;
|
|
};
|
|
opp14 {
|
|
opp-hz = /bits/ 64 <1000000000>;
|
|
opp-microvolt = <1068750>;
|
|
};
|
|
opp15 {
|
|
opp-hz = /bits/ 64 <1051000000>;
|
|
opp-microvolt = <1118750>;
|
|
};
|
|
};
|
|
|
|
cci: cci {
|
|
compatible = "mediatek,mtk-cci";
|
|
clocks = <&apmixed CLK_APMIXED_CCIPLL>;
|
|
clock-names = "dsu_clock";
|
|
operating-points-v2 = <&cci_opp>;
|
|
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
cpu0: cpu@000 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x000>;
|
|
enable-method = "psci";
|
|
clock-frequency = <2301000000>;
|
|
operating-points-v2 = <&cluster0_opp>;
|
|
dynamic-power-coefficient = <275>;
|
|
capacity-dmips-mhz = <1024>;
|
|
cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
|
|
<&SODI &SODI3 &DPIDLE &SUSPEND>;
|
|
};
|
|
|
|
cpu1: cpu@001 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x001>;
|
|
enable-method = "psci";
|
|
clock-frequency = <2301000000>;
|
|
operating-points-v2 = <&cluster0_opp>;
|
|
dynamic-power-coefficient = <275>;
|
|
capacity-dmips-mhz = <1024>;
|
|
cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
|
|
<&SODI &SODI3 &DPIDLE &SUSPEND>;
|
|
};
|
|
|
|
cpu2: cpu@002 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x002>;
|
|
enable-method = "psci";
|
|
clock-frequency = <2301000000>;
|
|
operating-points-v2 = <&cluster0_opp>;
|
|
dynamic-power-coefficient = <275>;
|
|
capacity-dmips-mhz = <1024>;
|
|
cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
|
|
<&SODI &SODI3 &DPIDLE &SUSPEND>;
|
|
};
|
|
|
|
cpu3: cpu@003 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x003>;
|
|
enable-method = "psci";
|
|
clock-frequency = <2301000000>;
|
|
operating-points-v2 = <&cluster0_opp>;
|
|
dynamic-power-coefficient = <275>;
|
|
capacity-dmips-mhz = <1024>;
|
|
cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
|
|
<&SODI &SODI3 &DPIDLE &SUSPEND>;
|
|
};
|
|
|
|
cpu4: cpu@100 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x100>;
|
|
enable-method = "psci";
|
|
clock-frequency = <1800000000>;
|
|
operating-points-v2 = <&cluster1_opp>;
|
|
dynamic-power-coefficient = <85>;
|
|
capacity-dmips-mhz = <801>;
|
|
cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
|
|
<&SODI &SODI3 &DPIDLE &SUSPEND>;
|
|
};
|
|
|
|
cpu5: cpu@101 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x101>;
|
|
enable-method = "psci";
|
|
clock-frequency = <1800000000>;
|
|
operating-points-v2 = <&cluster1_opp>;
|
|
dynamic-power-coefficient = <85>;
|
|
capacity-dmips-mhz = <801>;
|
|
cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
|
|
<&SODI &SODI3 &DPIDLE &SUSPEND>;
|
|
};
|
|
|
|
cpu6: cpu@102 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x102>;
|
|
enable-method = "psci";
|
|
clock-frequency = <1800000000>;
|
|
operating-points-v2 = <&cluster1_opp>;
|
|
dynamic-power-coefficient = <85>;
|
|
capacity-dmips-mhz = <801>;
|
|
cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
|
|
<&SODI &SODI3 &DPIDLE &SUSPEND>;
|
|
};
|
|
|
|
cpu7: cpu@103 {
|
|
device_type = "cpu";
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x103>;
|
|
enable-method = "psci";
|
|
clock-frequency = <1800000000>;
|
|
operating-points-v2 = <&cluster1_opp>;
|
|
dynamic-power-coefficient = <85>;
|
|
capacity-dmips-mhz = <801>;
|
|
cpu-idle-states = <&STANDBY &MCDI_CPU &MCDI_CLUSTER>,
|
|
<&SODI &SODI3 &DPIDLE &SUSPEND>;
|
|
};
|
|
|
|
cpu-map {
|
|
cluster0 {
|
|
core0 {
|
|
cpu = <&cpu0>;
|
|
};
|
|
core1 {
|
|
cpu = <&cpu1>;
|
|
};
|
|
core2 {
|
|
cpu = <&cpu2>;
|
|
};
|
|
core3 {
|
|
cpu = <&cpu3>;
|
|
};
|
|
};
|
|
|
|
cluster1 {
|
|
core0 {
|
|
cpu = <&cpu4>;
|
|
};
|
|
core1 {
|
|
cpu = <&cpu5>;
|
|
};
|
|
core2 {
|
|
cpu = <&cpu6>;
|
|
};
|
|
core3 {
|
|
cpu = <&cpu7>;
|
|
};
|
|
};
|
|
};
|
|
|
|
idle-states {
|
|
entry-method = "arm,psci";
|
|
|
|
STANDBY: standby {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x00000001>;
|
|
entry-latency-us = <600>;
|
|
exit-latency-us = <600>;
|
|
min-residency-us = <1200>;
|
|
};
|
|
|
|
MCDI_CPU: mcdi-cpu {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x00010001>;
|
|
entry-latency-us = <600>;
|
|
exit-latency-us = <600>;
|
|
min-residency-us = <1200>;
|
|
};
|
|
|
|
MCDI_CLUSTER: mcdi-cluster {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x01010001>;
|
|
entry-latency-us = <600>;
|
|
exit-latency-us = <600>;
|
|
min-residency-us = <1200>;
|
|
};
|
|
|
|
SODI: sodi {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x01010002>;
|
|
entry-latency-us = <800>;
|
|
exit-latency-us = <1000>;
|
|
min-residency-us = <2000>;
|
|
};
|
|
|
|
SODI3: sodi3 {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x01010003>;
|
|
entry-latency-us = <800>;
|
|
exit-latency-us = <1000>;
|
|
min-residency-us = <2000>;
|
|
};
|
|
|
|
DPIDLE: dpidle {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x01010004>;
|
|
entry-latency-us = <800>;
|
|
exit-latency-us = <1000>;
|
|
min-residency-us = <2000>;
|
|
};
|
|
|
|
SUSPEND: suspend {
|
|
compatible = "arm,idle-state";
|
|
arm,psci-suspend-param = <0x01010005>;
|
|
entry-latency-us = <800>;
|
|
exit-latency-us = <1000>;
|
|
min-residency-us = <2000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0";
|
|
method = "smc";
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,cortex-a7-pmu";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
l2c_parity {
|
|
compatible = "mediatek,l2c_parity-v1";
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
memory {
|
|
device_type = "memory";
|
|
reg = <0 0x40000000 0 0x20000000>;
|
|
};
|
|
|
|
reserved_memory: reserved-memory {
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
reserve-memory-sspm_share {
|
|
compatible = "mediatek,reserve-memory-sspm_share";
|
|
no-map;
|
|
status = "okay";
|
|
#ifdef CONFIG_MTK_GMO_RAM_OPTIMIZE
|
|
size = <0 0x110000>; /* 1M + 64K */
|
|
#else
|
|
size = <0 0x510000>; /* 5M + 64K */
|
|
#endif
|
|
alignment = <0 0x10000>;
|
|
alloc-ranges = <0 0x40000000 0 0x60000000>;
|
|
};
|
|
|
|
reserve-memory-scp_share {
|
|
compatible = "mediatek,reserve-memory-scp_share";
|
|
no-map;
|
|
#ifdef CONFIG_MTK_TINYSYS_SCP_LOGGER_SUPPORT
|
|
size = <0 0x00300000>;
|
|
#else
|
|
size = <0 0x00100000>;
|
|
#endif
|
|
alignment = <0 0x1000000>;
|
|
alloc-ranges = <0 0x40000000 0 0x50000000>;
|
|
};
|
|
|
|
consys_mem: consys-reserve-memory {
|
|
compatible = "mediatek,consys-reserve-memory";
|
|
no-map;
|
|
size = <0 0x400000>;
|
|
alignment = <0 0x1000000>;
|
|
alloc-ranges = <0 0x40000000 0 0x80000000>;
|
|
};
|
|
|
|
wifi_mem: wifi-reserve-memory {
|
|
compatible = "shared-dma-pool";
|
|
no-map;
|
|
size = <0 0x300000>;
|
|
alignment = <0 0x1000000>;
|
|
alloc-ranges = <0 0x40000000 0 0x80000000>;
|
|
};
|
|
|
|
#ifdef CONFIG_MICROTRUST_TEE_SUPPORT
|
|
soter-shared-mem {
|
|
compatible = "microtrust,shared_mem";
|
|
no-map;
|
|
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT) || \
|
|
defined(CONFIG_MTK_CAM_SECURITY_SUPPORT)
|
|
size = <0 0x800000>;
|
|
alignment = <0 0x1000000>;
|
|
#else
|
|
size = <0 0x200000>;
|
|
alignment = <0 0x200000>;
|
|
#endif
|
|
alloc-ranges = <0 0x40000000 0 0x50000000>;
|
|
};
|
|
#endif
|
|
|
|
};
|
|
|
|
cpu_dbgapb: cpu_dbgapb@0d410000 {
|
|
compatible = "mediatek,hw_dbg";
|
|
num = <8>;
|
|
reg = <0 0x0d410000 0 0x1000>,
|
|
<0 0x0d510000 0 0x1000>,
|
|
<0 0x0d610000 0 0x1000>,
|
|
<0 0x0d710000 0 0x1000>,
|
|
<0 0x0d810000 0 0x1000>,
|
|
<0 0x0d910000 0 0x1000>,
|
|
<0 0x0da10000 0 0x1000>,
|
|
<0 0x0db10000 0 0x1000>;
|
|
};
|
|
|
|
/* ATF logger SW IRQ number 279 = 32 + 247 */
|
|
atf_logger {
|
|
compatible = "mediatek,atf_logger";
|
|
interrupts = <GIC_SPI 247 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
/* AMMS SW IRQ number GIC:166 DTS:134*/
|
|
amms_control {
|
|
compatible = "mediatek,amms";
|
|
interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
/* Microtrust SW IRQ number 249(281) ~ 254(286) */
|
|
utos {
|
|
compatible = "microtrust,utos";
|
|
interrupts = <GIC_SPI 249 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 250 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
utos_tester {
|
|
compatible = "microtrust,tester-v1";
|
|
};
|
|
|
|
gic: interrupt-controller@0c000000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
#redistributor-regions = <1>;
|
|
interrupt-parent = <&gic>;
|
|
interrupt-controller;
|
|
reg = <0 0x0c000000 0 0x40000>, // distributor
|
|
<0 0x0c100000 0 0x200000>, // redistributor
|
|
<0 0x10200a80 0 0x50>; // intpol
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
dcm: dcm@10001000 {
|
|
compatible = "mediatek,mt6765-dcm";
|
|
reg = <0 0x10001000 0 0x1000>,
|
|
<0 0x10200000 0 0x1000>,
|
|
<0 0x10200000 0 0x1000>,
|
|
<0 0x10200200 0 0x1000>,
|
|
<0 0x10200400 0 0x1000>,
|
|
<0 0x1022d000 0 0x1000>,
|
|
<0 0x10235000 0 0x1000>,
|
|
<0 0x10238000 0 0x1000>,
|
|
<0 0x11220000 0 0x1000>,
|
|
<0 0x11c50000 0 0x1000>,
|
|
<0 0x13000000 0 0x1000>,
|
|
<0 0x14000000 0 0x1000>,
|
|
<0 0x14002000 0 0x1000>,
|
|
<0 0x14003000 0 0x1000>,
|
|
<0 0x15021000 0 0x1000>,
|
|
<0 0x17010000 0 0x1000>,
|
|
<0 0x17020000 0 0x1000>,
|
|
<0 0x17030000 0 0x1000>;
|
|
reg-names = "infracfg_ao",
|
|
"mcucfg",
|
|
"mp0_cpucfg",
|
|
"mp1_cpucfg",
|
|
"mcu_misccfg",
|
|
"chn0_emi",
|
|
"chn1_emi",
|
|
"gce",
|
|
"audio",
|
|
"efusec",
|
|
"mfgcfg",
|
|
"mmsys_config",
|
|
"smi_common",
|
|
"smi_larb0",
|
|
"smi_larb2",
|
|
"smi_larb1",
|
|
"venc",
|
|
"jpgenc";
|
|
};
|
|
|
|
sysirq: intpol-controller@10200a80 {
|
|
compatible = "mediatek,mt6577-sysirq";
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupt-parent = <&gic>;
|
|
reg = <0 0x10200a80 0 0x50>;
|
|
};
|
|
|
|
infracfg_ao: infracfg_ao@10001000 {
|
|
compatible = "mediatek,common-infracfg_ao",
|
|
"mediatek,infracfg_ao",
|
|
"mediatek,mt6765-infracfg", "syscon";
|
|
reg = <0 0x10001000 0 0x1000>;
|
|
interrupts = <GIC_SPI 147 IRQ_TYPE_EDGE_RISING>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mcdi@0010fc00 {
|
|
compatible = "mediatek,mt6765-mcdi";
|
|
reg = <0 0x0010fc00 0 0x800>;
|
|
};
|
|
|
|
scpsys: scpsys@10001000 {
|
|
compatible = "mediatek,mt6765-scpsys", "syscon";
|
|
reg = <0 0x10001000 0 0x1000>, /* infra_ao */
|
|
<0 0x10006000 0 0x1000>, /* spm */
|
|
<0 0x14002000 0 0x1000>, /* spi_common */
|
|
<0 0x1020e000 0 0x1000>, /* infracfg */
|
|
<0 0x18004000 0 0x1000>, /* connsys */
|
|
<0 0x18002000 0 0x1000>; /* connsys mcu */
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
topckgen: topckgen@10000000 {
|
|
compatible = "mediatek,mt6765-topckgen", "syscon";
|
|
reg = <0 0x10000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
scp_infra: scp_infra@10001000 {
|
|
compatible = "mediatek,scpinfra";
|
|
reg = <0 0x10001000 0 0x1000>;
|
|
};
|
|
|
|
io_cfg_lt: io_cfg_lt@10002000 {
|
|
compatible = "mediatek,io_cfg_lt";
|
|
reg = <0 0x10002000 0 0x200>;
|
|
};
|
|
|
|
io_cfg_lm: io_cfg_lm@10002200 {
|
|
compatible = "mediatek,io_cfg_lm";
|
|
reg = <0 0x10002200 0 0x200>;
|
|
};
|
|
|
|
io_cfg_lb: io_cfg_lb@10002400 {
|
|
compatible = "mediatek,io_cfg_lb";
|
|
reg = <0 0x10002400 0 0x200>;
|
|
};
|
|
|
|
io_cfg_bl: io_cfg_bl@10002600 {
|
|
compatible = "mediatek,io_cfg_bl";
|
|
reg = <0 0x10002600 0 0x200>;
|
|
};
|
|
|
|
io_cfg_rr: io_cfg_rr@10002800 {
|
|
compatible = "mediatek,io_cfg_rr";
|
|
reg = <0 0x10002800 0 0x200>;
|
|
};
|
|
|
|
io_cfg_rb: io_cfg_rb@10002a00 {
|
|
compatible = "mediatek,io_cfg_rb";
|
|
reg = <0 0x10002a00 0 0x200>;
|
|
};
|
|
|
|
io_cfg_rt: io_cfg_rt@10002c00 {
|
|
compatible = "mediatek,io_cfg_rt";
|
|
reg = <0 0x10002c00 0 0x200>;
|
|
};
|
|
|
|
pericfg: pericfg@10003000 {
|
|
compatible = "mediatek,pericfg", "syscon";
|
|
reg = <0 0x10003000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
efuse_dbg@10004000 {
|
|
compatible = "mediatek,efuse_dbg";
|
|
reg = <0 0x10004000 0 0x1000>;
|
|
};
|
|
|
|
gpio_usage_mapping:gpio {
|
|
compatible = "mediatek,gpio_usage_mapping";
|
|
};
|
|
|
|
eint: eint@1000b000 {
|
|
compatible = "mediatek,eint";
|
|
reg = <0 0x1000b000 0 0x1000>;
|
|
};
|
|
|
|
gpio: gpio@10005000 {
|
|
compatible = "mediatek,gpio", "syscon";
|
|
reg = <0 0x10005000 0 0x1000>;
|
|
};
|
|
|
|
pio: pinctrl@1000b000 {
|
|
compatible = "mediatek,mt6765-pinctrl";
|
|
reg_bases = <&gpio>,
|
|
<&io_cfg_lt>,
|
|
<&io_cfg_lm>,
|
|
<&io_cfg_lb>,
|
|
<&io_cfg_bl>,
|
|
<&io_cfg_rr>,
|
|
<&io_cfg_rb>,
|
|
<&io_cfg_rt>;
|
|
pins-are-numbered;
|
|
gpio-controller;
|
|
gpio-ranges = <&pio 0 0 179>;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&gic>;
|
|
};
|
|
|
|
sleep: sleep@10006000 {
|
|
compatible = "mediatek,sleep", "syscon";
|
|
reg = <0 0x10006000 0 0x1000>;
|
|
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
|
|
wakeup-source = <&keypad 0 (1 << 2)>,
|
|
<&consys 1 (1 << 5)>,
|
|
<&mddriver 3 (1 << 25)>;
|
|
};
|
|
|
|
toprgu: toprgu@10007000 {
|
|
compatible = "mediatek,mt6765-wdt",
|
|
"mediatek,mt6589-wdt",
|
|
"mediatek,toprgu",
|
|
"syscon", "simple-mfd";
|
|
reg = <0 0x10007000 0 0x1000>;
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
|
|
#reset-cells = <1>;
|
|
reboot-mode {
|
|
compatible = "syscon-reboot-mode";
|
|
offset = <0x24>;
|
|
mask = <0xf>;
|
|
mode-charger = <BOOT_CHARGER>;
|
|
mode-recovery = <BOOT_RECOVERY>;
|
|
mode-bootloader = <BOOT_BOOTLOADER>;
|
|
mode-dm-verity-dev-corrupt = <BOOT_DM_VERITY>;
|
|
mode-kpoc = <BOOT_KPOC>;
|
|
mode-ddr-reserve = <BOOT_DDR_RSVD>;
|
|
mode-meta = <BOOT_META>;
|
|
mode-rpmbpk = <BOOT_RPMBPK>;
|
|
};
|
|
};
|
|
|
|
chipid@08000000 {
|
|
compatible = "mediatek,chipid";
|
|
reg = <0 0x08000000 0 0x0004>,
|
|
<0 0x08000004 0 0x0004>,
|
|
<0 0x08000008 0 0x0004>,
|
|
<0 0x0800000c 0 0x0004>;
|
|
};
|
|
|
|
mobicore {
|
|
compatible = "trustonic,mobicore";
|
|
interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
tkcore {
|
|
compatible = "trustkernel,tkcore";
|
|
interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
|
clock-frequency = <13000000>;
|
|
};
|
|
|
|
clocks {
|
|
clk26m: clk26m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <26000000>;
|
|
};
|
|
|
|
clk13m: clk13m {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <13000000>;
|
|
};
|
|
|
|
clk32k: clk32k {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32000>;
|
|
};
|
|
};
|
|
|
|
apxgpt@10008000 {
|
|
compatible = "mediatek,apxgpt";
|
|
reg = <0 0x10008000 0 0x1000>;
|
|
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks =
|
|
<&clk32k>;
|
|
};
|
|
|
|
hacc@1000a000 {
|
|
compatible = "mediatek,hacc";
|
|
reg = <0 0x1000a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
apmixed: apmixed@1000c000 {
|
|
compatible = "mediatek,mt6765-apmixedsys", "syscon";
|
|
reg = <0 0x1000c000 0 0xe00>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
fhctl@1000ce00 {
|
|
compatible = "mediatek,mt6765-fhctl";
|
|
reg = <0 0x1000ce00 0 0x100>;
|
|
mediatek,apmixed = <&apmixed>;
|
|
|
|
armpll {
|
|
mediatek,fh-id = <0>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_ARMPLL>;
|
|
mediatek,fh-cpu-pll;
|
|
};
|
|
|
|
mainpll {
|
|
mediatek,fh-id = <1>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_MAINPLL>;
|
|
};
|
|
|
|
msdcpll {
|
|
mediatek,fh-id = <2>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_MSDCPLL>;
|
|
};
|
|
|
|
mfgpll {
|
|
mediatek,fh-id = <3>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_MFGPLL>;
|
|
};
|
|
|
|
mpll {
|
|
mediatek,fh-id = <5>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_MPLL>;
|
|
};
|
|
|
|
mmpll {
|
|
mediatek,fh-id = <6>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_MMPLL>;
|
|
};
|
|
|
|
armpll_l {
|
|
mediatek,fh-id = <7>;
|
|
mediatek,fh-pll-id = <CLK_APMIXED_ARMPLL_L>;
|
|
mediatek,fh-cpu-pll;
|
|
};
|
|
};
|
|
|
|
pwrap: pwrap@1000d000 {
|
|
compatible = "mediatek,mt6765-pwrap", "syscon";
|
|
reg = <0 0x1000d000 0 0x1000>;
|
|
reg-names = "pwrap";
|
|
interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk26m>, <&infracfg_ao CLK_IFR_PMIC_AP>,
|
|
<&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
|
|
clock-names = "spi", "wrap", "ulposc";
|
|
|
|
main_pmic: main_pmic {
|
|
compatible = "mediatek,mt6357";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&pio>;
|
|
interrupts = <144 IRQ_TYPE_LEVEL_HIGH 144 0>;
|
|
|
|
mtk_battery_oc_throttling {
|
|
compatible =
|
|
"mediatek,mt6357-battery_oc_throttling";
|
|
oc-thd-h = <4670>;
|
|
oc-thd-l = <5500>;
|
|
};
|
|
};
|
|
};
|
|
|
|
scp@10500000 {
|
|
compatible = "mediatek,scp";
|
|
status = "okay";
|
|
reg = <0 0x10500000 0 0x40000>,
|
|
<0 0x105c0000 0 0x3000>,
|
|
<0 0x105c4000 0 0x1000>,
|
|
<0 0x105d4000 0 0x6000>;
|
|
interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
|
|
core_1 = "enable";
|
|
scp_sramSize = <0x00040000>;
|
|
scp_mpuRegionId = <27>;
|
|
scp_feature_tbl = <0 47>, /* vow */
|
|
<1 356>, /* dsp */
|
|
<2 62>, /* sensor */
|
|
<3 47>, /* mp3 */
|
|
<4 26>, /* flp */
|
|
<5 0>, /* rtos */
|
|
<6 200>, /* speaker */
|
|
<7 0>, /* vcore */
|
|
<8 100>, /* barge in */
|
|
<9 10>; /* vow dump */
|
|
|
|
scp_mem_key = "mediatek,reserve-memory-scp_share";
|
|
#ifdef CONFIG_MTK_TINYSYS_SCP_LOGGER_SUPPORT
|
|
scp_mem_tbl = <1 0x100000>, /* sensor */
|
|
<4 0x200000>; /* logger */
|
|
#else
|
|
scp_mem_tbl = <1 0x100000>; /* sensor */
|
|
#endif
|
|
};
|
|
|
|
scp_dvfs {
|
|
compatible = "mediatek,scp_dvfs";
|
|
clocks = <&topckgen CLK_TOP_SCP_SEL>,
|
|
<&clk26m>,
|
|
<&topckgen CLK_TOP_SYSPLL4_D2>,
|
|
<&topckgen CLK_TOP_UNIVPLL2_D2>,
|
|
<&topckgen CLK_TOP_SYSPLL1_D2>,
|
|
<&topckgen CLK_TOP_UNIVPLL1_D2>,
|
|
<&topckgen CLK_TOP_SYSPLL_D3>,
|
|
<&topckgen CLK_TOP_UNIVPLL_D3>;
|
|
|
|
clock-names = "clk_mux",
|
|
"clk_pll_0",
|
|
"clk_pll_1",
|
|
"clk_pll_2",
|
|
"clk_pll_3",
|
|
"clk_pll_4",
|
|
"clk_pll_5",
|
|
"clk_pll_6";
|
|
|
|
dvfsrc-opp-num = <3>;
|
|
dvfs-opp =
|
|
/* vcore vsram uv dvfsrc spm freq mux */
|
|
< 0xff 0xff 0xff 0x0 0x0 250 0>,
|
|
< 0xff 0xff 0xff 0x0 0x0 273 3>,
|
|
< 0xff 0xff 0xff 0x2 0x8 330 5>,
|
|
< 0xff 0xff 0xff 0x3 0xC 416 6>;
|
|
|
|
pmic = <&main_pmic>;
|
|
pmic-feature = "pmic-vow-lp", "pmic-pmrc";
|
|
/*
|
|
* feature on off setting.
|
|
* 1: turns on, 0: turns off.
|
|
*/
|
|
pmic-feature-cfg = <0 0>;
|
|
|
|
gpio = <&gpio 1>;
|
|
gpio-feature = "gpio-mode";
|
|
gpio-feature-cfg = <0>;
|
|
};
|
|
|
|
sleep_reg_md@1000f000 {
|
|
compatible = "mediatek,sleep_reg_md";
|
|
reg = <0 0x1000f000 0 0x1000>;
|
|
};
|
|
|
|
keypad: kp@10010000 {
|
|
compatible = "mediatek,kp";
|
|
reg = <0 0x10010000 0 0x1000>;
|
|
interrupts = <GIC_SPI 180 IRQ_TYPE_EDGE_FALLING>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "kpd";
|
|
};
|
|
|
|
otg_iddig: otg_iddig{
|
|
compatible = "mediatek,usb_iddig_bi_eint";
|
|
};
|
|
|
|
mrdump_ext_rst: mrdump_ext_rst {
|
|
compatible = "mediatek, mrdump_ext_rst-eint";
|
|
force_mode = "EINT";
|
|
mode = "IRQ";
|
|
status = "okay";
|
|
};
|
|
|
|
touch: touch {
|
|
compatible = "goodix,touch";
|
|
};
|
|
|
|
accdet: accdet {
|
|
compatible = "mediatek,pmic-accdet";
|
|
};
|
|
|
|
goodix_fp: fingerprint {
|
|
compatible = "mediatek,goodix-fp";
|
|
};
|
|
|
|
topmisc@10011000 {
|
|
compatible = "mediatek,topmisc";
|
|
reg = <0 0x10011000 0 0x1000>;
|
|
};
|
|
|
|
dvfsrc: dvfsrc@10012000 {
|
|
compatible = "mediatek,mt6765-dvfsrc";
|
|
reg = <0 0x10012000 0 0x1000>,
|
|
<0 0x10006000 0 0x1000>;
|
|
reg-names = "dvfsrc", "spm";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
dvfsrc_freq_opp2: opp2 {
|
|
opp-level = <2>;
|
|
};
|
|
dvfsrc_freq_opp1: opp1 {
|
|
opp-level = <1>;
|
|
};
|
|
dvfsrc_freq_opp0: opp0 {
|
|
opp-level = <0>;
|
|
};
|
|
|
|
dvfsrc-up {
|
|
compatible = "mediatek,mt6765-dvfsrc-up";
|
|
};
|
|
|
|
dvfsrc-debug {
|
|
compatible = "mediatek,mt6765-dvfsrc-debug";
|
|
required-opps = <&dvfsrc_freq_opp0>,
|
|
<&dvfsrc_freq_opp1>,
|
|
<&dvfsrc_freq_opp2>;
|
|
};
|
|
|
|
dvfsrc-met {
|
|
compatible = "mediatek,mt6765-dvfsrc-met";
|
|
};
|
|
|
|
qos@00110780 {
|
|
compatible = "mediatek,mt6765-qos";
|
|
reg = <0 0x00110780 0 0x80>;
|
|
};
|
|
};
|
|
|
|
mbist_ao@10013000 {
|
|
compatible = "mediatek,mbist_ao";
|
|
reg = <0 0x10013000 0 0x1000>;
|
|
};
|
|
|
|
apcldmain_ao@10014000 {
|
|
compatible = "mediatek,apcldmain_ao";
|
|
reg = <0 0x10014000 0 0x400>;
|
|
};
|
|
|
|
apcldmaout_ao@10014400 {
|
|
compatible = "mediatek,apcldmaout_ao";
|
|
reg = <0 0x10014400 0 0x400>;
|
|
};
|
|
|
|
apcldmamisc_ao@10014800 {
|
|
compatible = "mediatek,apcldmamisc_ao";
|
|
reg = <0 0x10014800 0 0x400>;
|
|
};
|
|
|
|
ddrphy@10015000 {
|
|
compatible = "mediatek,ddrphy";
|
|
reg = <0 0x10015000 0 0x1000>;
|
|
};
|
|
|
|
aes_top0@10016000 {
|
|
compatible = "mediatek,aes_top0";
|
|
reg = <0 0x10016000 0 0x1000>;
|
|
};
|
|
|
|
timer: timer@10017000 {
|
|
compatible = "mediatek,sys_timer",
|
|
"mediatek,mt6761-timer",
|
|
"mediatek,mt6765-timer";
|
|
reg = <0 0x10017000 0 0x1000>;
|
|
reg-names = "sys_timer_base";
|
|
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clk13m>;
|
|
};
|
|
|
|
modem_temp_share@10018000 {
|
|
compatible = "mediatek,modem_temp_share";
|
|
reg = <0 0x10018000 0 0x1000>;
|
|
};
|
|
|
|
security_ao@1001a000 {
|
|
compatible = "mediatek,security_ao";
|
|
reg = <0 0x1001a000 0 0x1000>;
|
|
};
|
|
|
|
topckgen_ao@1001b000 {
|
|
compatible = "mediatek,topckgen_ao";
|
|
reg = <0 0x1001b000 0 0x1000>;
|
|
};
|
|
|
|
dramc0@1001d000 {
|
|
compatible = "mediatek,dramc0";
|
|
reg = <0 0x1001d000 0 0x1000>;
|
|
};
|
|
|
|
ddrphy@1001e000 {
|
|
compatible = "mediatek,ddrphy";
|
|
reg = <0 0x1001e000 0 0x1000>;
|
|
};
|
|
|
|
mdcldmain_ao@10015000 {
|
|
compatible = "mediatek,mdcldmain_ao";
|
|
reg = <0 0x10015000 0 0x400>;
|
|
};
|
|
|
|
mdcldmaout_ao@10015400 {
|
|
compatible = "mediatek,mdcldmaout_ao";
|
|
reg = <0 0x10015400 0 0x400>;
|
|
};
|
|
|
|
mdcldmamisc_ao@10015800 {
|
|
compatible = "mediatek,mdcldmamisc_ao";
|
|
reg = <0 0x10015800 0 0x400>;
|
|
};
|
|
|
|
sys_cirq@10204000 {
|
|
compatible = "mediatek,sys_cirq";
|
|
reg = <0 0x10204000 0 0x1000>;
|
|
mediatek,cirq_num = <209>;
|
|
mediatek,spi_start_offset = <72>;
|
|
interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
mcucfg@10200000 {
|
|
compatible = "mediatek,mcucfg";
|
|
reg = <0 0x10200000 0 0x1000>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
mcucfg_mp0_counter@10200000 {
|
|
compatible = "mediatek,mcucfg_mp0_counter";
|
|
reg = <0 0x10200000 0 0x4000>;
|
|
};
|
|
|
|
m4u@10205000 {
|
|
cell-index = <0>;
|
|
compatible = "mediatek,m4u";
|
|
reg = <0 0x10205000 0 0x1000>;
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
devapc@10207000 {
|
|
compatible = "mediatek,devapc";
|
|
reg = <0 0x10207000 0 0x1000>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_IFR_DEVICE_APC>;
|
|
clock-names = "devapc-infra-clock";
|
|
};
|
|
|
|
hwrng: hwrng {
|
|
compatible = "mediatek,mt67xx-rng";
|
|
};
|
|
|
|
bus_dbg@10208000 {
|
|
compatible = "mediatek,bus_dbg-v2";
|
|
reg = <0 0x10208000 0 0x1000>,
|
|
<0 0x10001000 0 0x1000>;
|
|
mediatek,bus_dbg_con_offset = <0x2fc>;
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
ap_ccif0@10209000 {
|
|
compatible = "mediatek,ap_ccif0";
|
|
reg = <0 0x10209000 0 0x1000>;
|
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
md_ccif0@1020a000 {
|
|
compatible = "mediatek,md_ccif0";
|
|
reg = <0 0x1020a000 0 0x1000>;
|
|
};
|
|
|
|
ap_ccif1@1020b000 {
|
|
compatible = "mediatek,ap_ccif1";
|
|
reg = <0 0x1020b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
md_ccif1@1020c000 {
|
|
compatible = "mediatek,md_ccif1";
|
|
reg = <0 0x1020c000 0 0x1000>;
|
|
};
|
|
|
|
infra_mbist@1020d000 {
|
|
compatible = "mediatek,infra_mbist";
|
|
reg = <0 0x1020d000 0 0x1000>;
|
|
};
|
|
|
|
infracfg@1020e000 {
|
|
compatible = "mediatek,infracfg";
|
|
reg = <0 0x1020e000 0 0x1000>;
|
|
};
|
|
|
|
trng@1020f000 {
|
|
compatible = "mediatek,trng";
|
|
reg = <0 0x1020f000 0 0x1000>;
|
|
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
dxcc_sec@10210000 {
|
|
compatible = "mediatek,dxcc_sec";
|
|
reg = <0 0x10210000 0 0x1000>;
|
|
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
mcupm_sram2@10211000 {
|
|
compatible = "mediatek,mcupm_sram2";
|
|
reg = <0 0x10211000 0 0x1000>;
|
|
};
|
|
|
|
cq_dma@10212000 {
|
|
compatible = "mediatek,mt-cqdma-v1";
|
|
reg = <0 0x10212000 0 0x80>,
|
|
<0 0x10212080 0 0x80>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
|
|
nr_channel = <2>;
|
|
keep_clock_ao = "yes";
|
|
clocks = <&infracfg_ao CLK_IFR_CQ_DMA>;
|
|
clock-names = "cqdma";
|
|
};
|
|
|
|
mcupm_sram3@10213000 {
|
|
compatible = "mediatek,mcupm_sram3";
|
|
reg = <0 0x10213000 0 0x1000>;
|
|
};
|
|
|
|
sramrom@10214000 {
|
|
compatible = "mediatek,sramrom";
|
|
reg = <0 0x10214000 0 0x1000>;
|
|
};
|
|
|
|
mcupm_reg@10216000 {
|
|
compatible = "mediatek,mcupm_reg";
|
|
reg = <0 0x10216000 0 0x1000>;
|
|
};
|
|
|
|
mcupm_sram0@10217000 {
|
|
compatible = "mediatek,mcupm_sram0";
|
|
reg = <0 0x10217000 0 0x1000>;
|
|
};
|
|
|
|
mcupm_sram1@10218000 {
|
|
compatible = "mediatek,mcupm_sram1";
|
|
reg = <0 0x10218000 0 0x1000>;
|
|
};
|
|
|
|
emi@10219000 {
|
|
compatible = "mediatek,emi";
|
|
reg = <0 0x10219000 0 0x1000>, /* CEN EMI */
|
|
<0 0x10226000 0 0x1000>, /* EMI MPU */
|
|
<0 0x1022d000 0 0x1000>, /* CHA EMI */
|
|
<0 0x10235000 0 0x1000>; /* CHB EMI */
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; /* MPU */
|
|
};
|
|
|
|
apcldmain@1021b000 {
|
|
compatible = "mediatek,apcldmain";
|
|
reg = <0 0x1021b000 0 0x0>;
|
|
};
|
|
|
|
apcldmaout@1021b400 {
|
|
compatible = "mediatek,apcldmaout";
|
|
reg = <0 0x1021b400 0 0x0>;
|
|
};
|
|
|
|
apcldmamisc@1021b800 {
|
|
compatible = "mediatek,apcldmamisc";
|
|
reg = <0 0x1021b800 0 0x0>;
|
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
mdcldmain@1021c000 {
|
|
compatible = "mediatek,mdcldmain";
|
|
reg = <0 0x1021c000 0 0x400>;
|
|
};
|
|
|
|
mdcldmaout@1021c400 {
|
|
compatible = "mediatek,mdcldmaout";
|
|
reg = <0 0x1021c400 0 0x400>;
|
|
};
|
|
|
|
mdcldmamisc@1021c800 {
|
|
compatible = "mediatek,mdcldmamisc";
|
|
reg = <0 0x1021c800 0 0x1000>;
|
|
};
|
|
|
|
ccifdriver:ccifdriver@10209000 {
|
|
compatible = "mediatek,ccci_ccif";
|
|
reg = <0 0x10209000 0 0x1000>, /*AP_CCIF_BASE*/
|
|
<0 0x1020a000 0 0x1000>; /*MD_CCIF_BASE*/
|
|
mediatek,sram_size = <512>;
|
|
/*CCIF0 174/206, CCIF0 175/207*/
|
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 149 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_IFR_CCIF_AP>,
|
|
<&infracfg_ao CLK_IFR_CCIF_MD>,
|
|
<&infracfg_ao CLK_IFR_CCIF1_AP>,
|
|
<&infracfg_ao CLK_IFR_CCIF1_MD>,
|
|
<&infracfg_ao CLK_IFR_CCIF2_AP>,
|
|
<&infracfg_ao CLK_IFR_CCIF2_MD>;
|
|
clock-names = "infra-ccif-ap",
|
|
"infra-ccif-md",
|
|
"infra-ccif1-ap",
|
|
"infra-ccif1-md",
|
|
"infra-ccif2-ap",
|
|
"infra-ccif2-md";
|
|
};
|
|
|
|
cldmadriver:cldmadriver@10014000 {
|
|
compatible = "mediatek,ccci_cldma";
|
|
reg = <0 0x10014000 0 0x1000>, /*AP_CLDMA_AO "mediatek,apcldmain_ao*/
|
|
<0 0x1021b000 0 0x1000>; /*AP_CLDMA_PDN "mediatek,apcldmain*/
|
|
/*CCIF0 174/206, IRQ_CLDMA "mediatek,apcldmamisc"*/
|
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
|
mediatek,cldma_capability = <6>;
|
|
mediatek,md_generation = <6293>;
|
|
mediatek,platform = <6765>;
|
|
clocks = <&infracfg_ao CLK_IFR_CLDMA_BCLK>;
|
|
clock-names = "infra-cldma-bclk";
|
|
cldma-infracfg = <&infracfg_ao>;
|
|
};
|
|
|
|
mddriver:mddriver@10014000 {
|
|
compatible = "mediatek,mddriver", "mediatek,mddriver-mt6765";
|
|
/*
|
|
* AP_CLDMA_AO "mediatek,apcldmain_ao"
|
|
* AP_CLDMA_PDN "mediatek,apcldmain"
|
|
* AP_CCIF_BASE "mediatek,ap_ccif0"
|
|
* MD_CCIF_BASE "mediatek,md_ccif0"
|
|
*/
|
|
reg = <0 0x10014000 0 0x1000>,
|
|
<0 0x1021b000 0 0x1000>,
|
|
<0 0x10209000 0 0x1000>,
|
|
<0 0x1020a000 0 0x1000>;
|
|
/*
|
|
* IRQ_CLDMA "mediatek,apcldmamisc"
|
|
* IRQ_CCIF0 "mediatek,ap_ccif0"
|
|
* IRQ_CCIF1
|
|
* IRQ_MDWDT "mediatek,md_rgu"
|
|
*/
|
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 148 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 149 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 261 IRQ_TYPE_EDGE_FALLING>;
|
|
mediatek,mdhif_type = <3>; /* bit0~3: CLDMA|CCIF|DPMAIF */
|
|
mediatek,md_id = <0>;
|
|
mediatek,ap_plat_info = <6765>;
|
|
mediatek,md_generation = <6293>;
|
|
mediatek,offset_apon_md1 = <0x1C24>;
|
|
mediatek,cldma_capability = <6>;
|
|
clocks = <&scpsys SCP_SYS_MD1>,
|
|
<&infracfg_ao CLK_IFR_CLDMA_BCLK>,
|
|
<&infracfg_ao CLK_IFR_CCIF_AP>,
|
|
<&infracfg_ao CLK_IFR_CCIF_MD>,
|
|
<&infracfg_ao CLK_IFR_CCIF1_AP>,
|
|
<&infracfg_ao CLK_IFR_CCIF1_MD>,
|
|
<&infracfg_ao CLK_IFR_CCIF2_AP>,
|
|
<&infracfg_ao CLK_IFR_CCIF2_MD>;
|
|
clock-names = "scp-sys-md1-main",
|
|
"infra-cldma-bclk",
|
|
"infra-ccif-ap",
|
|
"infra-ccif-md",
|
|
"infra-ccif1-ap",
|
|
"infra-ccif1-md",
|
|
"infra-ccif2-ap",
|
|
"infra-ccif2-md";
|
|
_vmodem-supply = <&mt_pmic_vmodem_buck_reg>;
|
|
_vcore-supply = <&mt_pmic_vcore_buck_reg>;
|
|
ccci-infracfg = <&infracfg_ao>;
|
|
};
|
|
|
|
md_auxadc:md_auxadc {
|
|
compatible = "mediatek,md_auxadc";
|
|
io-channels = <&auxadc 2>;
|
|
io-channel-names = "md-channel",
|
|
"md-battery";
|
|
};
|
|
|
|
dramc_nao@1021d000 {
|
|
compatible = "mediatek,dramc_nao";
|
|
reg = <0 0x1021d000 0 0x1000>;
|
|
};
|
|
|
|
bpi_bsi_slv0@1021e000 {
|
|
compatible = "mediatek,bpi_bsi_slv0";
|
|
reg = <0 0x1021e000 0 0x1000>;
|
|
};
|
|
|
|
bpi_bsi_slv1@1021f000 {
|
|
compatible = "mediatek,bpi_bsi_slv1";
|
|
reg = <0 0x1021f000 0 0x6000>;
|
|
};
|
|
|
|
bpi_bsi_slv2@10225000 {
|
|
compatible = "mediatek,bpi_bsi_slv2";
|
|
reg = <0 0x10225000 0 0x1000>;
|
|
};
|
|
|
|
dvfsp@10227000 {
|
|
compatible = "mediatek,dvfsp";
|
|
reg = <0 0x10227000 0 0x1000>;
|
|
};
|
|
|
|
dvfsp@00110800 {
|
|
compatible = "mediatek,mt6765-dvfsp";
|
|
reg = <0 0x00110800 0 0x1400>,
|
|
<0 0x00110800 0 0x1400>;
|
|
state = <1>;
|
|
change_flag = <0>;
|
|
little-rise-time = <1000>;
|
|
little-down-time = <750>;
|
|
big-rise-time = <1000>;
|
|
big-down-time = <750>;
|
|
nvmem-cells = <&efuse_segment &efuse_ly>;
|
|
nvmem-cell-names = "efuse_segment_cell","efuse_ly_cell";
|
|
L-table = <2000 96 1 1
|
|
1933 92 1 1
|
|
1866 88 1 1
|
|
1800 83 1 1
|
|
1733 80 1 1
|
|
1666 75 1 1
|
|
1548 71 1 1
|
|
1475 66 2 1
|
|
1375 64 2 1
|
|
1275 58 2 1
|
|
1175 54 2 1
|
|
1075 49 2 1
|
|
999 46 2 1
|
|
925 43 2 1
|
|
850 40 2 1
|
|
774 38 2 1 >;
|
|
|
|
B-table = <2200 100 1 1
|
|
2133 96 1 1
|
|
2066 92 1 1
|
|
2000 88 1 1
|
|
1933 84 1 1
|
|
1866 80 1 1
|
|
1800 75 1 1
|
|
1651 70 1 1
|
|
1503 64 1 1
|
|
1414 61 2 1
|
|
1295 57 2 1
|
|
1176 53 2 1
|
|
1087 49 2 1
|
|
998 46 2 1
|
|
909 43 2 1
|
|
850 40 2 1 >;
|
|
|
|
CCI-table = <1400 96 2 1
|
|
1353 92 2 1
|
|
1306 88 2 1
|
|
1260 84 2 1
|
|
1190 78 2 1
|
|
1155 75 2 1
|
|
1120 71 2 1
|
|
984 64 2 1
|
|
917 62 2 1
|
|
827 58 2 1
|
|
737 54 2 2
|
|
669 51 2 2
|
|
579 47 2 2
|
|
512 44 2 2
|
|
445 41 2 2
|
|
400 38 2 2 >;
|
|
};
|
|
|
|
eem_fsm@1100b000 {
|
|
compatible = "mediatek,eem_fsm";
|
|
reg = <0 0x1100b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_LOW>;
|
|
nvmem = <&efuse>;
|
|
nvmem-names = "mtk_efuse";
|
|
nvmem-cells = <&efuse_segment>;
|
|
nvmem-cell-names = "efuse_segment_cell";
|
|
};
|
|
|
|
dramc@1022a000 {
|
|
compatible = "mediatek,dramc";
|
|
reg = <0 0x1022a000 0 0x2000>, /* DRAMC AO CHA */
|
|
<0 0x10232000 0 0x2000>, /* DRAMC AO CHB */
|
|
<0 0x1022c000 0 0x1000>, /* DRAMC NAO CHA */
|
|
<0 0x10234000 0 0x1000>, /* DRAMC NAO CHB */
|
|
<0 0x10228000 0 0x2000>, /* DDRPHY AO CHA */
|
|
<0 0x10230000 0 0x2000>, /* DDRPHY AO CHB */
|
|
<0 0x1022e000 0 0x1000>, /* DDRPHY NAO CHA */
|
|
<0 0x10236000 0 0x1000>; /* DDRPHY NAO CHB */
|
|
};
|
|
|
|
gce: gce@10238000 {
|
|
compatible = "mediatek,gce", "syscon";
|
|
reg = <0 0x10238000 0 0x4000>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_LOW>;
|
|
g3d_config_base = <0x13000000 0 0xffff0000>;
|
|
mmsys_config_base = <0x14000000 1 0xffff0000>;
|
|
disp_dither_base = <0x14010000 2 0xffff0000>;
|
|
mm_na_base = <0x14020000 3 0xffff0000>;
|
|
imgsys_base = <0x15020000 4 0xffff0000>;
|
|
vdec_gcon_base = <0x18800000 5 0xffff0000>;
|
|
venc_gcon_base = <0x18810000 6 0xffff0000>;
|
|
conn_peri_base = <0x18820000 7 0xffff0000>;
|
|
topckgen_base = <0x18830000 8 0xffff0000>;
|
|
kp_base = <0x18840000 9 0xffff0000>;
|
|
scp_sram_base = <0x10000000 10 0xffff0000>;
|
|
infra_na3_base = <0x10010000 11 0xffff0000>;
|
|
infra_na4_base = <0x10020000 12 0xffff0000>;
|
|
scp_base = <0x10030000 13 0xffff0000>;
|
|
mcucfg_base = <0x10040000 14 0xffff0000>;
|
|
gcpu_base = <0x10050000 15 0xffff0000>;
|
|
usb0_base = <0x10200000 16 0xffff0000>;
|
|
usb_sif_base = <0x10280000 17 0xffff0000>;
|
|
audio_base = <0x17000000 18 0xffff0000>;
|
|
vdec_base = <0x17010000 19 0xffff0000>;
|
|
msdc2_base = <0x17020000 20 0xffff0000>;
|
|
vdec1_base = <0x17030000 21 0xffff0000>;
|
|
msdc3_base = <0x18000000 22 0xffff0000>;
|
|
ap_dma_base = <0x18010000 23 0xffff0000>;
|
|
gce_base = <0x18020000 24 0xffff0000>;
|
|
vdec2_base = <0x18040000 25 0xffff0000>;
|
|
vdec3_base = <0x18050000 26 0xffff0000>;
|
|
camsys_base = <0x18080000 27 0xffff0000>;
|
|
camsys1_base = <0x180a0000 28 0xffff0000>;
|
|
camsys2_base = <0x180b0000 29 0xffff0000>;
|
|
pwm_sw_base = <0x1100e000 99 0xffff0000>;
|
|
mipitx0_base = <0x11c80000 99 0xffff0000>;
|
|
mdp_rdma0_sof = <0>;
|
|
mdp_ccorr0_sof = <1>;
|
|
mdp_rsz0_sof = <2>;
|
|
mdp_rsz1_sof = <3>;
|
|
mdp_wdma_sof = <4>;
|
|
mdp_wrot0_sof = <5>;
|
|
mdp_tdshp0_sof = <6>;
|
|
disp_ovl0_sof = <7>;
|
|
disp_2l_ovl0_sof = <8>;
|
|
disp_rdma0_sof = <9>;
|
|
disp_wdma0_sof = <10>;
|
|
disp_color0_sof = <11>;
|
|
disp_ccorr0_sof = <12>;
|
|
disp_aal0_sof = <13>;
|
|
disp_gamma0_sof = <14>;
|
|
disp_dither0_sof = <15>;
|
|
disp_dsi0_sof = <16>;
|
|
disp_rsz0_sof = <17>;
|
|
img_dl_relay_sof = <18>;
|
|
disp_pwm0_sof = <19>;
|
|
mdp_rdma0_frame_done = <20>;
|
|
mdp_ccorr0_frame_done = <21>;
|
|
mdp_rsz0_frame_done = <22>;
|
|
mdp_rsz1_frame_done = <23>;
|
|
mdp_wrot0_write_frame_done = <24>;
|
|
mdp_wdma_frame_done = <25>;
|
|
mdp_tdshp0_frame_done = <26>;
|
|
disp_ovl0_frame_done = <27>;
|
|
disp_2l_ovl0_frame_done = <28>;
|
|
disp_rsz0_frame_done = <29>;
|
|
disp_rdma0_frame_done = <30>;
|
|
disp_wdma0_frame_done = <31>;
|
|
disp_color0_frame_done = <32>;
|
|
disp_ccorr0_frame_done = <33>;
|
|
disp_aal0_frame_done = <34>;
|
|
disp_gamma0_frame_done = <35>;
|
|
disp_dither0_frame_done = <36>;
|
|
disp_dsi0_frame_done = <37>;
|
|
stream_done_0 = <130>;
|
|
stream_done_1 = <131>;
|
|
stream_done_2 = <132>;
|
|
stream_done_3 = <133>;
|
|
stream_done_4 = <134>;
|
|
stream_done_5 = <135>;
|
|
stream_done_6 = <136>;
|
|
stream_done_7 = <137>;
|
|
stream_done_8 = <138>;
|
|
stream_done_9 = <139>;
|
|
buf_underrun_event_0 = <140>;
|
|
dsi0_te_event = <141>;
|
|
dsi0_irq_event = <142>;
|
|
dsi0_done_event = <143>;
|
|
disp_wdma0_rst_done = <147>;
|
|
mdp_wdma_rst_done = <148>;
|
|
mdp_wrot0_rst_done = <149>;
|
|
mdp_rdma0_rst_done = <151>;
|
|
disp_ovl0_frame_rst_done_pusle = <152>;
|
|
dip_cq_thread0_frame_done = <257>;
|
|
dip_cq_thread1_frame_done = <258>;
|
|
dip_cq_thread2_frame_done = <259>;
|
|
dip_cq_thread3_frame_done = <260>;
|
|
dip_cq_thread4_frame_done = <261>;
|
|
dip_cq_thread5_frame_done = <262>;
|
|
dip_cq_thread6_frame_done = <263>;
|
|
dip_cq_thread7_frame_done = <264>;
|
|
dip_cq_thread8_frame_done = <265>;
|
|
dip_cq_thread9_frame_done = <266>;
|
|
dip_cq_thread10_frame_done = <267>;
|
|
dip_cq_thread11_frame_done = <268>;
|
|
dip_cq_thread12_frame_done = <269>;
|
|
dip_cq_thread13_frame_done = <270>;
|
|
dip_cq_thread14_frame_done = <271>;
|
|
dip_cq_thread15_frame_done = <272>;
|
|
dip_cq_thread16_frame_done = <273>;
|
|
dip_cq_thread17_frame_done = <274>;
|
|
dip_cq_thread18_frame_done = <275>;
|
|
dve_frame_done = <276>;
|
|
wmf_frame_done = <277>;
|
|
rsc_frame_done = <278>;
|
|
venc_done = <289>;
|
|
jpgenc_done = <290>;
|
|
jpgdec_done = <291>;
|
|
venc_mb_done = <292>;
|
|
venc_128byte_cnt_done = <293>;
|
|
max_prefetch_cnt = <1>;
|
|
prefetch_size = <96>;
|
|
sram_size_cpr_64 = <64>;
|
|
mmsys_config = <&dispsys_config>;
|
|
mdp_rdma0 = <&mdp_rdma0>;
|
|
mdp_rsz0 = <&mdp_rsz0>;
|
|
mdp_rsz1 = <&mdp_rsz1>;
|
|
mdp_wdma0 = <&mdp_wdma0>;
|
|
mdp_wrot0 = <&mdp_wrot0>;
|
|
mdp_tdshp0 = <&mdp_tdshp0>;
|
|
mdp_color0 = <&disp_color0>;
|
|
mdp_ccorr0 = <&mdp_ccorr>;
|
|
mm_mutex = <&disp_mutex0>;
|
|
sram_share_cnt = <1>;
|
|
sram_share_engine = <10>;
|
|
sram_share_event = <710>;
|
|
clocks = <&infracfg_ao CLK_IFR_GCE>,
|
|
<&infracfg_ao CLK_IFR_GCE_26M>;
|
|
clock-names = "GCE", "GCE_TIMER";
|
|
mediatek,mailbox-gce = <&gce_mbox>;
|
|
mboxes = <&gce_mbox 0 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 1 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 2 0 CMDQ_THR_PRIO_5>,
|
|
<&gce_mbox 3 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 4 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 5 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 6 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox 7 CMDQ_NO_TIMEOUT CMDQ_THR_PRIO_2>,
|
|
#if defined(CONFIG_MTK_SEC_VIDEO_PATH_SUPPORT)
|
|
<&gce_mbox_svp 8 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox_svp 9 0 CMDQ_THR_PRIO_4>,
|
|
<&gce_mbox_svp 10 0 CMDQ_THR_PRIO_1>,
|
|
#else
|
|
<&gce_mbox 8 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 9 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 10 0 CMDQ_THR_PRIO_1>,
|
|
#endif
|
|
<&gce_mbox 11 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 12 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 13 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 14 0 CMDQ_THR_PRIO_1>,
|
|
<&gce_mbox 15 0 CMDQ_THR_PRIO_1>;
|
|
};
|
|
|
|
gce_mbox: gce_mbox@10238000 {
|
|
compatible = "mediatek,mt6761-gce";
|
|
reg = <0 0x10238000 0 0x4000>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_LOW>;
|
|
#mbox-cells = <3>;
|
|
#gce-event-cells = <1>;
|
|
#gce-subsys-cells = <2>;
|
|
default_tokens = /bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_0>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_1>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_2>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_3>,
|
|
/bits/ 16 <CMDQ_SYNC_TOKEN_GPR_SET_4>,
|
|
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT0>,
|
|
/bits/ 16 <CMDQ_SYNC_RESOURCE_WROT1>;
|
|
clocks = <&infracfg_ao CLK_IFR_GCE>,
|
|
<&infracfg_ao CLK_IFR_GCE_26M>;
|
|
clock-names = "gce", "gce-timer";
|
|
};
|
|
|
|
gce_mbox_svp: gce_mbox_svp@10238000 {
|
|
compatible = "mediatek,mailbox-gce-svp";
|
|
reg = <0 0x10238000 0 0x4000>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 155 IRQ_TYPE_LEVEL_LOW>;
|
|
#mbox-cells = <3>;
|
|
clocks = <&infracfg_ao CLK_IFR_GCE>,
|
|
<&infracfg_ao CLK_IFR_GCE_26M>;
|
|
clock-names = "gce", "GCE_TIMER";
|
|
};
|
|
|
|
ap_ccif2@1023c000 {
|
|
compatible = "mediatek,ap_ccif2";
|
|
reg = <0 0x1023c000 0 0x1000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
md_ccif2@1023d000 {
|
|
compatible = "mediatek,md_ccif2";
|
|
reg = <0 0x1023d000 0 0x1000>;
|
|
};
|
|
|
|
ap_ccif3@1023e000 {
|
|
compatible = "mediatek,ap_ccif3";
|
|
reg = <0 0x1023e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
md_ccif3@1023f000 {
|
|
compatible = "mediatek,md_ccif3";
|
|
reg = <0 0x1023f000 0 0x1000>;
|
|
};
|
|
|
|
sspm@10440000 {
|
|
compatible = "mediatek,mt6765-sspm";
|
|
reg = <0 0x10440000 0 0x10000>,
|
|
<0 0x10450000 0 0x100>,
|
|
<0 0x10451000 0 0x8>,
|
|
<0 0x10460000 0 0x100>,
|
|
<0 0x10461000 0 0x8>,
|
|
<0 0x10470000 0 0x100>,
|
|
<0 0x10471000 0 0x8>,
|
|
<0 0x10480000 0 0x100>,
|
|
<0 0x10481000 0 0x8>,
|
|
<0 0x10490000 0 0x100>,
|
|
<0 0x10491000 0 0x8>;
|
|
|
|
reg-names = "cfgreg",
|
|
"mbox0_base",
|
|
"mbox0_ctrl",
|
|
"mbox1_base",
|
|
"mbox1_ctrl",
|
|
"mbox2_base",
|
|
"mbox2_ctrl",
|
|
"mbox3_base",
|
|
"mbox3_ctrl",
|
|
"mbox4_base",
|
|
"mbox4_ctrl";
|
|
|
|
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "ipc",
|
|
"mbox0",
|
|
"mbox1",
|
|
"mbox2",
|
|
"mbox3",
|
|
"mbox4";
|
|
};
|
|
|
|
gic500@0c000000 {
|
|
compatible = "mediatek,gic500";
|
|
reg = <0 0x0c000000 0 0x1000>;
|
|
};
|
|
|
|
gic_cpu@0c400000 {
|
|
compatible = "mediatek,gic_cpu";
|
|
reg = <0 0x0c400000 0 0x40000>;
|
|
};
|
|
|
|
dfd@10200b00 {
|
|
compatible = "mediatek,dfd";
|
|
reg = <0 0x10200b00 0 0x10000>;
|
|
mediatek,enabled = <1>;
|
|
mediatek,chain_length = <0xc350>;
|
|
mediatek,rg_dfd_timeout = <0xa0>;
|
|
mediatek,check_dfd_support = <1>;
|
|
mediatek,dfd_infra_base = <0x390>;
|
|
mediatek,dfd_ap_addr_offset = <24>;
|
|
mediatek,dfd_latch_offset = <0x48>;
|
|
reg_base = <&toprgu>;
|
|
};
|
|
|
|
dbg_cti@0d020000 {
|
|
compatible = "mediatek,dbg_cti";
|
|
reg = <0 0x0d020000 0 0x10000>;
|
|
};
|
|
|
|
dbg_etr@0d030000 {
|
|
compatible = "mediatek,dbg_etr";
|
|
reg = <0 0x0d030000 0 0x10000>;
|
|
};
|
|
|
|
dbg_funnel@0d040000 {
|
|
compatible = "mediatek,dbg_funnel";
|
|
reg = <0 0x0d040000 0 0x10000>;
|
|
};
|
|
|
|
dbg_dem@0d0a0000 {
|
|
compatible = "mediatek,dbg_dem";
|
|
reg = <0 0x0d0a0000 0 0x10000>;
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
dbg_mdsys1@0d0c0000 {
|
|
compatible = "mediatek,dbg_mdsys1";
|
|
reg = <0 0x0d0c0000 0 0x40000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d400000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d400000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d410000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d410000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d420000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d420000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d430000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d430000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d440000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d440000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d510000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d510000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d520000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d520000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d530000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d530000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d540000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d540000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d610000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d610000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d620000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d620000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d630000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d630000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d640000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d640000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d710000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d710000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d720000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d720000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d730000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d730000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp0@0d740000 {
|
|
compatible = "mediatek,dbg_apmcu_mp0";
|
|
reg = <0 0x0d740000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0d800000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0d800000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0d810000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0d810000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0d820000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0d820000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0d830000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0d830000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0d840000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0d840000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0d910000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0d910000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0d920000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0d920000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0d930000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0d930000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0d940000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0d940000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0da10000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0da10000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0da20000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0da20000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0da30000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0da30000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0da40000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0da40000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0db10000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0db10000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0db20000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0db20000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0db30000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0db30000 0 0x1000>;
|
|
};
|
|
|
|
dbg_apmcu_mp1@0db40000 {
|
|
compatible = "mediatek,dbg_apmcu_mp1";
|
|
reg = <0 0x0db40000 0 0x1000>;
|
|
};
|
|
|
|
ap_dma@11000000 {
|
|
compatible = "mediatek,ap_dma";
|
|
reg = <0 0x11000000 0 0x1000>;
|
|
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
auxadc: auxadc@11001000 {
|
|
compatible = "mediatek,mt6765-auxadc";
|
|
reg = <0 0x11001000 0 0x1000>;
|
|
interrupts = <GIC_SPI 76 IRQ_TYPE_EDGE_FALLING>;
|
|
clocks = <&infracfg_ao CLK_IFR_AUXADC>;
|
|
clock-names = "main";
|
|
#io-channel-cells = <1>;
|
|
/* Auxadc efuse calibration */
|
|
/* 1. Auxadc cali on/off bit shift */
|
|
mediatek,cali-en-bit = <20>;
|
|
/* 2. Auxadc cali ge bits shift */
|
|
mediatek,cali-ge-bit = <10>;
|
|
/* 3. Auxadc cali oe bits shift */
|
|
mediatek,cali-oe-bit = <0>;
|
|
/* 4. Auxadc cali efuse reg offset */
|
|
mediatek,cali-efuse-reg-offset = <0x1A8>;
|
|
nvmem = <&efuse>;
|
|
nvmem-names = "mtk_efuse";
|
|
#interconnect-cells = <1>;
|
|
};
|
|
|
|
apdma: dma-controller@11000580 {
|
|
compatible = "mediatek,mt6577-uart-dma";
|
|
reg = <0 0x11000680 0 0x80>,
|
|
<0 0x11000700 0 0x80>,
|
|
<0 0x11000780 0 0x80>,
|
|
<0 0x11000800 0 0x80>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
|
|
<GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>;
|
|
dma-requests = <4>;
|
|
clocks = <&infracfg_ao CLK_IFR_AP_DMA>;
|
|
clock-names = "apdma";
|
|
#dma-cells = <1>;
|
|
};
|
|
|
|
uart0: serial@11020000 {
|
|
compatible = "mediatek,mt6758-uart",
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11002000 0 0x1000>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&clk26m>, <&infracfg_ao CLK_IFR_UART0>;
|
|
clock-names = "baud", "bus";
|
|
dmas = <&apdma 0
|
|
&apdma 1>;
|
|
dma-names = "tx", "rx";
|
|
};
|
|
|
|
uart1: serial@11030000 {
|
|
compatible = "mediatek,mt6758-uart",
|
|
"mediatek,mt6577-uart";
|
|
reg = <0 0x11003000 0 0x1000>;
|
|
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&clk26m>, <&infracfg_ao CLK_IFR_UART1>;
|
|
clock-names = "baud", "bus";
|
|
};
|
|
|
|
i2c_common: i2c_common {
|
|
compatible = "mediatek,i2c_common";
|
|
dma_support = /bits/ 8 <2>;
|
|
idvfs = /bits/ 8 <1>;
|
|
set_dt_div = /bits/ 8 <1>;
|
|
check_max_freq = /bits/ 8 <1>;
|
|
ver = /bits/ 8 <2>;
|
|
set_ltiming = /bits/ 8 <1>;
|
|
ext_time_config = /bits/ 16 <0x1801>;
|
|
cnt_constraint = /bits/ 8 <1>;
|
|
};
|
|
i2c0: i2c0@11007000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <0>;
|
|
reg = <0 0x11007000 0 0x1000>,
|
|
<0 0x11000080 0 0x80>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
|
|
<&infracfg_ao CLK_IFR_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <83>;
|
|
sda-gpio-id = <82>;
|
|
gpio_start = <0x10002a00>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x20>;
|
|
pu_cfg = <0x50>;
|
|
rsel_cfg = <0x70>;
|
|
aed = <0x1a>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
i2c1: i2c1@11008000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <1>;
|
|
reg = <0 0x11008000 0 0x1000>,
|
|
<0 0x11000100 0 0x80>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
|
|
<&infracfg_ao CLK_IFR_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <84>;
|
|
sda-gpio-id = <81>;
|
|
gpio_start = <0x10002a00>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x20>;
|
|
pu_cfg = <0x50>;
|
|
rsel_cfg = <0x70>;
|
|
aed = <0x1a>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
i2c2: i2c2@11009000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <2>;
|
|
reg = <0 0x11009000 0 0x1000>,
|
|
<0 0x11000180 0 0x180>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
|
|
<&infracfg_ao CLK_IFR_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <103>;
|
|
sda-gpio-id = <104>;
|
|
gpio_start = <0x10002800>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x20>;
|
|
pu_cfg = <0x60>;
|
|
rsel_cfg = <0xa0>;
|
|
aed = <0x1a>;
|
|
ch_offset_default = <0x100>;
|
|
ch_offset_ccu = <0x200>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
i2c3: i2c3@1100f000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <3>;
|
|
reg = <0 0x1100f000 0 0x1000>,
|
|
<0 0x11000300 0 0x100>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
|
|
<&infracfg_ao CLK_IFR_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <50>;
|
|
sda-gpio-id = <51>;
|
|
gpio_start = <0x10002600>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x20>;
|
|
pu_cfg = <0x90>;
|
|
rsel_cfg = <0xb0>;
|
|
aed = <0x1a>;
|
|
ch_offset_default = <0x100>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
i2c4: i2c4@11011000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <4>;
|
|
reg = <0 0x11011000 0 0x1000>,
|
|
<0 0x11000400 0 0x180>;
|
|
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
|
|
<&infracfg_ao CLK_IFR_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <105>;
|
|
sda-gpio-id = <106>;
|
|
gpio_start = <0x10002800>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x20>;
|
|
pu_cfg = <0x60>;
|
|
rsel_cfg = <0xa0>;
|
|
aed = <0x1a>;
|
|
ch_offset_default = <0x100>;
|
|
ch_offset_ccu = <0x200>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
i2c5: i2c5@11016000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <5>;
|
|
reg = <0 0x11016000 0 0x1000>,
|
|
<0 0x11000580 0 0x80>;
|
|
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
|
|
<&infracfg_ao CLK_IFR_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <48>;
|
|
sda-gpio-id = <49>;
|
|
gpio_start = <0x10002600>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x20>;
|
|
pu_cfg = <0x90>;
|
|
rsel_cfg = <0xb0>;
|
|
aed = <0x1a>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
i2c6: i2c6@1100d000 {
|
|
compatible = "mediatek,i2c";
|
|
id = <6>;
|
|
reg = <0 0x1100d000 0 0x1000>,
|
|
<0 0x11000600 0 0x80>;
|
|
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_IFR_I2C_AP>,
|
|
<&infracfg_ao CLK_IFR_AP_DMA>;
|
|
clock-names = "main", "dma";
|
|
clock-div = <5>;
|
|
scl-gpio-id = <161>;
|
|
sda-gpio-id = <162>;
|
|
gpio_start = <0x10002c00>;
|
|
mem_len = <0x200>;
|
|
eh_cfg = <0x20>;
|
|
pu_cfg = <0x50>;
|
|
rsel_cfg = <0x70>;
|
|
aed = <0x1a>;
|
|
ch_offset_default = <0x100>;
|
|
ch_offset_ccu = <0x200>;
|
|
mediatek,hs_only;
|
|
};
|
|
|
|
|
|
pwm: pwm@11006000 {
|
|
compatible = "mediatek,pwm";
|
|
reg = <0 0x11006000 0 0x10000>;
|
|
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_IFR_PWM1>,
|
|
<&infracfg_ao CLK_IFR_PWM2>,
|
|
<&infracfg_ao CLK_IFR_PWM3>,
|
|
<&infracfg_ao CLK_IFR_PWM4>,
|
|
<&infracfg_ao CLK_IFR_PWM5>,
|
|
<&infracfg_ao CLK_IFR_RG_PWM_FBCLK6>,
|
|
<&infracfg_ao CLK_IFR_PWM_HCLK>,
|
|
<&infracfg_ao CLK_IFR_PWM>;
|
|
clock-names = "PWM1-main", "PWM2-main",
|
|
"PWM3-main", "PWM4-main",
|
|
"PWM5-main", "PWM6-main",
|
|
"PWM-HCLK-main", "PWM-main";
|
|
};
|
|
|
|
spi0: spi@1100a000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x1100a000 0 0x1000>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
|
|
<&topckgen CLK_TOP_SPI_SEL>,
|
|
<&infracfg_ao CLK_IFR_SPI0>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
|
|
therm_ctrl@1100b000 {
|
|
compatible = "mediatek,therm_ctrl";
|
|
reg = <0 0x1100b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_IFR_THERM>;
|
|
clock-names = "therm-main";
|
|
nvmem = <&efuse>;
|
|
nvmem-names = "mtk_efuse";
|
|
nvmem-cells = <&cpu_freq_segment>,
|
|
<&thermal_efuse>;
|
|
nvmem-cell-names = "cpu_freq_segment_cell",
|
|
"thermal_efuse_cell";
|
|
};
|
|
|
|
tboard_thermistor1: thermal-sensor1 {
|
|
compatible = "mediatek,mtboard-thermistor1";
|
|
io-channels = <&auxadc 0>;
|
|
io-channel-names = "thermistor-ch0";
|
|
interconnects = <&auxadc 0>;
|
|
};
|
|
|
|
tboard_thermistor2: thermal-sensor2 {
|
|
compatible = "mediatek,mtboard-thermistor2";
|
|
io-channels = <&auxadc 1>;
|
|
io-channel-names = "thermistor-ch1";
|
|
interconnects = <&auxadc 1>;
|
|
};
|
|
btif@1100c000 {
|
|
compatible = "mediatek,btif";
|
|
/*btif base*/
|
|
reg = <0 0x1100c000 0 0x1000>,
|
|
/*btif tx dma base*/
|
|
<0 0x11000880 0 0x80>,
|
|
/*btif rx dma base*/
|
|
<0 0x11000900 0 0x80>;
|
|
/*btif irq*/
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
|
|
/*btif tx dma irq*/
|
|
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>,
|
|
/*btif rx dma irq*/
|
|
<GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&infracfg_ao CLK_IFR_BTIF>,
|
|
/*btif clock*/
|
|
<&infracfg_ao CLK_IFR_AP_DMA>;
|
|
/*ap dma clock*/
|
|
clock-names = "btifc","apdmac";
|
|
};
|
|
|
|
consys: consys@18002000 {
|
|
compatible = "mediatek,mt6765-consys";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
/*CONN_MCU_CONFIG_BASE */
|
|
reg = <0 0x18002000 0 0x1000>,
|
|
/*TOP_RGU_BASE */
|
|
<0 0x10007000 0 0x0100>,
|
|
/*INFRACFG_AO_BASE */
|
|
<0 0x10001000 0 0x1000>,
|
|
/*SPM_BASE */
|
|
<0 0x10006000 0 0x1000>,
|
|
/*CONN_HIF_ON_BASE */
|
|
<0 0x18007000 0 0x1000>,
|
|
/*CONN_TOP_MISC_OFF_BASE */
|
|
<0 0x180b1000 0 0x1000>,
|
|
/*CONN_MCU_CFG_ON_BASE */
|
|
<0 0x180a3000 0 0x1000>,
|
|
/*CONN_MCU_CIRQ_BASE */
|
|
<0 0x180a5000 0 0x800>,
|
|
/*CONN_TOP_MISC_ON_BASE */
|
|
<0 0x180c1000 0 0x1000>,
|
|
/*CONN_HIF_PDMA_BASE */
|
|
<0 0x18004000 0 0x1000>,
|
|
/* Add for index sync */
|
|
<0 0x00000000 0 0x0000>,
|
|
<0 0x00000000 0 0x0000>,
|
|
/* INFRACFG_REG_BASE */
|
|
<0 0x1020e000 0 0x1000>;
|
|
/*BGF_EINT */
|
|
interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_LOW>,
|
|
/*WDT_EINT */
|
|
<GIC_SPI 269 IRQ_TYPE_LEVEL_LOW>,
|
|
/*conn2ap_sw_irq*/
|
|
<GIC_SPI 270 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&scpsys SCP_SYS_CONN>;
|
|
clock-names = "conn";
|
|
pmic = <&main_pmic>;
|
|
memory-region = <&consys_mem>;
|
|
};
|
|
|
|
wifi@18000000 {
|
|
compatible = "mediatek,wifi";
|
|
reg = <0 0x18000000 0 0x100000>;
|
|
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_LOW>;
|
|
memory-region = <&wifi_mem>;
|
|
};
|
|
|
|
disp_pwm@1100e000 {
|
|
compatible = "mediatek,disp_pwm";
|
|
reg = <0 0x1100e000 0 0x1000>;
|
|
};
|
|
|
|
spi1: spi@11010000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11010000 0 0x1000>;
|
|
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
|
|
<&topckgen CLK_TOP_SPI_SEL>,
|
|
<&infracfg_ao CLK_IFR_SPI1>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi2: spi@11012000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11012000 0 0x1000>;
|
|
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
|
|
<&topckgen CLK_TOP_SPI_SEL>,
|
|
<&infracfg_ao CLK_IFR_SPI2>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi3: spi@11013000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11013000 0 0x1000>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
|
|
<&topckgen CLK_TOP_SPI_SEL>,
|
|
<&infracfg_ao CLK_IFR_SPI3>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi4: spi@11014000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11014000 0 0x1000>;
|
|
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
|
|
<&topckgen CLK_TOP_SPI_SEL>,
|
|
<&infracfg_ao CLK_IFR_SPI4>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
spi5: spi@11015000 {
|
|
compatible = "mediatek,mt6765-spi";
|
|
mediatek,pad-select = <0>;
|
|
reg = <0 0x11015000 0 0x1000>;
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
|
|
<&topckgen CLK_TOP_SPI_SEL>,
|
|
<&infracfg_ao CLK_IFR_SPI5>;
|
|
clock-names = "parent-clk", "sel-clk", "spi-clk";
|
|
};
|
|
|
|
imp_iic@11017000 {
|
|
compatible = "mediatek,imp_iic";
|
|
reg = <0 0x11017000 0 0x1000>;
|
|
};
|
|
|
|
nfi@11018000 {
|
|
compatible = "mediatek,nfi";
|
|
reg = <0 0x11018000 0 0x1000>;
|
|
};
|
|
|
|
nfiecc@11019000 {
|
|
compatible = "mediatek,nfiecc";
|
|
reg = <0 0x11019000 0 0x1000>;
|
|
};
|
|
|
|
usb: usb0@11200000 {
|
|
compatible = "mediatek,mt6765-usb20";
|
|
reg = <0 0x11200000 0 0x10000>,
|
|
<0 0x11CC0000 0 0x10000>;
|
|
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>;
|
|
mode = <2>;
|
|
multipoint = <1>;
|
|
num_eps = <16>;
|
|
clocks = <&infracfg_ao CLK_IFR_ICUSB>,
|
|
<&topckgen CLK_TOP_USB_TOP_SEL>,
|
|
<&topckgen CLK_TOP_UNIVPLL3_D4>;
|
|
clock-names = "usb0",
|
|
"usb0_clk_top_sel",
|
|
"usb0_clk_univpll3_d4";
|
|
pericfg= <&pericfg>;
|
|
interrupt-names = "mc";
|
|
phys = <&u2port0 PHY_TYPE_USB2>;
|
|
dr_mode = "otg";
|
|
usb-role-switch;
|
|
};
|
|
|
|
u2phy0: usb-phy@11210000 {
|
|
compatible = "mediatek,generic-tphy-v1";
|
|
reg = <0 0x11cc0000 0 0x0800>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
status = "okay";
|
|
u2port0: usb-phy@11210000 {
|
|
reg = <0 0x11cc0800 0 0x100>;
|
|
clocks = <&clk26m>;
|
|
clock-names = "ref";
|
|
#phy-cells = <1>;
|
|
nvmem-cells = <&u2_phy_data>;
|
|
nvmem-cell-names = "intr_cal";
|
|
nvmem-cell-masks = <0x1f>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
msdc0:msdc@11230000 {
|
|
compatible = "mediatek,msdc";
|
|
reg = <0 0x11230000 0 0x10000>;
|
|
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
msdc1:msdc@11240000 {
|
|
compatible = "mediatek,msdc";
|
|
reg = <0 0x11240000 0 0x10000>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
msdc2:msdc@11250000 {
|
|
compatible = "mediatek,msdc2";
|
|
reg = <0 0x11250000 0 0x10000>;
|
|
};
|
|
|
|
msdc3:msdc@11260000 {
|
|
compatible = "mediatek,msdc3";
|
|
reg = <0 0x11250000 0 0x10000>;
|
|
};
|
|
|
|
msdc1_ins:msdc1_ins@0 {
|
|
compatible = "mediatek,mt6765-sdcard-ins";
|
|
};
|
|
|
|
msdc0_top@11cd0000 {
|
|
compatible = "mediatek,msdc0_top";
|
|
reg = <0 0x11cd0000 0 0x1000>;
|
|
};
|
|
|
|
msdc1_top@11c90000 {
|
|
compatible = "mediatek,msdc1_top";
|
|
reg = <0 0x11c90000 0 0x1000>;
|
|
};
|
|
usb1p_sif@11210000 {
|
|
compatible = "mediatek,usb1p_sif";
|
|
reg = <0 0x11210000 0 0x10000>;
|
|
};
|
|
|
|
audclk: audclk@11220000 {
|
|
compatible = "mediatek,mt6765-audsys", "syscon";
|
|
reg = <0 0x11220000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
audio: audio@11220000 {
|
|
compatible = "mediatek,audio", "syscon";
|
|
reg = <0 0x11220000 0 0x1000>;
|
|
/* interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>; */
|
|
mediatek,btcvsd_snd = <&btcvsd_snd>;
|
|
};
|
|
|
|
audgpio: mt_soc_dl1_pcm@11220000 {
|
|
compatible = "mediatek,mt_soc_pcm_dl1";
|
|
reg = <0 0x11220000 0 0x1000>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&audclk CLK_AUDIO_AFE>,
|
|
<&audclk CLK_AUDIO_DAC>,
|
|
<&audclk CLK_AUDIO_DAC_PREDIS>,
|
|
<&audclk CLK_AUDIO_ADC>,
|
|
<&audclk CLK_AUDIO_22M>,
|
|
<&audclk CLK_AUDIO_APLL_TUNER>,
|
|
<&audclk CLK_AUDIO_TML>,
|
|
<&infracfg_ao CLK_IFR_AUDIO>,
|
|
<&infracfg_ao CLK_IFR_AUDIO_26M_BCLK>,
|
|
<&topckgen CLK_TOP_AUDIO_SEL>,
|
|
<&topckgen CLK_TOP_AUD_INTBUS_SEL>,
|
|
<&topckgen CLK_TOP_SYSPLL1_D4>,
|
|
<&topckgen CLK_TOP_AUD_1_SEL>,
|
|
<&topckgen CLK_TOP_APLL1>,
|
|
<&topckgen CLK_TOP_AUD_ENGEN1_SEL>,
|
|
<&topckgen CLK_TOP_APLL1_D8>,
|
|
<&apmixed CLK_APMIXED_APLL1>,
|
|
<&clk26m>;
|
|
clock-names = "aud_afe_clk",
|
|
"aud_dac_clk",
|
|
"aud_dac_predis_clk",
|
|
"aud_adc_clk",
|
|
"aud_apll22m_clk",
|
|
"aud_apll1_tuner_clk",
|
|
"aud_tml_clk",
|
|
"aud_infra_clk",
|
|
"mtkaif_26m_clk",
|
|
"top_mux_audio",
|
|
"top_mux_audio_int",
|
|
"top_sys_pll1_d4",
|
|
"top_mux_aud_1",
|
|
"top_apll1_ck",
|
|
"top_mux_aud_eng1",
|
|
"top_apll1_d8",
|
|
"apmixed_apll1",
|
|
"top_clk26m_clk";
|
|
};
|
|
|
|
audio_sram@11221000 {
|
|
compatible = "mediatek,audio_sram";
|
|
reg = <0 0x11221000 0 0x9000>;
|
|
};
|
|
|
|
btcvsd_snd: mtk-btcvsd-snd@18050000 {
|
|
compatible = "mediatek,mtk-btcvsd-snd";
|
|
reg=<0 0x18050000 0 0x1000>, /*PKV_PHYSICAL_BASE*/
|
|
<0 0x18080000 0 0x10000>; /*SRAM_BANK2*/
|
|
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_LOW>;
|
|
mediatek,infracfg = <&infracfg_ao>;
|
|
mediatek,offset =<0xf00 0x800 0x140 0x144 0x148>;
|
|
/*INFRA MISC, conn_bt_cvsd_mask*/
|
|
/*cvsd_mcu_read, write, packet_indicator*/
|
|
};
|
|
|
|
mipi_rx_ana_csi0a: mipi_rx_ana_csi0a@11c10000 {
|
|
compatible = "mediatek,mt6765-mipi0a", "syscon";
|
|
reg = <0 0x11c10000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mipi_rx_ana_csi0b: mipi_rx_ana_csi0b@11c11000 {
|
|
compatible = "mediatek,mt6765-mipi0b", "syscon";
|
|
reg = <0 0x11c11000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mipi_rx_ana_csi1a: mipi_rx_ana_csi1a@11c12000 {
|
|
compatible = "mediatek,mt6765-mipi1a", "syscon";
|
|
reg = <0 0x11c12000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mipi_rx_ana_csi1b: mipi_rx_ana_csi1b@11c13000 {
|
|
compatible = "mediatek,mt6765-mipi1b", "syscon";
|
|
reg = <0 0x11c13000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mipi_rx_ana_csi2a: mipi_rx_ana_csi2a@11c14000 {
|
|
compatible = "mediatek,mt6765-mipi2a", "syscon";
|
|
reg = <0 0x11c14000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mipi_rx_ana_csi2b: mipi_rx_ana_csi2b@11c15000 {
|
|
compatible = "mediatek,mt6765-mipi2b", "syscon";
|
|
reg = <0 0x11c15000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
efuse: efuse@11c50000 {
|
|
compatible = "mediatek,devinfo";
|
|
reg = <0 0x11c50000 0 0x10000>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
efuse_segment: segment@78 {
|
|
reg = <0x78 0x4>;
|
|
};
|
|
cpu_freq_segment: segment@1c {
|
|
reg = <0x1c 0x4>;
|
|
};
|
|
thermal_efuse: segment@190 {
|
|
reg = <0x190 0xc>;
|
|
};
|
|
u2_phy_data: u2_phy_data@1ac {
|
|
reg = <0x1ac 0x4>;
|
|
};
|
|
efuse_ly: ly@210 {
|
|
reg = <0x210 0x4>;
|
|
};
|
|
};
|
|
|
|
mipi_tx0@11c80000 {
|
|
compatible = "mediatek,mipi_tx0";
|
|
reg = <0 0x11c80000 0 0x10000>;
|
|
};
|
|
|
|
msdc1_pad_macro@11c90000 {
|
|
compatible = "mediatek,msdc1_pad_macro";
|
|
reg = <0 0x11c90000 0 0x10000>;
|
|
};
|
|
|
|
msdc0_pad_macro@11cd0000 {
|
|
compatible = "mediatek,msdc0_pad_macro";
|
|
reg = <0 0x11cd0000 0 0x10000>;
|
|
};
|
|
|
|
mfg_doma: mfg_doma@13000000 {
|
|
compatible = "mediatek,doma";
|
|
reg = <0 0x13000000 0 0x80000>;
|
|
interrupts = <GIC_SPI 259 IRQ_TYPE_LEVEL_LOW>;
|
|
interrupt-names = "RGX";
|
|
clock-frequency = <570000000>;
|
|
ged-supply = <&ged>;
|
|
};
|
|
|
|
mfg_cfg: mfg_cfg@13ffe000 {
|
|
compatible = "mediatek,mfgcfg", "syscon";
|
|
reg = <0 0x13ffe000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
gpufreq: gpufreq {
|
|
compatible = "mediatek,mt6765-gpufreq";
|
|
clocks =
|
|
<&topckgen CLK_TOP_MFG_SEL>,
|
|
<&topckgen CLK_TOP_MFGPLL>,
|
|
<&clk26m>,
|
|
<&scpsys SCP_SYS_MFG_ASYNC>,
|
|
<&scpsys SCP_SYS_MFG>,
|
|
<&scpsys SCP_SYS_MFG_CORE0>;
|
|
clock-names =
|
|
"clk_mux",
|
|
"clk_main_parent",
|
|
"clk_sub_parent",
|
|
"mtcmos_mfg_async",
|
|
"mtcmos_mfg",
|
|
"mtcmos_mfg_core0";
|
|
nvmem-cells = <&efuse_segment>;
|
|
nvmem-cell-names = "efuse_segment_cell";
|
|
vcore-supply = <&mt_pmic_vcore_buck_reg>;
|
|
};
|
|
|
|
ged: ged {
|
|
compatible = "mediatek,ged";
|
|
gpufreq-supply = <&gpufreq>;
|
|
};
|
|
|
|
mmsys_config: mmsys_config@14000000 {
|
|
compatible = "mediatek,mt6765-mmsys_config", "syscon";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
dispsys_config: dispsys_config@14000000 {
|
|
compatible = "mediatek,mmsys_config", "syscon";
|
|
reg = <0 0x14000000 0 0x1000>;
|
|
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys_config CLK_MM_CAM_MDP>,
|
|
<&mmsys_config CLK_MM_IMG_DL_RELAY>,
|
|
<&mmsys_config CLK_MM_IMG_DL_ASYNC_TOP>;
|
|
clock-names = "CAM_MDP", "IMG_DL_RELAY", "IMG_DL_ASYNC_TOP";
|
|
};
|
|
|
|
nfc:nfc {
|
|
compatible = "mediatek,nfc-gpio-v2";
|
|
gpio-rst = <172>;
|
|
gpio-rst-std = <&pio 172 0x0>;
|
|
gpio-irq = <10>;
|
|
gpio-irq-std = <&pio 10 0x0>;
|
|
};
|
|
|
|
irq_nfc: irq_nfc {
|
|
compatible = "mediatek,irq_nfc-eint";
|
|
};
|
|
|
|
disp_mutex0: disp_mutex0@14001000 {
|
|
compatible = "mediatek,disp_mutex0";
|
|
reg = <0 0x14001000 0 0x1000>;
|
|
interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
smi_common: smi_common@14002000 {
|
|
compatible = "mediatek,smi_common";
|
|
reg = <0 0x14002000 0 0x1000>;
|
|
mmsys_config = <&dispsys_config>;
|
|
clocks = <&scpsys SCP_SYS_DIS>,
|
|
<&mmsys_config CLK_MM_SMI_COMM0>,
|
|
<&mmsys_config CLK_MM_SMI_COMM1>,
|
|
<&mmsys_config CLK_MM_SMI_COMMON>,
|
|
<&topckgen CLK_TOP_MM_SEL>,
|
|
<&topckgen CLK_TOP_MMPLL>,
|
|
<&topckgen CLK_TOP_UNIVPLL1_D2>,
|
|
<&topckgen CLK_TOP_MMPLL_D2>;
|
|
clock-names = "mtcmos-mm", "smi-common-gals-comm0",
|
|
"smi-common-gals-comm1", "smi-common",
|
|
"mmdvfs_clk_mm_sel_ck",
|
|
"mmdvfs_clk_mmpll_ck", "mmdvfs_clk_univpll1_d2_ck",
|
|
"mmdvfs_clk_mmpll_d2_ck";
|
|
mediatek,smi-id = <4>;
|
|
mediatek,smi-cnt = <5>;
|
|
};
|
|
|
|
mmdvfs_pmqos {
|
|
compatible = "mediatek,mmdvfs_pmqos";
|
|
mm_step0 = <457 1 0 1>;
|
|
mm_step1 = <312 1 0 2>;
|
|
mm_step2 = <228 1 0 3>;
|
|
vopp_steps = <0 1 3>;
|
|
disp_freq = "mm_step0", "mm_step1", "mm_step2";
|
|
mdp_freq = "mm_step0", "mm_step1", "mm_step2";
|
|
cam_freq = "mm_step0","mm_step1","mm_step2";
|
|
img_freq = "mm_step0","mm_step1","mm_step2";
|
|
vdec_freq = "mm_step0","mm_step1","mm_step2";
|
|
venc_freq = "mm_step0","mm_step1","mm_step2";
|
|
clocks = <&topckgen CLK_TOP_MM_SEL>, /* 0 */
|
|
<&topckgen CLK_TOP_MMPLL>, /* 1 */
|
|
<&topckgen CLK_TOP_UNIVPLL1_D2>, /* 2 */
|
|
<&topckgen CLK_TOP_MMPLL_D2>; /* 3 */
|
|
clock-names = "mmdvfs_clk_mm_sel_ck", /* 0 */
|
|
"mmdvfs_clk_mmpll_ck", /* 1 */
|
|
"mmdvfs_clk_univpll1_d2_ck", /* 2 */
|
|
"mmdvfs_clk_mmpll_d2_ck"; /* 3 */
|
|
};
|
|
|
|
imgsys: imgsys_clk@15020000 {
|
|
compatible = "mediatek,mt6765-imgsys", "syscon";
|
|
reg = <0 0x15020000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
imgsys@15020000 {
|
|
compatible = "mediatek,imgsys", "syscon";
|
|
reg = <0 0x15020000 0 0x1000>;
|
|
/* Camera CCF */
|
|
clocks = <&scpsys SCP_SYS_DIS>,
|
|
<&scpsys SCP_SYS_ISP>,
|
|
<&scpsys SCP_SYS_CAM>,
|
|
<&imgsys CLK_IMG_DIP>,
|
|
<&camsys CLK_CAM>,
|
|
<&camsys CLK_CAMTG>,
|
|
<&camsys CLK_CAM_SENINF>,
|
|
<&camsys CLK_CAMSV0>,
|
|
<&camsys CLK_CAMSV1>,
|
|
<&camsys CLK_CAMSV2>;
|
|
clock-names = "ISP_SCP_SYS_DIS",
|
|
"ISP_SCP_SYS_ISP",
|
|
"ISP_SCP_SYS_CAM",
|
|
"ISP_CLK_IMG_DIP",
|
|
"ISP_CLK_CAM",
|
|
"ISP_CLK_CAMTG",
|
|
"ISP_CLK_CAM_SENINF",
|
|
"ISP_CLK_CAMSV0",
|
|
"ISP_CLK_CAMSV1",
|
|
"ISP_CLK_CAMSV2";
|
|
};
|
|
|
|
dip1@15022000 {
|
|
compatible = "mediatek,dip1";
|
|
reg = <0 0x15022000 0 0x3000>;
|
|
interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
dpe@15028000 {
|
|
compatible = "mediatek,dpe";
|
|
reg = <0 0x15028000 0 0x1000>;
|
|
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&imgsys CLK_IMG_DPE>;
|
|
clock-names = "DPE_CG_IMG_DPE";
|
|
};
|
|
|
|
smi_larb0: smi_larb0@14003000 {
|
|
cell-index = <0>;
|
|
compatible = "mediatek,smi_larb0", "mediatek,smi_larb";
|
|
reg = <0 0x14003000 0 0x1000>;
|
|
mediatek,larb-id = <0>;
|
|
clocks = <&scpsys SCP_SYS_DIS>,
|
|
<&mmsys_config CLK_MM_SMI_LARB0>;
|
|
clock-names = "mtcmos-mm", "mm-larb0";
|
|
mediatek,smi-id = <0>;
|
|
};
|
|
|
|
mdp_rdma0: mdp_rdma0@14004000 {
|
|
compatible = "mediatek,mdp_rdma0";
|
|
reg = <0 0x14004000 0 0x1000>;
|
|
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys_config CLK_MM_MDP_RDMA0>;
|
|
clock-names = "MDP_RDMA0";
|
|
};
|
|
|
|
mdp_ccorr: mdp_ccorr0@14005000 {
|
|
compatible = "mediatek,mdp_ccorr0";
|
|
reg = <0 0x14005000 0 0x1000>;
|
|
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys_config CLK_MM_MDP_CCORR0>;
|
|
clock-names = "MDP_CCORR";
|
|
};
|
|
|
|
mdp_rsz0: mdp_rsz0@14006000 {
|
|
compatible = "mediatek,mdp_rsz0";
|
|
reg = <0 0x14006000 0 0x1000>;
|
|
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys_config CLK_MM_MDP_RSZ0>;
|
|
clock-names = "MDP_RSZ0";
|
|
};
|
|
|
|
mdp_rsz1: mdp_rsz1@14007000 {
|
|
compatible = "mediatek,mdp_rsz1";
|
|
reg = <0 0x14007000 0 0x1000>;
|
|
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys_config CLK_MM_MDP_RSZ1>;
|
|
clock-names = "MDP_RSZ1";
|
|
};
|
|
|
|
mdp_wdma0: mdp_wdma0@14008000 {
|
|
compatible = "mediatek,mdp_wdma0";
|
|
reg = <0 0x14008000 0 0x1000>;
|
|
interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys_config CLK_MM_MDP_WDMA0>;
|
|
clock-names = "MDP_WDMA";
|
|
};
|
|
|
|
mdp_wrot0: mdp_wrot0@14009000 {
|
|
compatible = "mediatek,mdp_wrot0";
|
|
reg = <0 0x14009000 0 0x1000>;
|
|
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys_config CLK_MM_MDP_WROT0>;
|
|
clock-names = "MDP_WROT0";
|
|
};
|
|
|
|
mdp_tdshp0: mdp_tdshp0@1400a000 {
|
|
compatible = "mediatek,mdp_tdshp0";
|
|
reg = <0 0x1400a000 0 0x1000>;
|
|
clocks = <&mmsys_config CLK_MM_MDP_TDSHP0>;
|
|
clock-names = "MDP_TDSHP";
|
|
};
|
|
|
|
disp_ovl0@1400b000 {
|
|
compatible = "mediatek,disp_ovl0";
|
|
reg = <0 0x1400b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_ovl0_2l@1400c000 {
|
|
compatible = "mediatek,disp_ovl0_2l";
|
|
reg = <0 0x1400c000 0 0x1000>;
|
|
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_rdma0@1400d000 {
|
|
compatible = "mediatek,disp_rdma0";
|
|
reg = <0 0x1400d000 0 0x1000>;
|
|
interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_wdma0@1400e000 {
|
|
compatible = "mediatek,disp_wdma0";
|
|
reg = <0 0x1400e000 0 0x1000>;
|
|
interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_color0: disp_color0@1400f000 {
|
|
compatible = "mediatek,disp_color0";
|
|
reg = <0 0x1400f000 0 0x1000>;
|
|
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&mmsys_config CLK_MM_DISP_COLOR0>;
|
|
clock-names = "MDP_COLOR";
|
|
};
|
|
|
|
disp_ccorr0@14010000 {
|
|
compatible = "mediatek,disp_ccorr0";
|
|
reg = <0 0x14010000 0 0x1000>;
|
|
interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_aal0@14011000 {
|
|
compatible = "mediatek,disp_aal0";
|
|
reg = <0 0x14011000 0 0x1000>;
|
|
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_gamma0@14012000 {
|
|
compatible = "mediatek,disp_gamma0";
|
|
reg = <0 0x14012000 0 0x1000>;
|
|
interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_dither0@14013000 {
|
|
compatible = "mediatek,disp_dither0";
|
|
reg = <0 0x14013000 0 0x1000>;
|
|
interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
dsi0@14014000 {
|
|
compatible = "mediatek,dsi0";
|
|
reg = <0 0x14014000 0 0x1000>;
|
|
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
disp_rsz0@14015000 {
|
|
compatible = "mediatek,disp_rsz0";
|
|
reg = <0 0x14015000 0 0x1000>;
|
|
interrupts = <GIC_SPI 276 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
mtkfb: mtkfb@0 {
|
|
compatible = "mediatek,mtkfb";
|
|
};
|
|
|
|
dispsys {
|
|
compatible = "mediatek,dispsys";
|
|
|
|
clocks = <&scpsys SCP_SYS_DIS>,
|
|
<&mmsys_config CLK_MM_SMI_COMMON>,
|
|
<&mmsys_config CLK_MM_SMI_LARB0>,
|
|
<&mmsys_config CLK_MM_SMI_COMM0>,
|
|
<&mmsys_config CLK_MM_SMI_COMM1>,
|
|
<&mmsys_config CLK_MM_DISP_OVL0>,
|
|
<&mmsys_config CLK_MM_DISP_OVL0_2L>,
|
|
<&mmsys_config CLK_MM_DISP_RDMA0>,
|
|
<&mmsys_config CLK_MM_DISP_WDMA0>,
|
|
<&mmsys_config CLK_MM_DISP_COLOR0>,
|
|
<&mmsys_config CLK_MM_DISP_CCORR0>,
|
|
<&mmsys_config CLK_MM_DISP_AAL0>,
|
|
<&mmsys_config CLK_MM_DISP_GAMMA0>,
|
|
<&mmsys_config CLK_MM_DISP_DITHER0>,
|
|
<&mmsys_config CLK_MM_DSI0>,
|
|
<&mmsys_config CLK_MM_DIG_DSI>,
|
|
<&mmsys_config CLK_MM_F26M_HRTWT>,
|
|
<&mmsys_config CLK_MM_DISP_RSZ0>,
|
|
<&apmixed CLK_APMIXED_MIPID0_26M>,
|
|
<&topckgen CLK_TOP_DISP_PWM_SEL>,
|
|
<&infracfg_ao CLK_IFR_DISP_PWM>,
|
|
<&clk26m>,
|
|
<&topckgen CLK_TOP_UNIVPLL2_D4>,
|
|
<&topckgen CLK_TOP_ULPOSC1_D2>,
|
|
<&topckgen CLK_TOP_ULPOSC1_D8>;
|
|
|
|
clock-names = "MMSYS_MTCMOS",
|
|
"MMSYS_SMI_COMMON",
|
|
"MMSYS_SMI_LARB0",
|
|
"MMSYS_GALS_COMM0",
|
|
"MMSYS_GALS_COMM1",
|
|
"MMSYS_DISP_OVL0",
|
|
"MMSYS_DISP_OVL0_2L",
|
|
"MMSYS_DISP_RDMA0",
|
|
"MMSYS_DISP_WDMA0",
|
|
"MMSYS_DISP_COLOR0",
|
|
"MMSYS_DISP_CCORR0",
|
|
"MMSYS_DISP_AAL0",
|
|
"MMSYS_DISP_GAMMA0",
|
|
"MMSYS_DISP_DITHER0",
|
|
"MMSYS_DSI0_MM_CK",
|
|
"MMSYS_DSI0_IF_CK",
|
|
"MMSYS_26M",
|
|
"MMSYS_DISP_RSZ0",
|
|
"APMIXED_MIPI_26M",
|
|
"TOP_MUX_DISP_PWM",
|
|
"DISP_PWM",
|
|
"TOP_26M",
|
|
"TOP_UNIVPLL2_D4",
|
|
"TOP_ULPOSC1_D2",
|
|
"TOP_ULPOSC1_D8";
|
|
};
|
|
|
|
dsi_te: dsi_te {
|
|
compatible = "mediatek, DSI_TE-eint";
|
|
status = "disabled";
|
|
};
|
|
|
|
smi_larb2: smi_larb2@15021000 {
|
|
cell-index = <2>;
|
|
compatible = "mediatek,smi_larb2", "mediatek,smi_larb";
|
|
reg = <0 0x15021000 0 0x1000>;
|
|
mediatek,larb-id = <2>;
|
|
clocks = <&scpsys SCP_SYS_ISP>, <&mmsys_config CLK_MM_SMI_IMG>,
|
|
<&imgsys CLK_IMG_LARB2>;
|
|
clock-names = "mtcmos-isp", "gals-img2mm", "img-larb2";
|
|
mediatek,smi-id = <2>;
|
|
};
|
|
|
|
fdvt@1502b000 {
|
|
compatible = "mediatek,fdvt";
|
|
reg = <0 0x1502b000 0 0x1000>;
|
|
interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&imgsys CLK_IMG_FDVT>;
|
|
clock-names = "FD_CLK_IMG_FDVT";
|
|
};
|
|
|
|
vcodecsys: vcodecsys@17000000 {
|
|
compatible = "mediatek,mt6765-vcodecsys", "syscon";
|
|
reg = <0 0x17000000 0 0x10000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
venc_gcon: venc_gcon@17000000 {
|
|
compatible = "mediatek,venc_gcon", "syscon";
|
|
reg = <0 0x17000000 0 0x10000>;
|
|
clocks = <&scpsys SCP_SYS_DIS>,
|
|
<&scpsys SCP_SYS_VCODEC>,
|
|
<&mmsys_config CLK_MM_SMI_COMM0>,
|
|
<&mmsys_config CLK_MM_SMI_COMM1>,
|
|
<&mmsys_config CLK_MM_SMI_COMMON>,
|
|
<&vcodecsys CLK_VENC_SET3_VDEC>,
|
|
<&vcodecsys CLK_VENC_SET1_VENC>;
|
|
clock-names = "MT_SCP_SYS_DIS",
|
|
"MT_SCP_SYS_VCODEC",
|
|
"MT_CG_MM_SMI_COMM0",
|
|
"MT_CG_MM_SMI_COMM1",
|
|
"MT_CG_MM_SMI_COMMON",
|
|
"MT_CG_VDEC",
|
|
"MT_CG_VENC";
|
|
};
|
|
|
|
smi_larb1: smi_larb1@17010000 {
|
|
cell-index = <1>;
|
|
compatible = "mediatek,smi_larb1", "mediatek,smi_larb";
|
|
reg = <0 0x17010000 0 0x1000>;
|
|
mediatek,larb-id = <1>;
|
|
clocks = <&scpsys SCP_SYS_VCODEC>,
|
|
<&vcodecsys CLK_VENC_SET1_VENC>;
|
|
clock-names = "mtcmos-vcodec", "venc-larb1";
|
|
mediatek,smi-id = <1>;
|
|
};
|
|
|
|
venc@17020000 {
|
|
compatible = "mediatek,venc";
|
|
reg = <0 0x17020000 0 0x10000>;
|
|
interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
venc_jpg@17030000 {
|
|
compatible = "mediatek,venc_jpg";
|
|
reg = <0 0x17030000 0 0x10000>;
|
|
interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks =
|
|
<&vcodecsys CLK_VENC_SET2_JPGENC>;
|
|
clock-names =
|
|
"MT_CG_VENC_JPGENC";
|
|
};
|
|
|
|
vdec@17040000 {
|
|
compatible = "mediatek,vdec";
|
|
reg = <0 0x17040000 0 0x10000>;
|
|
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
mbist@17050000 {
|
|
compatible = "mediatek,mbist";
|
|
reg = <0 0x17050000 0 0x10000>;
|
|
};
|
|
|
|
camsys: camsys@1a000000 {
|
|
compatible = "mediatek,mt6765-camsys", "syscon";
|
|
reg = <0 0x1a000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
camsys1: camsysisp@1a000000 {
|
|
compatible = "mediatek,camsys", "syscon";
|
|
reg = <0 0x1a000000 0 0x1000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
smi_larb3: smi_larb3@1a002000 {
|
|
cell-index = <3>;
|
|
compatible = "mediatek,smi_larb3", "mediatek,smi_larb";
|
|
reg = <0 0x1a002000 0 0x1000>;
|
|
mediatek,larb-id = <3>;
|
|
clocks = <&scpsys SCP_SYS_CAM>, <&mmsys_config CLK_MM_SMI_CAM>,
|
|
<&camsys CLK_CAM_LARB3>;
|
|
clock-names = "mtcmos-cam", "gals-cam2mm", "cam-larb3";
|
|
mediatek,smi-id = <3>;
|
|
};
|
|
|
|
cam1@1a003000 {
|
|
compatible = "mediatek,cam1";
|
|
reg = <0 0x1a003000 0 0x1000>;
|
|
interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
cam2@1a004000 {
|
|
compatible = "mediatek,cam2";
|
|
reg = <0 0x1a004000 0 0x1000>;
|
|
interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
cam3@1a005000 {
|
|
compatible = "mediatek,cam3";
|
|
reg = <0 0x1a005000 0 0x1000>;
|
|
interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
cam_set@1a00b000 {
|
|
compatible = "mediatek,cam_set";
|
|
reg = <0 0x1a00b000 0 0x1000>;
|
|
};
|
|
|
|
cama_set@1a00c000 {
|
|
compatible = "mediatek,cama_set";
|
|
reg = <0 0x1a00c000 0 0x1000>;
|
|
};
|
|
|
|
camb_set@1a00d000 {
|
|
compatible = "mediatek,camb_set";
|
|
reg = <0 0x1a00d000 0 0x1000>;
|
|
};
|
|
|
|
cam_inner@1a013000 {
|
|
compatible = "mediatek,cam_inner";
|
|
reg = <0 0x1a013000 0 0x1000>;
|
|
};
|
|
|
|
cama_inner@1a014000 {
|
|
compatible = "mediatek,cama_inner";
|
|
reg = <0 0x1a014000 0 0x1000>;
|
|
};
|
|
|
|
camb_inner@1a015000 {
|
|
compatible = "mediatek,camb_inner";
|
|
reg = <0 0x1a015000 0 0x1000>;
|
|
};
|
|
|
|
cam_clear@1a01b000 {
|
|
compatible = "mediatek,cam_clear";
|
|
reg = <0 0x1a01b000 0 0x1000>;
|
|
};
|
|
|
|
cama_clear@1a01c000 {
|
|
compatible = "mediatek,cama_clear";
|
|
reg = <0 0x1a01c000 0 0x1000>;
|
|
};
|
|
|
|
camb_clear@1a01d000 {
|
|
compatible = "mediatek,camb_clear";
|
|
reg = <0 0x1a01d000 0 0x1000>;
|
|
};
|
|
|
|
cama_ext@1a024000 {
|
|
compatible = "mediatek,cama_ext";
|
|
reg = <0 0x1a024000 0 0x1000>;
|
|
};
|
|
|
|
camb_ext@1a025000 {
|
|
compatible = "mediatek,camb_ext";
|
|
reg = <0 0x1a025000 0 0x1000>;
|
|
};
|
|
|
|
seninf1@1a040000 {
|
|
compatible = "mediatek,seninf1";
|
|
reg = <0 0x1a040000 0 0x1000>;
|
|
};
|
|
|
|
seninf2@1a041000 {
|
|
compatible = "mediatek,seninf2";
|
|
reg = <0 0x1a041000 0 0x1000>;
|
|
};
|
|
|
|
seninf3@1a042000 {
|
|
compatible = "mediatek,seninf3";
|
|
reg = <0 0x1a042000 0 0x1000>;
|
|
};
|
|
|
|
seninf4@1a043000 {
|
|
compatible = "mediatek,seninf4";
|
|
reg = <0 0x1a043000 0 0x1000>;
|
|
};
|
|
|
|
kd_camera_hw1: kd_camera_hw1@1a040000 {
|
|
compatible = "mediatek,camera_hw";
|
|
reg = <0 0x1a040000 0 0x1000>;
|
|
/* SENINF_ADDR */
|
|
/* Camera Common Clock Framework (CCF) */
|
|
clocks = <&topckgen CLK_TOP_CAMTG_SEL>,
|
|
<&topckgen CLK_TOP_CAMTG1_SEL>,
|
|
<&topckgen CLK_TOP_CAMTG2_SEL>,
|
|
<&topckgen CLK_TOP_CAMTG3_SEL>,
|
|
<&topckgen CLK_TOP_USB20_192M_D32>,
|
|
<&topckgen CLK_TOP_USB20_192M_D16>,
|
|
<&topckgen CLK_TOP_UNIVPLL2_D32>,
|
|
<&topckgen CLK_TOP_USB20_192M_D4>,
|
|
<&topckgen CLK_TOP_UNIVPLL2_D8>,
|
|
<&topckgen CLK_TOP_USB20_192M_D8>,
|
|
<&clk26m>,
|
|
<&camsys CLK_CAM_SENINF>,
|
|
<&apmixed CLK_APMIXED_MIPIC0_26M>,
|
|
<&apmixed CLK_APMIXED_MIPIC1_26M>,
|
|
<&mipi_rx_ana_csi0a CLK_MIPI0A_CSR_CSI_EN_0A>,
|
|
<&topckgen CLK_TOP_CAMTM_SEL>,
|
|
<&topckgen CLK_TOP_UNIVPLL2_D2>,
|
|
<&scpsys SCP_SYS_CAM>;
|
|
|
|
|
|
clock-names = "CLK_TOP_CAMTG_SEL",
|
|
"CLK_TOP_CAMTG1_SEL",
|
|
"CLK_TOP_CAMTG2_SEL",
|
|
"CLK_TOP_CAMTG3_SEL",
|
|
"CLK_MCLK_6M",
|
|
"CLK_MCLK_12M",
|
|
"CLK_MCLK_13M",
|
|
"CLK_MCLK_48M",
|
|
"CLK_MCLK_52M",
|
|
"CLK_MCLK_24M",
|
|
"CLK_MCLK_26M",
|
|
"CLK_CAM_SENINF_CG",
|
|
"CLK_MIPI_C0_26M_CG",
|
|
"CLK_MIPI_C1_26M_CG",
|
|
"CLK_MIPI_ANA_0A_CG",
|
|
"CLK_TOP_CAMTM_SEL_CG",
|
|
"CLK_TOP_CAMTM_208_CG",
|
|
"CLK_SCP_SYS_CAM";
|
|
};
|
|
|
|
camsv1@1a050000 {
|
|
compatible = "mediatek,camsv1";
|
|
reg = <0 0x1a050000 0 0x1000>;
|
|
interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
camsv2@1a051000 {
|
|
compatible = "mediatek,camsv2";
|
|
reg = <0 0x1a051000 0 0x1000>;
|
|
interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
camsv3@1a052000 {
|
|
compatible = "mediatek,camsv3";
|
|
reg = <0 0x1a052000 0 0x1000>;
|
|
interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
camsv4@1a053000 {
|
|
compatible = "mediatek,camsv4";
|
|
reg = <0 0x1a053000 0 0x1000>;
|
|
interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_LOW>;
|
|
};
|
|
|
|
camera_af_hw_node: camera_af_hw_node {
|
|
compatible = "mediatek,camera_af_lens";
|
|
};
|
|
|
|
flashlight_core: flashlight_core {
|
|
compatible = "mediatek,flashlight_core";
|
|
};
|
|
|
|
flashlights_mt6370: flashlights_mt6370 {
|
|
compatible = "mediatek,flashlights_mt6370";
|
|
decouple = <0>;
|
|
channel@1 {
|
|
type = <0>;
|
|
ct = <0>;
|
|
part = <0>;
|
|
};
|
|
channel@2 {
|
|
type = <0>;
|
|
ct = <1>;
|
|
part = <0>;
|
|
};
|
|
};
|
|
|
|
gps {
|
|
compatible = "mediatek,gps";
|
|
};
|
|
|
|
ccu@1a0b1000 {
|
|
compatible = "mediatek,ccu";
|
|
reg = <0 0x1a0b1000 0 0x1000>;
|
|
interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&camsys CLK_CAM_CCU>,
|
|
<&scpsys SCP_SYS_CAM>;
|
|
clock-names = "CCU_CLK_CAM_CCU",
|
|
"CAM_PWR";
|
|
};
|
|
|
|
lk_charger: lk_charger {
|
|
compatible = "mediatek,lk_charger";
|
|
enable_anime;
|
|
enable_pe_plus;
|
|
enable_pd20_reset;
|
|
power_path_support;
|
|
max_charger_voltage = <6500000>;
|
|
fast_charge_voltage = <3000000>;
|
|
|
|
/* charging current */
|
|
usb_charger_current = <500000>;
|
|
ac_charger_current = <2000000>;
|
|
ac_charger_input_current = <1500000>;
|
|
non_std_ac_charger_current = <500000>;
|
|
charging_host_charger_current = <1500000>;
|
|
ta_ac_charger_current = <3000000>;
|
|
pd_charger_current = <500000>;
|
|
|
|
/* battery temperature protection */
|
|
temp_t4_threshold = <50>;
|
|
temp_t3_threshold = <45>;
|
|
temp_t1_threshold = <0>;
|
|
};
|
|
|
|
pe: pe {
|
|
compatible = "mediatek,charger,pe";
|
|
gauge = <&mtk_gauge>;
|
|
|
|
ta_12v_support;
|
|
ta_9v_support;
|
|
|
|
pe_ichg_level_threshold = <1000000>; /* uA */
|
|
ta_start_battery_soc = <0>;
|
|
ta_stop_battery_soc = <85>;
|
|
min_charger_voltage = <4600000>;
|
|
|
|
ta_ac_12v_input_current = <3200000>;
|
|
ta_ac_9v_input_current = <3200000>;
|
|
ta_ac_7v_input_current = <3200000>;
|
|
pe_charger_current = <3000000>;
|
|
};
|
|
|
|
pe2: pe2 {
|
|
compatible = "mediatek,charger,pe2";
|
|
gauge = <&mtk_gauge>;
|
|
|
|
/* PE 2.0 */
|
|
pe20_ichg_level_threshold = <1000000>; /* uA */
|
|
ta_start_battery_soc = <0>;
|
|
ta_stop_battery_soc = <85>;
|
|
min_charger_voltage = <4600000>;
|
|
|
|
/* cable measurement impedance */
|
|
cable_imp_threshold = <699>;
|
|
vbat_cable_imp_threshold = <3900000>; /* uV */
|
|
|
|
/* single charger */
|
|
sc_input_current = <3200000>;
|
|
sc_charger_current = <3000000>;
|
|
|
|
/* dual charger in series */
|
|
dcs_input_current = <3200000>;
|
|
dcs_chg1_charger_current = <1500000>;
|
|
dcs_chg2_charger_current = <1500000>;
|
|
|
|
dual_polling_ieoc = <450000>;
|
|
slave_mivr_diff = <100000>;
|
|
};
|
|
|
|
pdc: pdc {
|
|
compatible = "mediatek,charger,pd";
|
|
gauge = <&mtk_gauge>;
|
|
|
|
min_charger_voltage = <4600000>;
|
|
pd_vbus_low_bound = <5000000>;
|
|
pd_vbus_upper_bound = <5000000>;
|
|
vsys_watt = <5000000>;
|
|
ibus_err = <14>;
|
|
|
|
pd_stop_battery_soc = <80>;
|
|
|
|
/* single charger */
|
|
sc_input_current = <3200000>;
|
|
sc_charger_current = <3000000>;
|
|
|
|
/* dual charger in series */
|
|
dcs_input_current = <3200000>;
|
|
dcs_chg1_charger_current = <1500000>;
|
|
dcs_chg2_charger_current = <1500000>;
|
|
|
|
/* dual charger */
|
|
dual_polling_ieoc = <450000>;
|
|
slave_mivr_diff = <100000>;
|
|
};
|
|
|
|
pe4: pe4 {
|
|
compatible = "mediatek,charger,pe4";
|
|
gauge = <&mtk_gauge>;
|
|
|
|
min_charger_voltage = <4600000>;
|
|
pe40_stop_battery_soc = <80>;
|
|
|
|
high_temp_to_leave_pe40 = <46>;
|
|
high_temp_to_enter_pe40 = <39>;
|
|
low_temp_to_leave_pe40 = <10>;
|
|
low_temp_to_enter_pe40 = <16>;
|
|
ibus_err = <14>;
|
|
|
|
/* PE 4.0 cable impedance (mohm) */
|
|
pe40_r_cable_1a_lower = <500>;
|
|
pe40_r_cable_2a_lower = <351>;
|
|
pe40_r_cable_3a_lower = <240>;
|
|
|
|
/* single charger */
|
|
sc_input_current = <3200000>;
|
|
sc_charger_current = <3000000>;
|
|
|
|
/* dual charger in series*/
|
|
dcs_input_current = <3200000>;
|
|
dcs_chg1_charger_current = <1500000>;
|
|
dcs_chg2_charger_current = <1500000>;
|
|
|
|
dual_polling_ieoc = <450000>;
|
|
slave_mivr_diff = <100000>;
|
|
};
|
|
|
|
charger: charger {
|
|
compatible = "mediatek,charger";
|
|
gauge = <&mtk_gauge>;
|
|
charger = <&mt6370_chg>;
|
|
bootmode = <&chosen>;
|
|
pmic = <&main_pmic>;
|
|
|
|
algorithm_name = "Basic";
|
|
charger_configuration= <0>;
|
|
|
|
/* common */
|
|
battery_cv = <4350000>;
|
|
max_charger_voltage = <6500000>;
|
|
min_charger_voltage = <4600000>;
|
|
|
|
/* sw jeita */
|
|
/* enable_sw_jeita; */
|
|
jeita_temp_above_t4_cv = <4240000>;
|
|
jeita_temp_t3_to_t4_cv = <4240000>;
|
|
jeita_temp_t2_to_t3_cv = <4340000>;
|
|
jeita_temp_t1_to_t2_cv = <4240000>;
|
|
jeita_temp_t0_to_t1_cv = <4040000>;
|
|
jeita_temp_below_t0_cv = <4040000>;
|
|
temp_t4_thres = <50>;
|
|
temp_t4_thres_minus_x_degree = <47>;
|
|
temp_t3_thres = <45>;
|
|
temp_t3_thres_minus_x_degree = <39>;
|
|
temp_t2_thres = <10>;
|
|
temp_t2_thres_plus_x_degree = <16>;
|
|
temp_t1_thres = <0>;
|
|
temp_t1_thres_plus_x_degree = <6>;
|
|
temp_t0_thres = <0>;
|
|
temp_t0_thres_plus_x_degree = <0>;
|
|
temp_neg_10_thres = <0>;
|
|
|
|
/* battery temperature protection */
|
|
enable_min_charge_temp;
|
|
min_charge_temp = <0>;
|
|
min_charge_temp_plus_x_degree = <6>;
|
|
max_charge_temp = <50>;
|
|
max_charge_temp_minus_x_degree = <47>;
|
|
|
|
/* charging current */
|
|
usb_charger_current = <500000>;
|
|
ac_charger_current = <2000000>;
|
|
ac_charger_input_current = <1500000>;
|
|
charging_host_charger_current = <1500000>;
|
|
|
|
/* dynamic mivr */
|
|
enable_dynamic_mivr;
|
|
min_charger_voltage_1 = <4400000>;
|
|
min_charger_voltage_2 = <4200000>;
|
|
max_dmivr_charger_current = <1800000>;
|
|
};
|
|
|
|
pd_adapter: pd_adapter {
|
|
compatible = "mediatek,pd_adapter";
|
|
adapter_name = "pd_adapter";
|
|
};
|
|
|
|
extcon_usb: extcon_usb {
|
|
compatible = "mediatek,extcon-usb";
|
|
charger = <&mt6370_chg>;
|
|
vbus-supply = <&otg_vbus>;
|
|
vbus-voltage = <5000000>;
|
|
vbus-current = <1800000>;
|
|
dev-conn = <&usb>;
|
|
mediatek,bypss-typec-sink = <1>;
|
|
};
|
|
|
|
rt9465_slave_chr: rt9465_slave_chr {
|
|
compatible = "richtek,rt9465";
|
|
status = "disabled";
|
|
};
|
|
|
|
rt-pd-manager {
|
|
compatible = "mediatek,rt-pd-manager";
|
|
};
|
|
|
|
subpmic_pmu_eint: mt6370_pmu_eint {
|
|
};
|
|
|
|
tcpc_pd: mt6370_pd_eint {
|
|
};
|
|
|
|
irtx_pwm:irtx_pwm {
|
|
compatible = "mediatek,irtx-pwm";
|
|
pwm_ch = <0>;
|
|
pwm_data_invert = <0>;
|
|
};
|
|
|
|
odm: odm{
|
|
compatible = "simple-bus";
|
|
/* reserved for overlay by odm */
|
|
};
|
|
|
|
radio_md_cfg: radio_md_cfg {
|
|
compatible = "mediatek,radio_md_cfg";
|
|
};
|
|
|
|
dynamic_options: dynamic_options {
|
|
compatible = "mediatek,dynamic_options";
|
|
};
|
|
|
|
audio_snd_card {
|
|
compatible = "mediatek,audio_snd_card";
|
|
};
|
|
|
|
mt_soc_deep_buffer_dl_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_deep_buffer_dl";
|
|
};
|
|
|
|
mt_soc_ul1_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_capture";
|
|
};
|
|
|
|
mt_soc_voice_md1 {
|
|
compatible = "mediatek,mt_soc_pcm_voice_md1";
|
|
};
|
|
|
|
mt_soc_uldlloopback_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_uldlloopback";
|
|
};
|
|
|
|
mt_soc_i2s0_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_dl1_i2s0";
|
|
};
|
|
|
|
mt_soc_mrgrx_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_mrgrx";
|
|
};
|
|
|
|
mt_soc_mrgrx_awb_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_mrgrx_awb";
|
|
};
|
|
|
|
mt_soc_fm_i2s_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_fm_i2s";
|
|
};
|
|
|
|
mt_soc_fm_i2s_awb_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_fm_i2s_awb";
|
|
};
|
|
|
|
mt_soc_i2s0dl1_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_dl1_i2s0dl1";
|
|
};
|
|
|
|
mt_soc_dl1_awb_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_dl1_awb";
|
|
};
|
|
|
|
mt_soc_voice_md1_bt {
|
|
compatible = "mediatek,mt_soc_pcm_voice_md1_bt";
|
|
};
|
|
|
|
mt_soc_voip_bt_out {
|
|
compatible = "mediatek,mt_soc_pcm_dl1_bt";
|
|
};
|
|
|
|
mt_soc_voip_bt_in {
|
|
compatible = "mediatek,mt_soc_pcm_bt_dai";
|
|
};
|
|
|
|
mt_soc_tdmrx_pcm {
|
|
compatible = "mediatek,mt_soc_tdm_capture";
|
|
};
|
|
|
|
mt_soc_fm_mrgtx_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_fmtx";
|
|
};
|
|
|
|
mt_soc_ul2_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_capture2";
|
|
};
|
|
|
|
mt_soc_i2s0_awb_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_i2s0_awb";
|
|
};
|
|
|
|
mt_soc_voice_md2 {
|
|
compatible = "mediatek,mt_soc_pcm_voice_md2";
|
|
};
|
|
mt_soc_pcm_dl1_scp_spk {
|
|
compatible = "mediatek,mt_soc_pcm_dl1_scp_spk";
|
|
};
|
|
mt_soc_pcm_voice_scp {
|
|
compatible = "mediatek,mt_soc_pcm_voice_scp";
|
|
};
|
|
mt_soc_routing_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_routing";
|
|
/*i2s1clk-gpio = <7 6>;*/
|
|
/*i2s1dat-gpio = <5 6>;*/
|
|
/*i2s1mclk-gpio = <9 6>;*/
|
|
/*i2s1ws-gpio = <6 6>;*/
|
|
};
|
|
|
|
mt_soc_voice_md2_bt {
|
|
compatible = "mediatek,mt_soc_pcm_voice_md2_bt";
|
|
};
|
|
|
|
mt_soc_hp_impedance_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_hp_impedance";
|
|
};
|
|
|
|
mt_soc_codec_name {
|
|
compatible = "mediatek,mt_soc_codec_63xx";
|
|
use_hp_depop_flow = <0>; /* select 1: use, 0: not use */
|
|
use_ul_260k = <0>; /* select 1: use, 0: not use */
|
|
};
|
|
|
|
mt_soc_dummy_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_dummy";
|
|
};
|
|
|
|
mt_soc_codec_dummy_name {
|
|
compatible = "mediatek,mt_soc_codec_dummy";
|
|
};
|
|
|
|
mt_soc_routing_dai_name {
|
|
compatible = "mediatek,mt_soc_dai_routing";
|
|
};
|
|
|
|
mt_soc_dai_name {
|
|
compatible = "mediatek,mt_soc_dai_stub";
|
|
};
|
|
|
|
mt_soc_dl2_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_dl2";
|
|
};
|
|
|
|
mt_soc_anc_pcm {
|
|
compatible = "mediatek,mt_soc_pcm_anc";
|
|
};
|
|
|
|
mt_soc_pcm_voice_ultra {
|
|
compatible = "mediatek,mt_soc_pcm_voice_ultra";
|
|
};
|
|
|
|
mt_soc_pcm_voice_usb {
|
|
compatible = "mediatek,mt_soc_pcm_voice_usb";
|
|
};
|
|
|
|
mt_soc_pcm_voice_usb_echoref {
|
|
compatible = "mediatek,mt_soc_pcm_voice_usb_echoref";
|
|
};
|
|
|
|
pmic_clock_buffer_ctrl: pmic_clock_buffer_ctrl {
|
|
compatible = "mediatek,pmic_clock_buffer";
|
|
mediatek,clkbuf-quantity = <7>;
|
|
mediatek,clkbuf-config = <2 1 1 2 0 0 0>;
|
|
mediatek,clkbuf-driving-current = <1 1 1 1 1 1 1>;
|
|
mediatek,bblpm-support = "enable";
|
|
|
|
pwrap-dcxo-en = <0x188 0 0x188 1 0x188 0>;
|
|
pwrap-dcxo-cfg = <0x18c 0x19c>;
|
|
|
|
spm-pwr-status = <0x180 0 0x180 1>;
|
|
|
|
pwrap = <&pwrap>;
|
|
sleep = <&sleep>;
|
|
};
|
|
|
|
eas {
|
|
eff_turn_point = <467>;
|
|
tiny = <50>;
|
|
};
|
|
|
|
i2c7:i2c7{};
|
|
i2c8:i2c8{};
|
|
i2c9:i2c9{};
|
|
smart_pa: smart_pa{};
|
|
md1_sim1_hot_plug_eint:md1_sim1_hot_plug_eint{};
|
|
md1_sim2_hot_plug_eint:md1_sim2_hot_plug_eint{};
|
|
|
|
cm_mgr: cm_mgr@10200000 {
|
|
compatible = "mediatek,mt6765-cm_mgr";
|
|
reg = <0 0x10200000 0 0x4000>;
|
|
reg-names = "cm_mgr_base";
|
|
required-opps = <&dvfsrc_freq_opp0>,
|
|
<&dvfsrc_freq_opp1>,
|
|
<&dvfsrc_freq_opp2>;
|
|
cm_mgr,cp_down = <100 100>;
|
|
cm_mgr,cp_up = <100 100>;
|
|
cm_mgr,dt_down = <0 3>;
|
|
cm_mgr,dt_up = <0 3>;
|
|
cm_mgr,vp_down = <100 100>;
|
|
cm_mgr,vp_up = <100 100>;
|
|
|
|
/* use_bcpu_weight = "enable"; */
|
|
/* cpu_power_bcpu_weight_max = <100>; */
|
|
/* cpu_power_bcpu_weight_min = <100>; */
|
|
|
|
/* use_cpu_to_dram_map = "enable"; */
|
|
/* cm_mgr_cpu_opp_to_dram = <0 0 0 0 1 1 1 1 */
|
|
/* 1 2 2 2 2 2 2 2>; */
|
|
|
|
/* use_cpu_to_dram_map_new = "enable"; */
|
|
};
|
|
|
|
dram_ctrl {
|
|
compatible = "mediatek,dram-qosctrl";
|
|
required-opps = <&dvfsrc_freq_opp0>,
|
|
<&dvfsrc_freq_opp1>;
|
|
};
|
|
|
|
};
|
|
|
|
#include "cust_mt6765_msdc.dtsi"
|
|
#include "mt6357.dtsi"
|
|
#include "bat_setting/mt6765_battery_prop.dtsi"
|
|
#include "mt6370.dtsi"
|
|
#include "mt6370_pd.dtsi"
|
|
#ifdef CONFIG_CHARGER_RT9471
|
|
#include "rt9471.dtsi"
|
|
#endif
|