1315 lines
29 KiB
Plaintext
1315 lines
29 KiB
Plaintext
/*
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* Device Tree Source for OMAP4 clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&cm1_clocks {
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extalt_clkin_ck: extalt_clkin_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <59000000>;
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};
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pad_clks_src_ck: pad_clks_src_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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};
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pad_clks_ck: pad_clks_ck@108 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&pad_clks_src_ck>;
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ti,bit-shift = <8>;
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reg = <0x0108>;
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};
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pad_slimbus_core_clks_ck: pad_slimbus_core_clks_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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};
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secure_32k_clk_src_ck: secure_32k_clk_src_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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slimbus_src_clk: slimbus_src_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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};
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slimbus_clk: slimbus_clk@108 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&slimbus_src_clk>;
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ti,bit-shift = <10>;
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reg = <0x0108>;
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};
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sys_32k_ck: sys_32k_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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virt_12000000_ck: virt_12000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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};
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virt_13000000_ck: virt_13000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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};
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virt_16800000_ck: virt_16800000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <16800000>;
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};
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virt_19200000_ck: virt_19200000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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};
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virt_26000000_ck: virt_26000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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};
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virt_27000000_ck: virt_27000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <27000000>;
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};
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virt_38400000_ck: virt_38400000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <38400000>;
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};
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tie_low_clock_ck: tie_low_clock_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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utmi_phy_clkout_ck: utmi_phy_clkout_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <60000000>;
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};
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xclk60mhsp1_ck: xclk60mhsp1_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <60000000>;
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};
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xclk60mhsp2_ck: xclk60mhsp2_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <60000000>;
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};
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xclk60motg_ck: xclk60motg_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <60000000>;
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};
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dpll_abe_ck: dpll_abe_ck@1e0 {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-m4xen-clock";
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clocks = <&abe_dpll_refclk_mux_ck>, <&abe_dpll_bypass_clk_mux_ck>;
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reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
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};
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dpll_abe_x2_ck: dpll_abe_x2_ck@1f0 {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-x2-clock";
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clocks = <&dpll_abe_ck>;
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reg = <0x01f0>;
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};
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dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_abe_x2_ck>;
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ti,max-div = <31>;
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ti,autoidle-shift = <8>;
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reg = <0x01f0>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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};
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abe_24m_fclk: abe_24m_fclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_abe_m2x2_ck>;
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clock-mult = <1>;
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clock-div = <8>;
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};
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abe_clk: abe_clk@108 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_abe_m2x2_ck>;
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ti,max-div = <4>;
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reg = <0x0108>;
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ti,index-power-of-two;
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};
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dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_abe_x2_ck>;
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ti,max-div = <31>;
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ti,autoidle-shift = <8>;
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reg = <0x01f4>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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};
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core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck@12c {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_clkin_ck>, <&dpll_abe_m3x2_ck>;
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ti,bit-shift = <23>;
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reg = <0x012c>;
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};
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dpll_core_ck: dpll_core_ck@120 {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-core-clock";
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clocks = <&sys_clkin_ck>, <&core_hsd_byp_clk_mux_ck>;
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reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
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};
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dpll_core_x2_ck: dpll_core_x2_ck {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-x2-clock";
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clocks = <&dpll_core_ck>;
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};
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dpll_core_m6x2_ck: dpll_core_m6x2_ck@140 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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ti,autoidle-shift = <8>;
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reg = <0x0140>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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};
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dpll_core_m2_ck: dpll_core_m2_ck@130 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_ck>;
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ti,max-div = <31>;
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ti,autoidle-shift = <8>;
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reg = <0x0130>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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};
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ddrphy_ck: ddrphy_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m2_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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dpll_core_m5x2_ck: dpll_core_m5x2_ck@13c {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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ti,autoidle-shift = <8>;
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reg = <0x013c>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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};
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div_core_ck: div_core_ck@100 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_m5x2_ck>;
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reg = <0x0100>;
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ti,max-div = <2>;
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};
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div_iva_hs_clk: div_iva_hs_clk@1dc {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_m5x2_ck>;
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ti,max-div = <4>;
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reg = <0x01dc>;
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ti,index-power-of-two;
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};
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div_mpu_hs_clk: div_mpu_hs_clk@19c {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_m5x2_ck>;
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ti,max-div = <4>;
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reg = <0x019c>;
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ti,index-power-of-two;
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};
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dpll_core_m4x2_ck: dpll_core_m4x2_ck@138 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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ti,autoidle-shift = <8>;
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reg = <0x0138>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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};
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dll_clk_div_ck: dll_clk_div_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_m4x2_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_abe_ck>;
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ti,max-div = <31>;
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reg = <0x01f0>;
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ti,index-starts-at-one;
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};
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dpll_core_m3x2_gate_ck: dpll_core_m3x2_gate_ck@134 {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,bit-shift = <8>;
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reg = <0x0134>;
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};
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dpll_core_m3x2_div_ck: dpll_core_m3x2_div_ck@134 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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reg = <0x0134>;
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ti,index-starts-at-one;
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};
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dpll_core_m3x2_ck: dpll_core_m3x2_ck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&dpll_core_m3x2_gate_ck>, <&dpll_core_m3x2_div_ck>;
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};
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dpll_core_m7x2_ck: dpll_core_m7x2_ck@144 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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ti,autoidle-shift = <8>;
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reg = <0x0144>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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};
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iva_hsd_byp_clk_mux_ck: iva_hsd_byp_clk_mux_ck@1ac {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_clkin_ck>, <&div_iva_hs_clk>;
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ti,bit-shift = <23>;
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reg = <0x01ac>;
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};
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dpll_iva_ck: dpll_iva_ck@1a0 {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-clock";
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clocks = <&sys_clkin_ck>, <&iva_hsd_byp_clk_mux_ck>;
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reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
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assigned-clocks = <&dpll_iva_ck>;
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assigned-clock-rates = <931200000>;
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};
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dpll_iva_x2_ck: dpll_iva_x2_ck {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-x2-clock";
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clocks = <&dpll_iva_ck>;
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};
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dpll_iva_m4x2_ck: dpll_iva_m4x2_ck@1b8 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_iva_x2_ck>;
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ti,max-div = <31>;
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ti,autoidle-shift = <8>;
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reg = <0x01b8>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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assigned-clocks = <&dpll_iva_m4x2_ck>;
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assigned-clock-rates = <465600000>;
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};
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dpll_iva_m5x2_ck: dpll_iva_m5x2_ck@1bc {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_iva_x2_ck>;
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ti,max-div = <31>;
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ti,autoidle-shift = <8>;
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reg = <0x01bc>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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assigned-clocks = <&dpll_iva_m5x2_ck>;
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assigned-clock-rates = <266100000>;
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};
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dpll_mpu_ck: dpll_mpu_ck@160 {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-clock";
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clocks = <&sys_clkin_ck>, <&div_mpu_hs_clk>;
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reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
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};
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dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_mpu_ck>;
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ti,max-div = <31>;
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ti,autoidle-shift = <8>;
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reg = <0x0170>;
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ti,index-starts-at-one;
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ti,invert-autoidle-bit;
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};
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per_hs_clk_div_ck: per_hs_clk_div_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_abe_m3x2_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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usb_hs_clk_div_ck: usb_hs_clk_div_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_abe_m3x2_ck>;
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clock-mult = <1>;
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clock-div = <3>;
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};
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l3_div_ck: l3_div_ck@100 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&div_core_ck>;
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ti,bit-shift = <4>;
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ti,max-div = <2>;
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reg = <0x0100>;
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};
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l4_div_ck: l4_div_ck@100 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&l3_div_ck>;
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ti,bit-shift = <8>;
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ti,max-div = <2>;
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reg = <0x0100>;
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};
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lp_clk_div_ck: lp_clk_div_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_abe_m2x2_ck>;
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clock-mult = <1>;
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clock-div = <16>;
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};
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mpu_periphclk: mpu_periphclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_mpu_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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ocp_abe_iclk: ocp_abe_iclk@528 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&abe_clkctrl OMAP4_AESS_CLKCTRL 24>;
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ti,bit-shift = <24>;
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reg = <0x0528>;
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ti,dividers = <2>, <1>;
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};
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per_abe_24m_fclk: per_abe_24m_fclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_abe_m2_ck>;
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clock-mult = <1>;
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clock-div = <4>;
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};
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dummy_ck: dummy_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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};
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&prm_clocks {
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sys_clkin_ck: sys_clkin_ck@110 {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
|
|
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
|
|
reg = <0x0110>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
abe_dpll_bypass_clk_mux_ck: abe_dpll_bypass_clk_mux_ck@108 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x0108>;
|
|
};
|
|
|
|
abe_dpll_refclk_mux_ck: abe_dpll_refclk_mux_ck@10c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin_ck>, <&sys_32k_ck>;
|
|
reg = <0x010c>;
|
|
};
|
|
|
|
dbgclk_mux_ck: dbgclk_mux_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&sys_clkin_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <1>;
|
|
};
|
|
|
|
l4_wkup_clk_mux_ck: l4_wkup_clk_mux_ck@108 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin_ck>, <&lp_clk_div_ck>;
|
|
reg = <0x0108>;
|
|
};
|
|
|
|
syc_clk_div_ck: syc_clk_div_ck@100 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&sys_clkin_ck>;
|
|
reg = <0x0100>;
|
|
ti,max-div = <2>;
|
|
};
|
|
|
|
usim_ck: usim_ck@1858 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_m4x2_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x1858>;
|
|
ti,dividers = <14>, <18>;
|
|
};
|
|
|
|
usim_fclk: usim_fclk@1858 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&usim_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1858>;
|
|
};
|
|
|
|
trace_clk_div_ck: trace_clk_div_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,clkdm-gate-clock";
|
|
clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 24>;
|
|
};
|
|
};
|
|
|
|
&prm_clockdomains {
|
|
emu_sys_clkdm: emu_sys_clkdm {
|
|
compatible = "ti,clockdomain";
|
|
clocks = <&trace_clk_div_ck>;
|
|
};
|
|
};
|
|
|
|
&cm2_clocks {
|
|
per_hsd_byp_clk_mux_ck: per_hsd_byp_clk_mux_ck@14c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin_ck>, <&per_hs_clk_div_ck>;
|
|
ti,bit-shift = <23>;
|
|
reg = <0x014c>;
|
|
};
|
|
|
|
dpll_per_ck: dpll_per_ck@140 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap4-dpll-clock";
|
|
clocks = <&sys_clkin_ck>, <&per_hsd_byp_clk_mux_ck>;
|
|
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
|
|
};
|
|
|
|
dpll_per_m2_ck: dpll_per_m2_ck@150 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_ck>;
|
|
ti,max-div = <31>;
|
|
reg = <0x0150>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
dpll_per_x2_ck: dpll_per_x2_ck@150 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap4-dpll-x2-clock";
|
|
clocks = <&dpll_per_ck>;
|
|
reg = <0x0150>;
|
|
};
|
|
|
|
dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_x2_ck>;
|
|
ti,max-div = <31>;
|
|
ti,autoidle-shift = <8>;
|
|
reg = <0x0150>;
|
|
ti,index-starts-at-one;
|
|
ti,invert-autoidle-bit;
|
|
};
|
|
|
|
dpll_per_m3x2_gate_ck: dpll_per_m3x2_gate_ck@154 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-no-wait-gate-clock";
|
|
clocks = <&dpll_per_x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0154>;
|
|
};
|
|
|
|
dpll_per_m3x2_div_ck: dpll_per_m3x2_div_ck@154 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-divider-clock";
|
|
clocks = <&dpll_per_x2_ck>;
|
|
ti,max-div = <31>;
|
|
reg = <0x0154>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
dpll_per_m3x2_ck: dpll_per_m3x2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&dpll_per_m3x2_gate_ck>, <&dpll_per_m3x2_div_ck>;
|
|
};
|
|
|
|
dpll_per_m4x2_ck: dpll_per_m4x2_ck@158 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_x2_ck>;
|
|
ti,max-div = <31>;
|
|
ti,autoidle-shift = <8>;
|
|
reg = <0x0158>;
|
|
ti,index-starts-at-one;
|
|
ti,invert-autoidle-bit;
|
|
};
|
|
|
|
dpll_per_m5x2_ck: dpll_per_m5x2_ck@15c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_x2_ck>;
|
|
ti,max-div = <31>;
|
|
ti,autoidle-shift = <8>;
|
|
reg = <0x015c>;
|
|
ti,index-starts-at-one;
|
|
ti,invert-autoidle-bit;
|
|
};
|
|
|
|
dpll_per_m6x2_ck: dpll_per_m6x2_ck@160 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_x2_ck>;
|
|
ti,max-div = <31>;
|
|
ti,autoidle-shift = <8>;
|
|
reg = <0x0160>;
|
|
ti,index-starts-at-one;
|
|
ti,invert-autoidle-bit;
|
|
};
|
|
|
|
dpll_per_m7x2_ck: dpll_per_m7x2_ck@164 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_x2_ck>;
|
|
ti,max-div = <31>;
|
|
ti,autoidle-shift = <8>;
|
|
reg = <0x0164>;
|
|
ti,index-starts-at-one;
|
|
ti,invert-autoidle-bit;
|
|
};
|
|
|
|
dpll_usb_ck: dpll_usb_ck@180 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap4-dpll-j-type-clock";
|
|
clocks = <&sys_clkin_ck>, <&usb_hs_clk_div_ck>;
|
|
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
|
|
};
|
|
|
|
dpll_usb_clkdcoldo_ck: dpll_usb_clkdcoldo_ck@1b4 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,fixed-factor-clock";
|
|
clocks = <&dpll_usb_ck>;
|
|
ti,clock-div = <1>;
|
|
ti,autoidle-shift = <8>;
|
|
reg = <0x01b4>;
|
|
ti,clock-mult = <1>;
|
|
ti,invert-autoidle-bit;
|
|
};
|
|
|
|
dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_usb_ck>;
|
|
ti,max-div = <127>;
|
|
ti,autoidle-shift = <8>;
|
|
reg = <0x0190>;
|
|
ti,index-starts-at-one;
|
|
ti,invert-autoidle-bit;
|
|
};
|
|
|
|
ducati_clk_mux_ck: ducati_clk_mux_ck@100 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&div_core_ck>, <&dpll_per_m6x2_ck>;
|
|
reg = <0x0100>;
|
|
};
|
|
|
|
func_12m_fclk: func_12m_fclk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_per_m2x2_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <16>;
|
|
};
|
|
|
|
func_24m_clk: func_24m_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_per_m2_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <4>;
|
|
};
|
|
|
|
func_24mc_fclk: func_24mc_fclk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_per_m2x2_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <8>;
|
|
};
|
|
|
|
func_48m_fclk: func_48m_fclk@108 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_m2x2_ck>;
|
|
reg = <0x0108>;
|
|
ti,dividers = <4>, <8>;
|
|
};
|
|
|
|
func_48mc_fclk: func_48mc_fclk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_per_m2x2_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <4>;
|
|
};
|
|
|
|
func_64m_fclk: func_64m_fclk@108 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_m4x2_ck>;
|
|
reg = <0x0108>;
|
|
ti,dividers = <2>, <4>;
|
|
};
|
|
|
|
func_96m_fclk: func_96m_fclk@108 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_m2x2_ck>;
|
|
reg = <0x0108>;
|
|
ti,dividers = <2>, <4>;
|
|
};
|
|
|
|
init_60m_fclk: init_60m_fclk@104 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_usb_m2_ck>;
|
|
reg = <0x0104>;
|
|
ti,dividers = <1>, <8>;
|
|
};
|
|
|
|
per_abe_nc_fclk: per_abe_nc_fclk@108 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_abe_m2_ck>;
|
|
reg = <0x0108>;
|
|
ti,max-div = <2>;
|
|
};
|
|
|
|
usb_phy_cm_clk32k: usb_phy_cm_clk32k@640 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_32k_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0640>;
|
|
};
|
|
};
|
|
|
|
&cm2_clockdomains {
|
|
l3_init_clkdm: l3_init_clkdm {
|
|
compatible = "ti,clockdomain";
|
|
clocks = <&dpll_usb_ck>;
|
|
};
|
|
};
|
|
|
|
&scrm_clocks {
|
|
auxclk0_src_gate_ck: auxclk0_src_gate_ck@310 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-no-wait-gate-clock";
|
|
clocks = <&dpll_core_m3x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0310>;
|
|
};
|
|
|
|
auxclk0_src_mux_ck: auxclk0_src_mux_ck@310 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x0310>;
|
|
};
|
|
|
|
auxclk0_src_ck: auxclk0_src_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
|
|
};
|
|
|
|
auxclk0_ck: auxclk0_ck@310 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&auxclk0_src_ck>;
|
|
ti,bit-shift = <16>;
|
|
ti,max-div = <16>;
|
|
reg = <0x0310>;
|
|
};
|
|
|
|
auxclk1_src_gate_ck: auxclk1_src_gate_ck@314 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-no-wait-gate-clock";
|
|
clocks = <&dpll_core_m3x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0314>;
|
|
};
|
|
|
|
auxclk1_src_mux_ck: auxclk1_src_mux_ck@314 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x0314>;
|
|
};
|
|
|
|
auxclk1_src_ck: auxclk1_src_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
|
|
};
|
|
|
|
auxclk1_ck: auxclk1_ck@314 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&auxclk1_src_ck>;
|
|
ti,bit-shift = <16>;
|
|
ti,max-div = <16>;
|
|
reg = <0x0314>;
|
|
};
|
|
|
|
auxclk2_src_gate_ck: auxclk2_src_gate_ck@318 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-no-wait-gate-clock";
|
|
clocks = <&dpll_core_m3x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0318>;
|
|
};
|
|
|
|
auxclk2_src_mux_ck: auxclk2_src_mux_ck@318 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x0318>;
|
|
};
|
|
|
|
auxclk2_src_ck: auxclk2_src_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
|
|
};
|
|
|
|
auxclk2_ck: auxclk2_ck@318 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&auxclk2_src_ck>;
|
|
ti,bit-shift = <16>;
|
|
ti,max-div = <16>;
|
|
reg = <0x0318>;
|
|
};
|
|
|
|
auxclk3_src_gate_ck: auxclk3_src_gate_ck@31c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-no-wait-gate-clock";
|
|
clocks = <&dpll_core_m3x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x031c>;
|
|
};
|
|
|
|
auxclk3_src_mux_ck: auxclk3_src_mux_ck@31c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x031c>;
|
|
};
|
|
|
|
auxclk3_src_ck: auxclk3_src_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
|
|
};
|
|
|
|
auxclk3_ck: auxclk3_ck@31c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&auxclk3_src_ck>;
|
|
ti,bit-shift = <16>;
|
|
ti,max-div = <16>;
|
|
reg = <0x031c>;
|
|
};
|
|
|
|
auxclk4_src_gate_ck: auxclk4_src_gate_ck@320 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-no-wait-gate-clock";
|
|
clocks = <&dpll_core_m3x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0320>;
|
|
};
|
|
|
|
auxclk4_src_mux_ck: auxclk4_src_mux_ck@320 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x0320>;
|
|
};
|
|
|
|
auxclk4_src_ck: auxclk4_src_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
|
|
};
|
|
|
|
auxclk4_ck: auxclk4_ck@320 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&auxclk4_src_ck>;
|
|
ti,bit-shift = <16>;
|
|
ti,max-div = <16>;
|
|
reg = <0x0320>;
|
|
};
|
|
|
|
auxclk5_src_gate_ck: auxclk5_src_gate_ck@324 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-no-wait-gate-clock";
|
|
clocks = <&dpll_core_m3x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0324>;
|
|
};
|
|
|
|
auxclk5_src_mux_ck: auxclk5_src_mux_ck@324 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&sys_clkin_ck>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x0324>;
|
|
};
|
|
|
|
auxclk5_src_ck: auxclk5_src_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&auxclk5_src_gate_ck>, <&auxclk5_src_mux_ck>;
|
|
};
|
|
|
|
auxclk5_ck: auxclk5_ck@324 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&auxclk5_src_ck>;
|
|
ti,bit-shift = <16>;
|
|
ti,max-div = <16>;
|
|
reg = <0x0324>;
|
|
};
|
|
|
|
auxclkreq0_ck: auxclkreq0_ck@210 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
auxclkreq1_ck: auxclkreq1_ck@214 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
auxclkreq2_ck: auxclkreq2_ck@218 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0218>;
|
|
};
|
|
|
|
auxclkreq3_ck: auxclkreq3_ck@21c {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x021c>;
|
|
};
|
|
|
|
auxclkreq4_ck: auxclkreq4_ck@220 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0220>;
|
|
};
|
|
|
|
auxclkreq5_ck: auxclkreq5_ck@224 {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>, <&auxclk5_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0224>;
|
|
};
|
|
};
|
|
|
|
&cm1 {
|
|
mpuss_cm: mpuss_cm@300 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x300 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x300 0x100>;
|
|
|
|
mpuss_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
tesla_cm: tesla_cm@400 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x400 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x400 0x100>;
|
|
|
|
tesla_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
abe_cm: abe_cm@500 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x500 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x500 0x100>;
|
|
|
|
abe_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x6c>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
&cm2 {
|
|
l4_ao_cm: l4_ao_cm@600 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x600 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x600 0x100>;
|
|
|
|
l4_ao_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x1c>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
l3_1_cm: l3_1_cm@700 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x700 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x700 0x100>;
|
|
|
|
l3_1_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
l3_2_cm: l3_2_cm@800 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x800 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x800 0x100>;
|
|
|
|
l3_2_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x14>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
ducati_cm: ducati_cm@900 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x900 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x900 0x100>;
|
|
|
|
ducati_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
l3_dma_cm: l3_dma_cm@a00 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0xa00 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0xa00 0x100>;
|
|
|
|
l3_dma_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
l3_emif_cm: l3_emif_cm@b00 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0xb00 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0xb00 0x100>;
|
|
|
|
l3_emif_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x1c>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
d2d_cm: d2d_cm@c00 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0xc00 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0xc00 0x100>;
|
|
|
|
d2d_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
l4_cfg_cm: l4_cfg_cm@d00 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0xd00 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0xd00 0x100>;
|
|
|
|
l4_cfg_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x14>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
l3_instr_cm: l3_instr_cm@e00 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0xe00 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0xe00 0x100>;
|
|
|
|
l3_instr_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x24>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
ivahd_cm: ivahd_cm@f00 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0xf00 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0xf00 0x100>;
|
|
|
|
ivahd_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0xc>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
iss_cm: iss_cm@1000 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x1000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x1000 0x100>;
|
|
|
|
iss_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0xc>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
l3_dss_cm: l3_dss_cm@1100 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x1100 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x1100 0x100>;
|
|
|
|
l3_dss_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
l3_gfx_cm: l3_gfx_cm@1200 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x1200 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x1200 0x100>;
|
|
|
|
l3_gfx_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
l3_init_cm: l3_init_cm@1300 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x1300 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x1300 0x100>;
|
|
|
|
l3_init_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0xc4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
l4_per_cm: l4_per_cm@1400 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x1400 0x200>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x1400 0x200>;
|
|
|
|
l4_per_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x144>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
};
|
|
|
|
&prm {
|
|
l4_wkup_cm: l4_wkup_cm@1800 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x1800 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x1800 0x100>;
|
|
|
|
l4_wkup_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x5c>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
|
|
emu_sys_cm: emu_sys_cm@1a00 {
|
|
compatible = "ti,omap4-cm";
|
|
reg = <0x1a00 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x1a00 0x100>;
|
|
|
|
emu_sys_clkctrl: clk@20 {
|
|
compatible = "ti,clkctrl";
|
|
reg = <0x20 0x4>;
|
|
#clock-cells = <2>;
|
|
};
|
|
};
|
|
};
|