342 lines
6.2 KiB
Plaintext
342 lines
6.2 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Device tree file for ZII's SSMB SPU3 board
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*
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* SSMB - SPU3 Switch Management Board
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* SPU - Seat Power Unit
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*
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* Copyright (C) 2015, 2016 Zodiac Inflight Innovations
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*
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* Based on an original 'vf610-twr.dts' which is Copyright 2015,
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* Freescale Semiconductor, Inc.
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*/
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/dts-v1/;
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#include "vf610.dtsi"
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/ {
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model = "ZII VF610 SSMB SPU3 Board";
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compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610";
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chosen {
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stdout-path = &uart0;
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};
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memory@80000000 {
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reg = <0x80000000 0x20000000>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&pinctrl_leds_debug>;
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pinctrl-names = "default";
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led-debug {
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label = "zii:green:debug1";
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gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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max-brightness = <1>;
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};
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};
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reg_vcc_3v3_mcu: regulator {
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compatible = "regulator-fixed";
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regulator-name = "vcc_3v3_mcu";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&adc0 {
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vref-supply = <®_vcc_3v3_mcu>;
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status = "okay";
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};
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&adc1 {
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vref-supply = <®_vcc_3v3_mcu>;
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status = "okay";
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};
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&dspi1 {
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bus-num = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dspi1>;
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/*
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* Some SPU3s come with SPI-NOR chip DNPed, so we leave this
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* node disabled by default and rely on bootloader to enable
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* it when appropriate.
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*/
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status = "disabled";
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m25p128@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "m25p128", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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partition@0 {
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label = "m25p128-0";
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reg = <0x0 0x01000000>;
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};
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};
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};
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&edma0 {
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status = "okay";
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};
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&edma1 {
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status = "okay";
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};
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&esdhc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc0>;
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bus-width = <8>;
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non-removable;
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no-1-8-v;
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keep-power-in-suspend;
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status = "okay";
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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bus-width = <4>;
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status = "okay";
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};
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&fec1 {
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phy-mode = "rmii";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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status = "okay";
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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mdio1: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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status = "okay";
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switch0: switch0@0 {
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compatible = "marvell,mv88e6190";
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pinctrl-0 = <&pinctrl_gpio_switch0>;
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pinctrl-names = "default";
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reg = <0>;
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eeprom-length = <65536>;
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reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
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interrupt-parent = <&gpio3>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "cpu";
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ethernet = <&fec1>;
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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port@1 {
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reg = <1>;
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label = "eth_cu_1000_1";
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};
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port@2 {
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reg = <2>;
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label = "eth_cu_1000_2";
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};
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port@3 {
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reg = <3>;
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label = "eth_cu_1000_3";
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};
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port@4 {
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reg = <4>;
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label = "eth_cu_1000_4";
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};
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port@5 {
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reg = <5>;
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label = "eth_cu_1000_5";
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};
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port@6 {
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reg = <6>;
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label = "eth_cu_1000_6";
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};
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};
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};
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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status = "okay";
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gpio6: pca9505@22 {
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compatible = "nxp,pca9554";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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lm75@48 {
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compatible = "national,lm75";
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reg = <0x48>;
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};
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at24c04@50 {
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compatible = "atmel,24c04";
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reg = <0x50>;
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label = "nameplate";
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};
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at24c04@52 {
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compatible = "atmel,24c04";
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reg = <0x52>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart0>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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rave-sp {
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compatible = "zii,rave-sp-rdu2";
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current-speed = <1000000>;
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#address-cells = <1>;
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#size-cells = <1>;
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watchdog {
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compatible = "zii,rave-sp-watchdog";
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};
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eeprom@a3 {
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compatible = "zii,rave-sp-eeprom";
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reg = <0xa3 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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zii,eeprom-name = "main-eeprom";
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};
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};
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};
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&iomuxc {
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pinctrl_dspi1: dspi1grp {
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fsl,pins = <
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VF610_PAD_PTD5__DSPI1_CS0 0x1182
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VF610_PAD_PTD4__DSPI1_CS1 0x1182
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VF610_PAD_PTC6__DSPI1_SIN 0x1181
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VF610_PAD_PTC7__DSPI1_SOUT 0x1182
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VF610_PAD_PTC8__DSPI1_SCK 0x1182
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>;
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};
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pinctrl_esdhc0: esdhc0grp {
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fsl,pins = <
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VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
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VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
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VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
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VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
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VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
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VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
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VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
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VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
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VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
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VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
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>;
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};
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pinctrl_esdhc1: esdhc1grp {
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fsl,pins = <
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VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
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VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
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VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
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VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
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VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
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VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
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>;
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};
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pinctrl_fec1: fec1grp {
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fsl,pins = <
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VF610_PAD_PTA6__RMII_CLKIN 0x30d1
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VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
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VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
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VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
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VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
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VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
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VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
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VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
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VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
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VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
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>;
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};
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pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
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fsl,pins = <
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VF610_PAD_PTE2__GPIO_107 0x31c2
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VF610_PAD_PTB28__GPIO_98 0x219d
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>;
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};
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pinctrl_i2c0: i2c0grp {
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fsl,pins = <
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VF610_PAD_PTB14__I2C0_SCL 0x37ff
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VF610_PAD_PTB15__I2C0_SDA 0x37ff
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>;
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};
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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VF610_PAD_PTB16__I2C1_SCL 0x37ff
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VF610_PAD_PTB17__I2C1_SDA 0x37ff
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>;
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};
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pinctrl_leds_debug: pinctrl-leds-debug {
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fsl,pins = <
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VF610_PAD_PTD3__GPIO_82 0x31c2
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>;
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};
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pinctrl_uart0: uart0grp {
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fsl,pins = <
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VF610_PAD_PTB10__UART0_TX 0x21a2
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VF610_PAD_PTB11__UART0_RX 0x21a1
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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VF610_PAD_PTB23__UART1_TX 0x21a2
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VF610_PAD_PTB24__UART1_RX 0x21a1
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>;
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};
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};
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