330 lines
7.2 KiB
C
330 lines
7.2 KiB
C
/*
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* linux/arch/arm/mach-ebsa110/core.c
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*
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* Copyright (C) 1998-2001 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Extra MM routines for the EBSA-110 architecture
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*/
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/interrupt.h>
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#include <linux/serial_8250.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/setup.h>
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#include <asm/mach-types.h>
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#include <asm/pgtable.h>
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#include <asm/page.h>
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#include <asm/system_misc.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/irq.h>
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#include <asm/mach/map.h>
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#include <asm/mach/time.h>
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#include "core.h"
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static void ebsa110_mask_irq(struct irq_data *d)
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{
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__raw_writeb(1 << d->irq, IRQ_MCLR);
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}
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static void ebsa110_unmask_irq(struct irq_data *d)
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{
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__raw_writeb(1 << d->irq, IRQ_MSET);
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}
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static struct irq_chip ebsa110_irq_chip = {
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.irq_ack = ebsa110_mask_irq,
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.irq_mask = ebsa110_mask_irq,
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.irq_unmask = ebsa110_unmask_irq,
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};
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static void __init ebsa110_init_irq(void)
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{
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unsigned long flags;
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unsigned int irq;
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local_irq_save(flags);
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__raw_writeb(0xff, IRQ_MCLR);
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__raw_writeb(0x55, IRQ_MSET);
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__raw_writeb(0x00, IRQ_MSET);
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if (__raw_readb(IRQ_MASK) != 0x55)
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while (1);
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__raw_writeb(0xff, IRQ_MCLR); /* clear all interrupt enables */
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local_irq_restore(flags);
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for (irq = 0; irq < NR_IRQS; irq++) {
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irq_set_chip_and_handler(irq, &ebsa110_irq_chip,
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handle_level_irq);
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irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
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}
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}
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static struct map_desc ebsa110_io_desc[] __initdata = {
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/*
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* sparse external-decode ISAIO space
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*/
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{ /* IRQ_STAT/IRQ_MCLR */
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.virtual = (unsigned long)IRQ_STAT,
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.pfn = __phys_to_pfn(TRICK4_PHYS),
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.length = TRICK4_SIZE,
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.type = MT_DEVICE
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}, { /* IRQ_MASK/IRQ_MSET */
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.virtual = (unsigned long)IRQ_MASK,
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.pfn = __phys_to_pfn(TRICK3_PHYS),
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.length = TRICK3_SIZE,
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.type = MT_DEVICE
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}, { /* SOFT_BASE */
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.virtual = (unsigned long)SOFT_BASE,
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.pfn = __phys_to_pfn(TRICK1_PHYS),
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.length = TRICK1_SIZE,
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.type = MT_DEVICE
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}, { /* PIT_BASE */
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.virtual = (unsigned long)PIT_BASE,
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.pfn = __phys_to_pfn(TRICK0_PHYS),
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.length = TRICK0_SIZE,
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.type = MT_DEVICE
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},
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/*
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* self-decode ISAIO space
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*/
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{
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.virtual = ISAIO_BASE,
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.pfn = __phys_to_pfn(ISAIO_PHYS),
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.length = ISAIO_SIZE,
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.type = MT_DEVICE
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}, {
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.virtual = ISAMEM_BASE,
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.pfn = __phys_to_pfn(ISAMEM_PHYS),
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.length = ISAMEM_SIZE,
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.type = MT_DEVICE
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}
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};
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static void __init ebsa110_map_io(void)
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{
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iotable_init(ebsa110_io_desc, ARRAY_SIZE(ebsa110_io_desc));
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}
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static void __iomem *ebsa110_ioremap_caller(phys_addr_t cookie, size_t size,
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unsigned int flags, void *caller)
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{
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return (void __iomem *)cookie;
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}
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static void ebsa110_iounmap(volatile void __iomem *io_addr)
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{}
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static void __init ebsa110_init_early(void)
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{
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arch_ioremap_caller = ebsa110_ioremap_caller;
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arch_iounmap = ebsa110_iounmap;
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}
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#define PIT_CTRL (PIT_BASE + 0x0d)
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#define PIT_T2 (PIT_BASE + 0x09)
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#define PIT_T1 (PIT_BASE + 0x05)
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#define PIT_T0 (PIT_BASE + 0x01)
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/*
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* This is the rate at which your MCLK signal toggles (in Hz)
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* This was measured on a 10 digit frequency counter sampling
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* over 1 second.
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*/
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#define MCLK 47894000
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/*
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* This is the rate at which the PIT timers get clocked
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*/
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#define CLKBY7 (MCLK / 7)
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/*
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* This is the counter value. We tick at 200Hz on this platform.
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*/
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#define COUNT ((CLKBY7 + (HZ / 2)) / HZ)
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/*
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* Get the time offset from the system PIT. Note that if we have missed an
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* interrupt, then the PIT counter will roll over (ie, be negative).
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* This actually works out to be convenient.
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*/
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static u32 ebsa110_gettimeoffset(void)
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{
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unsigned long offset, count;
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__raw_writeb(0x40, PIT_CTRL);
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count = __raw_readb(PIT_T1);
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count |= __raw_readb(PIT_T1) << 8;
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/*
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* If count > COUNT, make the number negative.
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*/
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if (count > COUNT)
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count |= 0xffff0000;
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offset = COUNT;
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offset -= count;
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/*
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* `offset' is in units of timer counts. Convert
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* offset to units of microseconds.
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*/
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offset = offset * (1000000 / HZ) / COUNT;
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return offset * 1000;
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}
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static irqreturn_t
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ebsa110_timer_interrupt(int irq, void *dev_id)
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{
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u32 count;
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/* latch and read timer 1 */
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__raw_writeb(0x40, PIT_CTRL);
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count = __raw_readb(PIT_T1);
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count |= __raw_readb(PIT_T1) << 8;
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count += COUNT;
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__raw_writeb(count & 0xff, PIT_T1);
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__raw_writeb(count >> 8, PIT_T1);
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timer_tick();
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return IRQ_HANDLED;
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}
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static struct irqaction ebsa110_timer_irq = {
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.name = "EBSA110 Timer Tick",
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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.handler = ebsa110_timer_interrupt,
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};
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/*
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* Set up timer interrupt.
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*/
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void __init ebsa110_timer_init(void)
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{
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arch_gettimeoffset = ebsa110_gettimeoffset;
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/*
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* Timer 1, mode 2, LSB/MSB
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*/
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__raw_writeb(0x70, PIT_CTRL);
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__raw_writeb(COUNT & 0xff, PIT_T1);
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__raw_writeb(COUNT >> 8, PIT_T1);
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setup_irq(IRQ_EBSA110_TIMER0, &ebsa110_timer_irq);
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}
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static struct plat_serial8250_port serial_platform_data[] = {
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{
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.iobase = 0x3f8,
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.irq = 1,
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.uartclk = 1843200,
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.regshift = 0,
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.iotype = UPIO_PORT,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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},
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{
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.iobase = 0x2f8,
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.irq = 2,
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.uartclk = 1843200,
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.regshift = 0,
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.iotype = UPIO_PORT,
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.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
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},
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{ },
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};
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static struct platform_device serial_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_PLATFORM,
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.dev = {
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.platform_data = serial_platform_data,
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},
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};
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static struct resource am79c961_resources[] = {
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{
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.start = 0x220,
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.end = 0x238,
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.flags = IORESOURCE_IO,
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}, {
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.start = IRQ_EBSA110_ETHERNET,
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.end = IRQ_EBSA110_ETHERNET,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device am79c961_device = {
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.name = "am79c961",
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.id = -1,
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.num_resources = ARRAY_SIZE(am79c961_resources),
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.resource = am79c961_resources,
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};
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static struct platform_device *ebsa110_devices[] = {
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&serial_device,
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&am79c961_device,
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};
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/*
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* EBSA110 idling methodology:
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*
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* We can not execute the "wait for interrupt" instruction since that
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* will stop our MCLK signal (which provides the clock for the glue
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* logic, and therefore the timer interrupt).
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*
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* Instead, we spin, polling the IRQ_STAT register for the occurrence
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* of any interrupt with core clock down to the memory clock.
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*/
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static void ebsa110_idle(void)
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{
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const char *irq_stat = (char *)0xff000000;
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/* disable clock switching */
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asm volatile ("mcr p15, 0, ip, c15, c2, 2" : : : "cc");
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/* wait for an interrupt to occur */
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while (!*irq_stat);
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/* enable clock switching */
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asm volatile ("mcr p15, 0, ip, c15, c1, 2" : : : "cc");
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}
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static int __init ebsa110_init(void)
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{
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arm_pm_idle = ebsa110_idle;
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return platform_add_devices(ebsa110_devices, ARRAY_SIZE(ebsa110_devices));
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}
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arch_initcall(ebsa110_init);
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static void ebsa110_restart(enum reboot_mode mode, const char *cmd)
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{
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soft_restart(0x80000000);
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}
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MACHINE_START(EBSA110, "EBSA110")
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/* Maintainer: Russell King */
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.atag_offset = 0x400,
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.reserve_lp0 = 1,
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.reserve_lp2 = 1,
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.map_io = ebsa110_map_io,
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.init_early = ebsa110_init_early,
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.init_irq = ebsa110_init_irq,
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.init_time = ebsa110_timer_init,
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.restart = ebsa110_restart,
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MACHINE_END
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