354 lines
15 KiB
C
354 lines
15 KiB
C
#ifndef __PARISC_PATPDC_H
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#define __PARISC_PATPDC_H
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright 2000 (c) Hewlett Packard (Paul Bame <bame()spam.parisc-linux.org>)
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* Copyright 2000,2004 (c) Grant Grundler <grundler()nahspam.parisc-linux.org>
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*/
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#define PDC_PAT_CELL 64L /* Interface for gaining and
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* manipulatin g cell state within PD */
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#define PDC_PAT_CELL_GET_NUMBER 0L /* Return Cell number */
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#define PDC_PAT_CELL_GET_INFO 1L /* Returns info about Cell */
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#define PDC_PAT_CELL_MODULE 2L /* Returns info about Module */
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#define PDC_PAT_CELL_SET_ATTENTION 9L /* Set Cell Attention indicator */
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#define PDC_PAT_CELL_NUMBER_TO_LOC 10L /* Cell Number -> Location */
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#define PDC_PAT_CELL_WALK_FABRIC 11L /* Walk the Fabric */
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#define PDC_PAT_CELL_GET_RDT_SIZE 12L /* Return Route Distance Table Sizes */
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#define PDC_PAT_CELL_GET_RDT 13L /* Return Route Distance Tables */
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#define PDC_PAT_CELL_GET_LOCAL_PDH_SZ 14L /* Read Local PDH Buffer Size */
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#define PDC_PAT_CELL_SET_LOCAL_PDH 15L /* Write Local PDH Buffer */
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#define PDC_PAT_CELL_GET_REMOTE_PDH_SZ 16L /* Return Remote PDH Buffer Size */
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#define PDC_PAT_CELL_GET_REMOTE_PDH 17L /* Read Remote PDH Buffer */
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#define PDC_PAT_CELL_GET_DBG_INFO 128L /* Return DBG Buffer Info */
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#define PDC_PAT_CELL_CHANGE_ALIAS 129L /* Change Non-Equivalent Alias Chacking */
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/*
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** Arg to PDC_PAT_CELL_MODULE memaddr[4]
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**
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** Addresses on the Merced Bus != all Runway Bus addresses.
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** This is intended for programming SBA/LBA chips range registers.
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*/
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#define IO_VIEW 0UL
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#define PA_VIEW 1UL
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/* PDC_PAT_CELL_MODULE entity type values */
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#define PAT_ENTITY_CA 0 /* central agent */
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#define PAT_ENTITY_PROC 1 /* processor */
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#define PAT_ENTITY_MEM 2 /* memory controller */
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#define PAT_ENTITY_SBA 3 /* system bus adapter */
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#define PAT_ENTITY_LBA 4 /* local bus adapter */
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#define PAT_ENTITY_PBC 5 /* processor bus converter */
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#define PAT_ENTITY_XBC 6 /* crossbar fabric connect */
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#define PAT_ENTITY_RC 7 /* fabric interconnect */
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/* PDC_PAT_CELL_MODULE address range type values */
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#define PAT_PBNUM 0 /* PCI Bus Number */
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#define PAT_LMMIO 1 /* < 4G MMIO Space */
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#define PAT_GMMIO 2 /* > 4G MMIO Space */
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#define PAT_NPIOP 3 /* Non Postable I/O Port Space */
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#define PAT_PIOP 4 /* Postable I/O Port Space */
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#define PAT_AHPA 5 /* Addional HPA Space */
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#define PAT_UFO 6 /* HPA Space (UFO for Mariposa) */
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#define PAT_GNIP 7 /* GNI Reserved Space */
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/* PDC PAT CHASSIS LOG -- Platform logging & forward progress functions */
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#define PDC_PAT_CHASSIS_LOG 65L
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#define PDC_PAT_CHASSIS_WRITE_LOG 0L /* Write Log Entry */
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#define PDC_PAT_CHASSIS_READ_LOG 1L /* Read Log Entry */
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/* PDC PAT CPU -- CPU configuration within the protection domain */
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#define PDC_PAT_CPU 67L
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#define PDC_PAT_CPU_INFO 0L /* Return CPU config info */
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#define PDC_PAT_CPU_DELETE 1L /* Delete CPU */
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#define PDC_PAT_CPU_ADD 2L /* Add CPU */
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#define PDC_PAT_CPU_GET_NUMBER 3L /* Return CPU Number */
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#define PDC_PAT_CPU_GET_HPA 4L /* Return CPU HPA */
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#define PDC_PAT_CPU_STOP 5L /* Stop CPU */
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#define PDC_PAT_CPU_RENDEZVOUS 6L /* Rendezvous CPU */
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#define PDC_PAT_CPU_GET_CLOCK_INFO 7L /* Return CPU Clock info */
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#define PDC_PAT_CPU_GET_RENDEZVOUS_STATE 8L /* Return Rendezvous State */
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#define PDC_PAT_CPU_PLUNGE_FABRIC 128L /* Plunge Fabric */
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#define PDC_PAT_CPU_UPDATE_CACHE_CLEANSING 129L /* Manipulate Cache
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* Cleansing Mode */
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/* PDC PAT EVENT -- Platform Events */
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#define PDC_PAT_EVENT 68L
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#define PDC_PAT_EVENT_GET_CAPS 0L /* Get Capabilities */
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#define PDC_PAT_EVENT_SET_MODE 1L /* Set Notification Mode */
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#define PDC_PAT_EVENT_SCAN 2L /* Scan Event */
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#define PDC_PAT_EVENT_HANDLE 3L /* Handle Event */
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#define PDC_PAT_EVENT_GET_NB_CALL 4L /* Get Non-Blocking call Args */
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/* PDC PAT HPMC -- Cause processor to go into spin loop, and wait
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* for wake up from Monarch Processor.
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*/
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#define PDC_PAT_HPMC 70L
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#define PDC_PAT_HPMC_RENDEZ_CPU 0L /* go into spin loop */
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#define PDC_PAT_HPMC_SET_PARAMS 1L /* Allows OS to specify intr which PDC
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* will use to interrupt OS during
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* machine check rendezvous */
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/* parameters for PDC_PAT_HPMC_SET_PARAMS: */
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#define HPMC_SET_PARAMS_INTR 1L /* Rendezvous Interrupt */
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#define HPMC_SET_PARAMS_WAKE 2L /* Wake up processor */
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/* PDC PAT IO -- On-line services for I/O modules */
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#define PDC_PAT_IO 71L
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#define PDC_PAT_IO_GET_SLOT_STATUS 5L /* Get Slot Status Info*/
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#define PDC_PAT_IO_GET_LOC_FROM_HARDWARE 6L /* Get Physical Location from */
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/* Hardware Path */
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#define PDC_PAT_IO_GET_HARDWARE_FROM_LOC 7L /* Get Hardware Path from
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* Physical Location */
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#define PDC_PAT_IO_GET_PCI_CONFIG_FROM_HW 11L /* Get PCI Configuration
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* Address from Hardware Path */
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#define PDC_PAT_IO_GET_HW_FROM_PCI_CONFIG 12L /* Get Hardware Path
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* from PCI Configuration Address */
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#define PDC_PAT_IO_READ_HOST_BRIDGE_INFO 13L /* Read Host Bridge State Info */
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#define PDC_PAT_IO_CLEAR_HOST_BRIDGE_INFO 14L /* Clear Host Bridge State Info*/
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#define PDC_PAT_IO_GET_PCI_ROUTING_TABLE_SIZE 15L /* Get PCI INT Routing Table
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* Size */
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#define PDC_PAT_IO_GET_PCI_ROUTING_TABLE 16L /* Get PCI INT Routing Table */
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#define PDC_PAT_IO_GET_HINT_TABLE_SIZE 17L /* Get Hint Table Size */
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#define PDC_PAT_IO_GET_HINT_TABLE 18L /* Get Hint Table */
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#define PDC_PAT_IO_PCI_CONFIG_READ 19L /* PCI Config Read */
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#define PDC_PAT_IO_PCI_CONFIG_WRITE 20L /* PCI Config Write */
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#define PDC_PAT_IO_GET_NUM_IO_SLOTS 21L /* Get Number of I/O Bay Slots in
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* Cabinet */
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#define PDC_PAT_IO_GET_LOC_IO_SLOTS 22L /* Get Physical Location of I/O */
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/* Bay Slots in Cabinet */
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#define PDC_PAT_IO_BAY_STATUS_INFO 28L /* Get I/O Bay Slot Status Info */
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#define PDC_PAT_IO_GET_PROC_VIEW 29L /* Get Processor view of IO address */
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#define PDC_PAT_IO_PROG_SBA_DIR_RANGE 30L /* Program directed range */
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/* PDC PAT MEM -- Manage memory page deallocation */
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#define PDC_PAT_MEM 72L
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#define PDC_PAT_MEM_PD_INFO 0L /* Return PDT info for PD */
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#define PDC_PAT_MEM_PD_CLEAR 1L /* Clear PDT for PD */
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#define PDC_PAT_MEM_PD_READ 2L /* Read PDT entries for PD */
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#define PDC_PAT_MEM_PD_RESET 3L /* Reset clear bit for PD */
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#define PDC_PAT_MEM_CELL_INFO 5L /* Return PDT info For Cell */
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#define PDC_PAT_MEM_CELL_CLEAR 6L /* Clear PDT For Cell */
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#define PDC_PAT_MEM_CELL_READ 7L /* Read PDT entries For Cell */
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#define PDC_PAT_MEM_CELL_RESET 8L /* Reset clear bit For Cell */
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#define PDC_PAT_MEM_SETGM 9L /* Set Good Memory value */
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#define PDC_PAT_MEM_ADD_PAGE 10L /* ADDs a page to the cell */
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#define PDC_PAT_MEM_ADDRESS 11L /* Get Physical Location From */
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/* Memory Address */
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#define PDC_PAT_MEM_GET_TXT_SIZE 12L /* Get Formatted Text Size */
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#define PDC_PAT_MEM_GET_PD_TXT 13L /* Get PD Formatted Text */
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#define PDC_PAT_MEM_GET_CELL_TXT 14L /* Get Cell Formatted Text */
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#define PDC_PAT_MEM_RD_STATE_INFO 15L /* Read Mem Module State Info*/
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#define PDC_PAT_MEM_CLR_STATE_INFO 16L /*Clear Mem Module State Info*/
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#define PDC_PAT_MEM_CLEAN_RANGE 128L /*Clean Mem in specific range*/
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#define PDC_PAT_MEM_GET_TBL_SIZE 131L /* Get Memory Table Size */
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#define PDC_PAT_MEM_GET_TBL 132L /* Get Memory Table */
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/* PDC PAT NVOLATILE -- Access Non-Volatile Memory */
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#define PDC_PAT_NVOLATILE 73L
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#define PDC_PAT_NVOLATILE_READ 0L /* Read Non-Volatile Memory */
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#define PDC_PAT_NVOLATILE_WRITE 1L /* Write Non-Volatile Memory */
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#define PDC_PAT_NVOLATILE_GET_SIZE 2L /* Return size of NVM */
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#define PDC_PAT_NVOLATILE_VERIFY 3L /* Verify contents of NVM */
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#define PDC_PAT_NVOLATILE_INIT 4L /* Initialize NVM */
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/* PDC PAT PD */
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#define PDC_PAT_PD 74L /* Protection Domain Info */
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#define PDC_PAT_PD_GET_ADDR_MAP 0L /* Get Address Map */
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/* PDC_PAT_PD_GET_ADDR_MAP entry types */
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#define PAT_MEMORY_DESCRIPTOR 1
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/* PDC_PAT_PD_GET_ADDR_MAP memory types */
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#define PAT_MEMTYPE_MEMORY 0
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#define PAT_MEMTYPE_FIRMWARE 4
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/* PDC_PAT_PD_GET_ADDR_MAP memory usage */
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#define PAT_MEMUSE_GENERAL 0
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#define PAT_MEMUSE_GI 128
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#define PAT_MEMUSE_GNI 129
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#ifdef CONFIG_64BIT
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#define is_pdc_pat() (PDC_TYPE_PAT == pdc_type)
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extern int pdc_pat_get_irt_size(unsigned long *num_entries, unsigned long cell_num);
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extern int pdc_pat_get_irt(void *r_addr, unsigned long cell_num);
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#else /* ! CONFIG_64BIT */
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/* No PAT support for 32-bit kernels...sorry */
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#define is_pdc_pat() (0)
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#define pdc_pat_get_irt_size(num_entries, cell_numn) PDC_BAD_PROC
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#define pdc_pat_get_irt(r_addr, cell_num) PDC_BAD_PROC
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#endif /* ! CONFIG_64BIT */
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struct pdc_pat_cell_num {
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unsigned long cell_num;
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unsigned long cell_loc;
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};
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struct pdc_pat_cpu_num {
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unsigned long cpu_num;
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unsigned long cpu_loc;
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};
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struct pdc_pat_mem_retinfo { /* PDC_PAT_MEM/PDC_PAT_MEM_PD_INFO (return info) */
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unsigned int ke; /* bit 0: memory inside good memory? */
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unsigned int current_pdt_entries:16;
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unsigned int max_pdt_entries:16;
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unsigned long Cs_bitmap;
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unsigned long Ic_bitmap;
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unsigned long good_mem;
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unsigned long first_dbe_loc; /* first location of double bit error */
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unsigned long clear_time; /* last PDT clear time (since Jan 1970) */
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};
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struct pdc_pat_mem_cell_pdt_retinfo { /* PDC_PAT_MEM/PDC_PAT_MEM_CELL_INFO */
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u64 reserved:32;
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u64 cs:1; /* clear status: cleared since the last call? */
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u64 current_pdt_entries:15;
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u64 ic:1; /* interleaving had to be changed ? */
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u64 max_pdt_entries:15;
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unsigned long good_mem;
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unsigned long first_dbe_loc; /* first location of double bit error */
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unsigned long clear_time; /* last PDT clear time (since Jan 1970) */
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};
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struct pdc_pat_mem_read_pd_retinfo { /* PDC_PAT_MEM/PDC_PAT_MEM_PD_READ */
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unsigned long actual_count_bytes;
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unsigned long pdt_entries;
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};
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struct pdc_pat_mem_phys_mem_location { /* PDC_PAT_MEM/PDC_PAT_MEM_ADDRESS */
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u64 cabinet:8;
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u64 ign1:8;
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u64 ign2:8;
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u64 cell_slot:8;
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u64 ign3:8;
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u64 dimm_slot:8; /* DIMM slot, e.g. 0x1A, 0x2B, show user hex value! */
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u64 ign4:8;
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u64 source:4; /* for mem: always 0x07 */
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u64 source_detail:4; /* for mem: always 0x04 (SIMM or DIMM) */
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};
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struct pdc_pat_pd_addr_map_entry {
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unsigned char entry_type; /* 1 = Memory Descriptor Entry Type */
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unsigned char reserve1[5];
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unsigned char memory_type;
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unsigned char memory_usage;
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unsigned long paddr;
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unsigned int pages; /* Length in 4K pages */
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unsigned int reserve2;
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unsigned long cell_map;
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};
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/********************************************************************
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* PDC_PAT_CELL[Return Cell Module] memaddr[0] conf_base_addr
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* ----------------------------------------------------------
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* Bit 0 to 51 - conf_base_addr
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* Bit 52 to 62 - reserved
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* Bit 63 - endianess bit
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********************************************************************/
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#define PAT_GET_CBA(value) ((value) & 0xfffffffffffff000UL)
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/********************************************************************
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* PDC_PAT_CELL[Return Cell Module] memaddr[1] mod_info
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* ----------------------------------------------------
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* Bit 0 to 7 - entity type
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* 0 = central agent, 1 = processor,
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* 2 = memory controller, 3 = system bus adapter,
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* 4 = local bus adapter, 5 = processor bus converter,
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* 6 = crossbar fabric connect, 7 = fabric interconnect,
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* 8 to 254 reserved, 255 = unknown.
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* Bit 8 to 15 - DVI
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* Bit 16 to 23 - IOC functions
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* Bit 24 to 39 - reserved
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* Bit 40 to 63 - mod_pages
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* number of 4K pages a module occupies starting at conf_base_addr
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********************************************************************/
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#define PAT_GET_ENTITY(value) (((value) >> 56) & 0xffUL)
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#define PAT_GET_DVI(value) (((value) >> 48) & 0xffUL)
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#define PAT_GET_IOC(value) (((value) >> 40) & 0xffUL)
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#define PAT_GET_MOD_PAGES(value) ((value) & 0xffffffUL)
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/*
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** PDC_PAT_CELL_GET_INFO return block
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*/
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typedef struct pdc_pat_cell_info_rtn_block {
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unsigned long cpu_info;
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unsigned long cell_info;
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unsigned long cell_location;
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unsigned long reo_location;
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unsigned long mem_size;
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unsigned long dimm_status;
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unsigned long pdc_rev;
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unsigned long fabric_info0;
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unsigned long fabric_info1;
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unsigned long fabric_info2;
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unsigned long fabric_info3;
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unsigned long reserved[21];
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} pdc_pat_cell_info_rtn_block_t;
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/* FIXME: mod[508] should really be a union of the various mod components */
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struct pdc_pat_cell_mod_maddr_block { /* PDC_PAT_CELL_MODULE */
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unsigned long cba; /* func 0 cfg space address */
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unsigned long mod_info; /* module information */
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unsigned long mod_location; /* physical location of the module */
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struct hardware_path mod_path; /* module path (device path - layers) */
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unsigned long mod[508]; /* PAT cell module components */
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} __attribute__((aligned(8))) ;
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typedef struct pdc_pat_cell_mod_maddr_block pdc_pat_cell_mod_maddr_block_t;
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extern int pdc_pat_chassis_send_log(unsigned long status, unsigned long data);
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extern int pdc_pat_cell_get_number(struct pdc_pat_cell_num *cell_info);
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extern int pdc_pat_cell_module(unsigned long *actcnt, unsigned long ploc, unsigned long mod, unsigned long view_type, void *mem_addr);
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extern int pdc_pat_cell_num_to_loc(void *, unsigned long);
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extern int pdc_pat_cpu_get_number(struct pdc_pat_cpu_num *cpu_info, unsigned long hpa);
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extern int pdc_pat_pd_get_addr_map(unsigned long *actual_len, void *mem_addr, unsigned long count, unsigned long offset);
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extern int pdc_pat_io_pci_cfg_read(unsigned long pci_addr, int pci_size, u32 *val);
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extern int pdc_pat_io_pci_cfg_write(unsigned long pci_addr, int pci_size, u32 val);
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extern int pdc_pat_mem_pdt_info(struct pdc_pat_mem_retinfo *rinfo);
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extern int pdc_pat_mem_pdt_cell_info(struct pdc_pat_mem_cell_pdt_retinfo *rinfo,
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unsigned long cell);
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extern int pdc_pat_mem_read_cell_pdt(struct pdc_pat_mem_read_pd_retinfo *pret,
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unsigned long *pdt_entries_ptr, unsigned long max_entries);
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extern int pdc_pat_mem_read_pd_pdt(struct pdc_pat_mem_read_pd_retinfo *pret,
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unsigned long *pdt_entries_ptr, unsigned long count,
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unsigned long offset);
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extern int pdc_pat_mem_get_dimm_phys_location(
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struct pdc_pat_mem_phys_mem_location *pret,
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unsigned long phys_addr);
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#endif /* __ASSEMBLY__ */
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#endif /* ! __PARISC_PATPDC_H */
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