2003 lines
53 KiB
C
2003 lines
53 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2019 MediaTek Inc.
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*/
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/*
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*
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* Filename:
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* ---------
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* mtk_auxadc.c
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*
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* Project:
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* --------
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* Android_Software
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*
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* Description:
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* ------------
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* This Module defines functions of AUXADC common code
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*
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* Author:
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* -------
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* Zhong Wang
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*
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*/
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#include <linux/init.h> /* For init/exit macros */
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#include <linux/module.h> /* For MODULE_ marcros */
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#include <linux/fs.h>
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#include <linux/device.h>
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#include <linux/interrupt.h>
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#include <linux/spinlock.h>
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include <linux/kdev_t.h>
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#include <linux/fs.h>
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#include <linux/cdev.h>
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#include <linux/delay.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/proc_fs.h>
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#include <linux/kthread.h>
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#include <linux/seq_file.h>
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#include <linux/uaccess.h>
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#include <linux/io.h>
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#include <asm/irq.h>
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#include <mt-plat/sync_write.h>
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#include <mt-plat/mtk_devinfo.h>
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#include "mtk_auxadc.h"
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#include "mtk_auxadc_hw.h"
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#include <linux/of.h>
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#include <linux/of_address.h>
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static struct clk *clk_auxadc;
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#if defined(AUXADC_CLK_CTR)
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static struct clk *clk_top_auxadc1;
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static struct clk *clk_top_auxadc2;
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static struct clk *clk_top_aux_tp;
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#endif
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void __iomem *auxadc_base;
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void __iomem *auxadc_apmix_base;
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#if defined(EFUSE_CALI)
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void __iomem *auxadc_efuse_base;
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#endif
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#include <linux/clk.h>
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#define READ_REGISTER_UINT16(reg) (*(unsigned short * const)(reg))
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#define INREG16(x) \
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READ_REGISTER_UINT16((unsigned short *)((void *)(x)))
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#define DRV_Reg16(addr) INREG16(addr)
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#define DRV_Reg(addr) DRV_Reg16(addr)
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#if defined(AUXADC_SPM)
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#define READ_REGISTER_UINT32(reg) (*(unsigned int * const)(reg))
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#define INREG32(x) READ_REGISTER_UINT32((unsigned int *)((void *)(x)))
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#define DRV_Reg32(addr) INREG32(addr)
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#endif
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/******************************************************/
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#define DRV_ClearBits(addr, data) {\
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unsigned short temp;\
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temp = DRV_Reg16(addr);\
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temp &= ~(data);\
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mt_reg_sync_writew(temp, addr);\
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}
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#define DRV_SetBits(addr, data) {\
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unsigned short temp;\
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temp = DRV_Reg16(addr);\
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temp |= (data);\
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mt_reg_sync_writew(temp, addr);\
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}
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#define DRV_SetData(addr, bitmask, value) {\
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unsigned short temp;\
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temp = (~(bitmask)) & DRV_Reg16(addr);\
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temp |= (value);\
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mt_reg_sync_writew(temp, addr);\
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}
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#define AUXADC_DRV_ClearBits16(addr, data) DRV_ClearBits(addr, data)
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#define AUXADC_DRV_SetBits16(addr, data) DRV_SetBits(addr, data)
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#define AUXADC_DRV_WriteReg16(addr, data) \
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mt_reg_sync_writew(data, addr)
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#define AUXADC_DRV_ReadReg16(addr) DRV_Reg(addr)
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#define AUXADC_DRV_SetData16(addr, bitmask, value) \
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DRV_SetData(addr, bitmask, value)
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#if defined(AUXADC_SPM)
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#define AUXADC_DRV_ReadReg32(addr) DRV_Reg32(addr)
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#endif
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#define AUXADC_CLR_BITS(BS, REG) {\
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unsigned int temp;\
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temp = DRV_Reg32(REG);\
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temp &= ~(BS);\
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mt_reg_sync_writel(temp, REG);\
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}
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#define AUXADC_SET_BITS(BS, REG) {\
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unsigned int temp;\
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temp = DRV_Reg32(REG);\
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temp |= (BS);\
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mt_reg_sync_writel(temp, REG);\
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}
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#define VOLTAGE_FULL_RANGE 1500 /* VA voltage */
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#define AUXADC_PRECISE 4096 /* 12 bits */
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/******************************************************/
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/*****************************************************************************
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* Integrate with NVRAM
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*/
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#define AUXADC_CALI_DEVNAME "mtk-adc-cali"
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#define TAG "[AUXADC]"
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#define TEST_ADC_CALI_PRINT _IO('k', 0)
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#define SET_ADC_CALI_Slop _IOW('k', 1, int)
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#define SET_ADC_CALI_Offset _IOW('k', 2, int)
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#define SET_ADC_CALI_Cal _IOW('k', 3, int)
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#define ADC_CHANNEL_READ _IOW('k', 4, int)
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struct adc_info {
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char channel_name[64];
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int channel_number;
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int reserve1;
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int reserve2;
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int reserve3;
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};
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static struct adc_info g_adc_info[ADC_CHANNEL_MAX];
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static int auxadc_cali_slop[ADC_CHANNEL_MAX] = { 0 };
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static int auxadc_cali_offset[ADC_CHANNEL_MAX] = { 0 };
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static bool g_AUXADC_Cali;
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static int auxadc_cali_cal[1] = { 0 };
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static int auxadc_in_data[2] = { 1, 1 };
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static int auxadc_out_data[2] = { 1, 1 };
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static DEFINE_MUTEX(auxadc_mutex);
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static DEFINE_MUTEX(mutex_get_cali_value);
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static int adc_auto_set;
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#if !defined(CONFIG_AUXADC_NOT_CONTROL_APMIXED_BASE)
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static int adc_rtp_set = 1;
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#endif
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static dev_t auxadc_cali_devno;
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static int auxadc_cali_major;
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static struct cdev *auxadc_cali_cdev;
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static struct class *auxadc_cali_class;
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static struct task_struct *thread;
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static int g_start_debug_thread;
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static int g_adc_init_flag;
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static u32 cali_reg;
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static s32 cali_oe;
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static s32 cali_ge;
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static u32 cali_ge_a;
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static u32 cali_oe_a;
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static u32 gain;
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static void mt_auxadc_update_cali(void)
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{
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cali_oe = 0;
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cali_ge = 0;
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#if defined(EFUSE_CALI)
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#if defined(AUXADC_INDEX)
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cali_reg = get_devinfo_with_index(AUXADC_INDEX);
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#else
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cali_reg = (*(unsigned int *const)(ADC_CALI_EN_A_REG));
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#endif
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if (((cali_reg & ADC_CALI_EN_A_MASK) >> ADC_CALI_EN_A_SHIFT) != 0) {
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cali_oe_a = (cali_reg & ADC_OE_A_MASK) >> ADC_OE_A_SHIFT;
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cali_ge_a = ((cali_reg & ADC_GE_A_MASK) >> ADC_GE_A_SHIFT);
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/* In sw implement guide, ge should div 4096.
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* But we don't do that now due to it will multi 4096 later
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*/
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cali_ge = cali_ge_a - 512;
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cali_oe = cali_oe_a - 512;
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gain = 1 + cali_ge;
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/* In sw implement guide, gain = 1 + GE = 1 + cali_ge / 4096,
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* we doen't use the variable here
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*/
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}
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#endif
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}
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static void mt_auxadc_get_cali_data(unsigned int rawdata, int data[4],
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bool enable_cali)
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{
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if (enable_cali == true) {
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#if defined(EFUSE_CALI)
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/* In sw implement guide, 4096 * gain = 4096 * (1 + GE)
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* = 4096 * (1 + cali_ge / 4096) = 4096 + cali_ge)
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*/
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rawdata = rawdata - cali_oe;
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/* convert to volt */
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data[0] = (rawdata * 1500 / (4096 + cali_ge)) / 1000;
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/* convert to mv, need multiply 10 */
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data[1] = (rawdata * 150 / (4096 + cali_ge)) % 100;
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/* data[2] provide high precision mv */
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data[2] = (rawdata * 1500 / (4096 + cali_ge)) % 1000;
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#else
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data[0] = (rawdata * 150 / AUXADC_PRECISE / 100);
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data[1] = ((rawdata * 150 / AUXADC_PRECISE) % 100);
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data[2] = ((rawdata * 1500 / AUXADC_PRECISE) % 1000);
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#endif
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} else {
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data[0] = (rawdata * 150 / AUXADC_PRECISE / 100);
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data[1] = ((rawdata * 150 / AUXADC_PRECISE) % 100);
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data[2] = ((rawdata * 1500 / AUXADC_PRECISE) % 1000);
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}
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}
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#if defined(CONFIG_AUXADC_NOT_CONTROL_APMIXED_BASE)
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static void mt_auxadc_disable_penirq(void)
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{
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}
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#else
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static u16 mt_tpd_read_adc(u16 pos)
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{
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AUXADC_DRV_SetBits16((u16 *)AUXADC_TP_ADDR, pos);
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AUXADC_DRV_SetBits16((u16 *)AUXADC_TP_CON0, 0x01);
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/* wait for write finish */
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while (0x01 & AUXADC_DRV_ReadReg16((u16 *)AUXADC_TP_CON0))
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pr_debug(TAG "AUXADC_TP_CON0 waiting.\n");
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return AUXADC_DRV_ReadReg16((u16 *)AUXADC_TP_DATA0);
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}
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static void mt_auxadc_disable_penirq(void)
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{
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if (adc_rtp_set) {
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adc_rtp_set = 0;
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AUXADC_DRV_SetBits16((u16 *)AUXADC_CON_RTP, 1);
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/* Turn off PENIRQ detection circuit */
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AUXADC_DRV_SetBits16((u16 *)AUXADC_TP_CMD, 1);
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/* run once touch function */
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mt_tpd_read_adc(TP_CMD_ADDR_X);
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}
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}
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#endif
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/* HAL API */
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static int IMM_auxadc_GetOneChannelValue(int dwChannel, int data[4],
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int *rawdata)
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{
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unsigned int channel[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0 };
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/* int idle_count = 0; */
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int data_ready_count = 0;
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int ret = 0;
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mutex_lock(&mutex_get_cali_value);
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if (clk_auxadc) {
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ret = clk_prepare_enable(clk_auxadc);
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if (ret) {
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pr_err(TAG "hwEnableClock AUXADC failed.");
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mutex_unlock(&mutex_get_cali_value);
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return -1;
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}
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} else {
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pr_err(TAG "hwEnableClock AUXADC failed.");
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mutex_unlock(&mutex_get_cali_value);
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return -1;
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}
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if (dwChannel == PAD_AUX_XP || dwChannel == PAD_AUX_YM)
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mt_auxadc_disable_penirq();
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/* step1 check con2 if auxadc is busy */
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/* Remove because hw/sw may access in the same time */
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#if 0
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while (AUXADC_DRV_ReadReg16((u16 *)AUXADC_CON2) & 0x01) {
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mdelay(1);
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idle_count++;
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if (idle_count > 30) {
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pr_warn(TAG "wait for auxadc idle time out\n");
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mutex_unlock(&mutex_get_cali_value);
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return -1;
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}
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}
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#endif
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/* step2 clear bit */
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if (adc_auto_set == 0) {
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/* clear bit */
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#if defined(CONFIG_MACH_MT6739)
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AUXADC_DRV_ClearBits16((u16 *)AUXADC_CON1, (1 << dwChannel));
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#else
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AUXADC_DRV_WriteReg16((u16 *)AUXADC_CON1_CLR, (1 << dwChannel));
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#endif
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}
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/* step3 read channel and make sure old ready bit == 0 */
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while (AUXADC_DRV_ReadReg16(AUXADC_DAT0 + dwChannel * 0x04) &
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(1 << 12)) {
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pr_debug(TAG "wait for channel[%d] ready\n", dwChannel);
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mdelay(1);
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data_ready_count++;
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if (data_ready_count > 30) {
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/* wait for idle time out */
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pr_err(TAG "wait for channel[%d] ready timeout\n",
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dwChannel);
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mutex_unlock(&mutex_get_cali_value);
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return -2;
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}
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}
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/* step4 set bit to trigger sample */
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if (adc_auto_set == 0)
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#if defined(CONFIG_MACH_MT6739)
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AUXADC_DRV_SetBits16((u16 *)AUXADC_CON1, (1 << dwChannel));
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#else
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AUXADC_DRV_WriteReg16((u16 *)AUXADC_CON1_SET, (1 << dwChannel));
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#endif
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/* step5 read channel and make sure ready bit == 1
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* we must dealay here for hw sample cahnnel data
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*/
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udelay(25);
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while (0 == (AUXADC_DRV_ReadReg16(AUXADC_DAT0 + dwChannel * 0x04) &
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(1 << 12))) {
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mdelay(1);
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data_ready_count++;
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if (data_ready_count > 30) {
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/* wait for idle time out */
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pr_err(TAG "wait for channel[%d] data ready timeout\n",
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dwChannel);
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mutex_unlock(&mutex_get_cali_value);
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return -3;
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}
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}
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/* step6 read data */
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channel[dwChannel] = AUXADC_DRV_ReadReg16(AUXADC_DAT0 + dwChannel *
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0x04) & 0x0FFF;
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if (rawdata != NULL)
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*rawdata = channel[dwChannel];
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mt_auxadc_get_cali_data(channel[dwChannel], data, true);
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if (clk_auxadc) {
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clk_disable_unprepare(clk_auxadc);
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} else {
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pr_err(TAG "hwdisableClock AUXADC failed.");
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mutex_unlock(&mutex_get_cali_value);
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return -1;
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}
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mutex_unlock(&mutex_get_cali_value);
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return ret;
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}
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/* 1v == 1000000 uv */
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/* this function voltage Unit is uv */
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static int IMM_auxadc_GetOneChannelValue_Cali(int Channel, int *voltage)
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{
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int ret = 0, data[4], rawvalue;
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u_int64_t temp_vol;
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int tmp;
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ret = IMM_auxadc_GetOneChannelValue(Channel, data, &rawvalue);
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if (ret) {
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pr_err(TAG "get raw value error %d\n", ret);
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return -1;
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}
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tmp = data[0] * 1000 + data[2];
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temp_vol = (u_int64_t) tmp * 1000;
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*voltage = temp_vol;
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return 0;
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}
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static void mt_auxadc_cal_prepare(void)
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{
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/* no voltage calibration */
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}
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#if defined(CONFIG_AUXADC_NEED_POWER_ON)
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static void mt_auxadc_power_on(void)
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{
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/* power on ADC */
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AUXADC_DRV_SetBits16((u16 *)AUXADC_MISC, 1 << 14);
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}
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#else
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static void mt_auxadc_power_on(void)
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{
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}
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#endif
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void mt_auxadc_hal_init(struct platform_device *dev)
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{
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struct device_node *node;
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node = of_find_compatible_node(NULL, NULL, AUXADC_APMIX_NODE);
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if (node) {
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/* Setup IO addresses */
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auxadc_apmix_base = of_iomap(node, 0);
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pr_debug(TAG "auxadc_apmix_base=0x%p\n", auxadc_apmix_base);
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} else
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pr_err(TAG "auxadc_apmix_base error\n");
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node = of_find_compatible_node(NULL, NULL, AUXADC_NODE);
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if (!node)
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pr_err(TAG "find node failed\n");
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auxadc_base = of_iomap(node, 0);
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if (!auxadc_base)
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pr_err(TAG "base failed\n");
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#if defined(EFUSE_CALI) && !defined(AUXADC_INDEX)
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node = of_find_compatible_node(NULL, NULL, "mediatek,efusec");
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if (!node)
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pr_err(TAG "find node failed\n");
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auxadc_efuse_base = of_iomap(node, 0);
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if (!auxadc_efuse_base)
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pr_err(TAG "auxadc_efuse_base base failed\n");
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pr_debug(TAG "auxadc_efuse_base:0x%p\n", auxadc_efuse_base);
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#endif
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pr_debug(TAG "auxadc:0x%p\n", auxadc_base);
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mt_auxadc_cal_prepare();
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mt_auxadc_power_on();
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}
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static void mt_auxadc_hal_suspend(void)
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{
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pr_debug(TAG "******** MT auxadc driver suspend!! ********\n");
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#if defined(AUXADC_SPM)
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AUXADC_SET_BITS((0x3 << 6) | (0x3 << 16), AUXADC_TS_X_BUFFER);
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AUXADC_CLR_BITS(0xffff << 0, AUXADC_CON1);
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#endif
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#if !defined(AUXADC_CLOCK_BY_SPM)
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pr_debug(TAG "auxadc suspend disable clock.\n");
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clk_disable_unprepare(clk_auxadc);
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#if defined(AUXADC_CLK_CTR)
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clk_disable_unprepare(clk_top_auxadc1);
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clk_disable_unprepare(clk_top_auxadc2);
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clk_disable_unprepare(clk_top_aux_tp);
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#endif
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#endif
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}
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static void mt_auxadc_hal_resume(void)
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{
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#if !defined(AUXADC_CLOCK_BY_SPM)
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int ret = 0;
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#endif
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pr_debug(TAG "******** MT auxadc driver resume!! ********\n");
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#if !defined(AUXADC_CLOCK_BY_SPM)
|
|
ret = clk_prepare_enable(clk_auxadc);
|
|
if (ret)
|
|
pr_err(TAG "auxadc enable auxadc clk failed.");
|
|
#if defined(AUXADC_CLK_CTR)
|
|
ret = clk_prepare_enable(clk_top_auxadc1);
|
|
if (ret)
|
|
pr_err(TAG "auxadc enable auxadc1 clk failed.");
|
|
|
|
ret = clk_prepare_enable(clk_top_auxadc2);
|
|
if (ret)
|
|
pr_err(TAG "auxadc enable auxadc2 clk failed.");
|
|
|
|
ret = clk_prepare_enable(clk_top_aux_tp);
|
|
if (ret)
|
|
pr_err(TAG "auxadc enable aux_tp clk failed.");
|
|
#endif
|
|
#endif
|
|
mt_auxadc_power_on();
|
|
#if defined(AUXADC_SPM)
|
|
AUXADC_CLR_BITS((0x3 << 6) | (0x3 << 16), AUXADC_TS_X_BUFFER);
|
|
#endif
|
|
}
|
|
|
|
static int mt_auxadc_dump_register(char *buf)
|
|
{
|
|
pr_debug(TAG "AUXADC_CON0=%x AUXADC_CON1=%x AUXADC_CON2=%x\n",
|
|
*(u16 *)AUXADC_CON0, *(u16 *)AUXADC_CON1, *(u16 *)AUXADC_CON2);
|
|
|
|
return sprintf(buf, "AUXADC_CON0:%x\nAUXADC_CON1:%x\nAUXADC_CON2:%x\n",
|
|
*(u16 *)AUXADC_CON0, *(u16 *)AUXADC_CON1,
|
|
*(u16 *)AUXADC_CON2);
|
|
}
|
|
|
|
int IMM_IsAdcInitReady(void)
|
|
{
|
|
return g_adc_init_flag;
|
|
}
|
|
|
|
int IMM_get_adc_channel_num(char *channel_name, int len)
|
|
{
|
|
unsigned int i = 0;
|
|
int ret = 0;
|
|
|
|
if (channel_name == NULL) {
|
|
pr_err(TAG "error: channel_name is NULL!\n");
|
|
return -1;
|
|
}
|
|
|
|
pr_debug(TAG "name=%s, name_len=%d\n", channel_name, len);
|
|
for (i = 0; i < ADC_CHANNEL_MAX; i++) {
|
|
ret = strncmp(channel_name, g_adc_info[i].channel_name, len);
|
|
if (!ret)
|
|
return g_adc_info[i].channel_number;
|
|
}
|
|
pr_err(TAG "find channel number failed\n");
|
|
return -1;
|
|
}
|
|
|
|
int IMM_GetOneChannelValue(int dwChannel, int data[4], int *rawdata)
|
|
{
|
|
return IMM_auxadc_GetOneChannelValue(dwChannel, data, rawdata);
|
|
}
|
|
|
|
/* 1v == 1000000 uv
|
|
* this function voltage Unit is uv
|
|
*/
|
|
int IMM_GetOneChannelValue_Cali(int Channel, int *voltage)
|
|
{
|
|
return IMM_auxadc_GetOneChannelValue_Cali(Channel, voltage);
|
|
}
|
|
|
|
static long auxadc_cali_unlocked_ioctl(struct file *file, unsigned int cmd,
|
|
unsigned long arg)
|
|
{
|
|
int i = 0, ret = 0;
|
|
long *user_data_addr;
|
|
long *nvram_data_addr;
|
|
|
|
mutex_lock(&auxadc_mutex);
|
|
|
|
switch (cmd) {
|
|
case TEST_ADC_CALI_PRINT:
|
|
g_AUXADC_Cali = false;
|
|
break;
|
|
|
|
case SET_ADC_CALI_Slop:
|
|
nvram_data_addr = (long *)arg;
|
|
ret = copy_from_user(auxadc_cali_slop, nvram_data_addr, 36);
|
|
g_AUXADC_Cali = false;
|
|
/* Protection */
|
|
for (i = 0; i < ADC_CHANNEL_MAX; i++) {
|
|
if ((*(auxadc_cali_slop + i) == 0) || (*
|
|
(auxadc_cali_slop + i) == 1))
|
|
*(auxadc_cali_slop + i) = 1000;
|
|
}
|
|
for (i = 0; i < ADC_CHANNEL_MAX; i++)
|
|
pr_debug(TAG "auxadc_cali_slop[%d] = %d\n",
|
|
i, *(auxadc_cali_slop + i));
|
|
break;
|
|
|
|
case SET_ADC_CALI_Offset:
|
|
nvram_data_addr = (long *)arg;
|
|
ret = copy_from_user(auxadc_cali_offset, nvram_data_addr, 36);
|
|
g_AUXADC_Cali = false;
|
|
for (i = 0; i < ADC_CHANNEL_MAX; i++)
|
|
pr_debug(TAG "auxadc_cali_offset[%d] = %d\n",
|
|
i, *(auxadc_cali_offset + i));
|
|
break;
|
|
|
|
case SET_ADC_CALI_Cal:
|
|
nvram_data_addr = (long *)arg;
|
|
ret = copy_from_user(auxadc_cali_cal, nvram_data_addr, 4);
|
|
/* enable calibration after setting AUXADC_CALI_Cal */
|
|
g_AUXADC_Cali = true;
|
|
if (auxadc_cali_cal[0] == 1)
|
|
g_AUXADC_Cali = true;
|
|
else
|
|
g_AUXADC_Cali = false;
|
|
break;
|
|
|
|
case ADC_CHANNEL_READ:
|
|
g_AUXADC_Cali = false;
|
|
user_data_addr = (long *)arg;
|
|
ret = copy_from_user(auxadc_in_data, user_data_addr, 8);
|
|
ret = copy_to_user(user_data_addr, auxadc_out_data, 8);
|
|
pr_debug(TAG "AUXADC Channel %d * %d times = %d\n",
|
|
auxadc_in_data[0],
|
|
auxadc_in_data[1], auxadc_out_data[0]);
|
|
break;
|
|
|
|
default:
|
|
g_AUXADC_Cali = false;
|
|
break;
|
|
}
|
|
|
|
mutex_unlock(&auxadc_mutex);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_COMPAT
|
|
static long compat_auxadc_unlocked_ioctl(struct file *filp, unsigned int cmd,
|
|
unsigned long arg)
|
|
{
|
|
|
|
if (!filp->f_op || !filp->f_op->unlocked_ioctl) {
|
|
pr_err(TAG "copat unlocked ioctl fail.\n");
|
|
return -ENOTTY;
|
|
}
|
|
|
|
switch (cmd) {
|
|
case TEST_ADC_CALI_PRINT:
|
|
case SET_ADC_CALI_Slop:
|
|
case SET_ADC_CALI_Offset:
|
|
case SET_ADC_CALI_Cal:
|
|
case ADC_CHANNEL_READ:
|
|
return filp->f_op->unlocked_ioctl(filp, cmd,
|
|
(unsigned long)compat_ptr(arg));
|
|
default:
|
|
pr_err(TAG "compat_ion_ioctl : No such command!! 0x%x\n", cmd);
|
|
return -ENOIOCTLCMD;
|
|
}
|
|
}
|
|
#endif
|
|
|
|
static int auxadc_cali_open(struct inode *inode, struct file *file)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int auxadc_cali_release(struct inode *inode, struct file *file)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static const struct file_operations auxadc_cali_fops = {
|
|
.owner = THIS_MODULE,
|
|
.unlocked_ioctl = auxadc_cali_unlocked_ioctl,
|
|
.open = auxadc_cali_open,
|
|
.release = auxadc_cali_release,
|
|
#if IS_ENABLED(CONFIG_COMPAT)
|
|
.compat_ioctl = compat_auxadc_unlocked_ioctl,
|
|
#endif
|
|
};
|
|
|
|
/*
|
|
* Create File For EM : AUXADC_Channel_X_Slope/Offset
|
|
*/
|
|
#if ADC_CHANNEL_MAX > 0
|
|
static ssize_t show_AUXADC_Channel_0_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 0));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_0_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_0_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_0_Slope, 0664, show_AUXADC_Channel_0_Slope,
|
|
store_AUXADC_Channel_0_Slope);
|
|
static ssize_t show_AUXADC_Channel_0_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 0));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_0_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_0_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_0_Offset, 0664, show_AUXADC_Channel_0_Offset,
|
|
store_AUXADC_Channel_0_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 1
|
|
static ssize_t show_AUXADC_Channel_1_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 1));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_1_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_1_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_1_Slope, 0664, show_AUXADC_Channel_1_Slope,
|
|
store_AUXADC_Channel_1_Slope);
|
|
static ssize_t show_AUXADC_Channel_1_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 1));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_1_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_1_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_1_Offset, 0664, show_AUXADC_Channel_1_Offset,
|
|
store_AUXADC_Channel_1_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 2
|
|
static ssize_t show_AUXADC_Channel_2_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 2));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_2_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_2_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_2_Slope, 0664, show_AUXADC_Channel_2_Slope,
|
|
store_AUXADC_Channel_2_Slope);
|
|
static ssize_t show_AUXADC_Channel_2_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 2));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_2_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_2_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_2_Offset, 0664, show_AUXADC_Channel_2_Offset,
|
|
store_AUXADC_Channel_2_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 3
|
|
static ssize_t show_AUXADC_Channel_3_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 3));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_3_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_3_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_3_Slope, 0664, show_AUXADC_Channel_3_Slope,
|
|
store_AUXADC_Channel_3_Slope);
|
|
static ssize_t show_AUXADC_Channel_3_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 3));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_3_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_3_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_3_Offset, 0664, show_AUXADC_Channel_3_Offset,
|
|
store_AUXADC_Channel_3_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 4
|
|
static ssize_t show_AUXADC_Channel_4_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 4));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_4_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_4_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_4_Slope, 0664, show_AUXADC_Channel_4_Slope,
|
|
store_AUXADC_Channel_4_Slope);
|
|
static ssize_t show_AUXADC_Channel_4_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 4));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_4_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_4_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_4_Offset, 0664, show_AUXADC_Channel_4_Offset,
|
|
store_AUXADC_Channel_4_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 5
|
|
static ssize_t show_AUXADC_Channel_5_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 5));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_5_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_5_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_5_Slope, 0664, show_AUXADC_Channel_5_Slope,
|
|
store_AUXADC_Channel_5_Slope);
|
|
static ssize_t show_AUXADC_Channel_5_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 5));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_5_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_5_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_5_Offset, 0664, show_AUXADC_Channel_5_Offset,
|
|
store_AUXADC_Channel_5_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 6
|
|
static ssize_t show_AUXADC_Channel_6_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 6));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_6_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_6_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_6_Slope, 0664, show_AUXADC_Channel_6_Slope,
|
|
store_AUXADC_Channel_6_Slope);
|
|
static ssize_t show_AUXADC_Channel_6_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 6));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_6_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_6_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_6_Offset, 0664, show_AUXADC_Channel_6_Offset,
|
|
store_AUXADC_Channel_6_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 7
|
|
static ssize_t show_AUXADC_Channel_7_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 7));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_7_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_7_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_7_Slope, 0664, show_AUXADC_Channel_7_Slope,
|
|
store_AUXADC_Channel_7_Slope);
|
|
static ssize_t show_AUXADC_Channel_7_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 7));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_7_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_7_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_7_Offset, 0664, show_AUXADC_Channel_7_Offset,
|
|
store_AUXADC_Channel_7_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 8
|
|
static ssize_t show_AUXADC_Channel_8_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 8));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_8_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_8_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_8_Slope, 0664, show_AUXADC_Channel_8_Slope,
|
|
store_AUXADC_Channel_8_Slope);
|
|
static ssize_t show_AUXADC_Channel_8_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 8));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_8_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_8_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_8_Offset, 0664, show_AUXADC_Channel_8_Offset,
|
|
store_AUXADC_Channel_8_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 9
|
|
static ssize_t show_AUXADC_Channel_9_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 9));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_9_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_9_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_9_Slope, 0664, show_AUXADC_Channel_9_Slope,
|
|
store_AUXADC_Channel_9_Slope);
|
|
static ssize_t show_AUXADC_Channel_9_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 9));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_9_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_9_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_9_Offset, 0664, show_AUXADC_Channel_9_Offset,
|
|
store_AUXADC_Channel_9_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 10
|
|
static ssize_t show_AUXADC_Channel_10_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 10));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_10_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_10_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_10_Slope, 0664, show_AUXADC_Channel_10_Slope,
|
|
store_AUXADC_Channel_10_Slope);
|
|
static ssize_t show_AUXADC_Channel_10_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 10));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_10_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_10_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_10_Offset, 0664,
|
|
show_AUXADC_Channel_10_Offset, store_AUXADC_Channel_10_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 11
|
|
static ssize_t show_AUXADC_Channel_11_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 11));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_11_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_11_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_11_Slope, 0664, show_AUXADC_Channel_11_Slope,
|
|
store_AUXADC_Channel_11_Slope);
|
|
static ssize_t show_AUXADC_Channel_11_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 11));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_11_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_11_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_11_Offset, 0664,
|
|
show_AUXADC_Channel_11_Offset, store_AUXADC_Channel_11_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 12
|
|
static ssize_t show_AUXADC_Channel_12_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 12));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_12_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_12_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_12_Slope, 0664, show_AUXADC_Channel_12_Slope,
|
|
store_AUXADC_Channel_12_Slope);
|
|
static ssize_t show_AUXADC_Channel_12_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 12));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_12_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_12_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_12_Offset, 0664,
|
|
show_AUXADC_Channel_12_Offset, store_AUXADC_Channel_12_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 13
|
|
static ssize_t show_AUXADC_Channel_13_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 13));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_13_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_13_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_13_Slope, 0664, show_AUXADC_Channel_13_Slope,
|
|
store_AUXADC_Channel_13_Slope);
|
|
static ssize_t show_AUXADC_Channel_13_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 13));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_13_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_13_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_13_Offset, 0664,
|
|
show_AUXADC_Channel_13_Offset, store_AUXADC_Channel_13_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 14
|
|
static ssize_t show_AUXADC_Channel_14_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 14));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_14_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_14_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_14_Slope, 0664, show_AUXADC_Channel_14_Slope,
|
|
store_AUXADC_Channel_14_Slope);
|
|
static ssize_t show_AUXADC_Channel_14_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 14));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_14_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_14_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_14_Offset, 0664,
|
|
show_AUXADC_Channel_14_Offset, store_AUXADC_Channel_14_Offset);
|
|
#endif
|
|
|
|
|
|
#if ADC_CHANNEL_MAX > 15
|
|
static ssize_t show_AUXADC_Channel_15_Slope(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_slop + 15));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_15_Slope : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_15_Slope(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_15_Slope, 0664, show_AUXADC_Channel_15_Slope,
|
|
store_AUXADC_Channel_15_Slope);
|
|
static ssize_t show_AUXADC_Channel_15_Offset(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 1;
|
|
|
|
ret_value = (*(auxadc_cali_offset + 15));
|
|
pr_debug(TAG "[EM] AUXADC_Channel_15_Offset : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_15_Offset(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_15_Offset, 0664,
|
|
show_AUXADC_Channel_15_Offset, store_AUXADC_Channel_15_Offset);
|
|
#endif
|
|
|
|
/*
|
|
* Create File For EM : AUXADC_Channel_Is_Calibration
|
|
*/
|
|
static ssize_t show_AUXADC_Channel_Is_Calibration(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret_value = 2;
|
|
|
|
ret_value = g_AUXADC_Cali;
|
|
pr_debug(TAG "[EM] AUXADC_Channel_Is_Calibration : %d\n", ret_value);
|
|
return sprintf(buf, "%u\n", ret_value);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_Channel_Is_Calibration(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support Write Function\n");
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_Channel_Is_Calibration, 0664,
|
|
show_AUXADC_Channel_Is_Calibration,
|
|
store_AUXADC_Channel_Is_Calibration);
|
|
|
|
static ssize_t show_AUXADC_register(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
return mt_auxadc_dump_register(buf);
|
|
}
|
|
|
|
static ssize_t store_AUXADC_register(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
pr_debug(TAG "[EM] Not Support %s\n", __func__);
|
|
return size;
|
|
}
|
|
|
|
static DEVICE_ATTR(AUXADC_register, 0664, show_AUXADC_register,
|
|
store_AUXADC_register);
|
|
|
|
/* for support factory mode, It will make a fatal error if you delete this */
|
|
static ssize_t show_AUXADC_channel(struct device *dev,
|
|
struct device_attribute *attr, char *buf)
|
|
{
|
|
int ret = 0;
|
|
int i = 0;
|
|
int tmp_len = 0;
|
|
int rawdata = 0;
|
|
int tmp_vol[4] = { 0, 0, 0, 0 };
|
|
char tmp_buf[256];
|
|
|
|
for (i = 0; i < ADC_CHANNEL_MAX; i++) {
|
|
ret = IMM_auxadc_GetOneChannelValue(i, tmp_vol,
|
|
&rawdata);
|
|
if (ret < 0) {
|
|
pr_info(TAG "get chn[%d] data error\n", i);
|
|
rawdata = 0;
|
|
tmp_vol[0] = -1;
|
|
tmp_len = snprintf(tmp_buf, 255,
|
|
"[%2d,%4d,%4d]-%15.15s-\n",
|
|
i, rawdata, tmp_vol[0],
|
|
g_adc_info[i].channel_name);
|
|
if (tmp_len > 0)
|
|
strncat(buf, tmp_buf, strlen(tmp_buf));
|
|
} else {
|
|
tmp_len = snprintf(tmp_buf, 255,
|
|
"[%2d,%4d,%4d]-%15.15s-\n", i, rawdata,
|
|
(tmp_vol[0]*1000+tmp_vol[2]),
|
|
g_adc_info[i].channel_name);
|
|
if (tmp_len > 0)
|
|
strncat(buf, tmp_buf, strlen(tmp_buf));
|
|
pr_info(TAG "len:%d,chn[%d]=%d mv, [%s]\n",
|
|
(int)strlen(buf), i,
|
|
(tmp_vol[0]*1000+tmp_vol[2]),
|
|
g_adc_info[i].channel_name);
|
|
}
|
|
}
|
|
|
|
ret = sprintf(tmp_buf,
|
|
"-->REG:0x%4x,GAIN:%4u,GE_A:%4u,OE_A:%4u,GE:%4d,OE:%4d\n",
|
|
cali_reg, gain, cali_ge_a, cali_oe_a, cali_ge, cali_oe);
|
|
if (ret > 0)
|
|
strncat(buf, tmp_buf, strlen(tmp_buf));
|
|
/* mt_auxadc_dump_register(tmp_buf); */
|
|
/* strncat(buf, tmp_buf, strlen(tmp_buf)); */
|
|
return strlen(buf);
|
|
}
|
|
|
|
static int dbug_thread(void *unused)
|
|
{
|
|
int i = 0, data[4] = { 0, 0, 0, 0 };
|
|
int res = 0;
|
|
int rawdata = 0;
|
|
int cali_voltage = 0;
|
|
|
|
while (g_start_debug_thread) {
|
|
for (i = 0; i < ADC_CHANNEL_MAX; i++) {
|
|
res = IMM_auxadc_GetOneChannelValue(i, data, &rawdata);
|
|
if (res < 0) {
|
|
pr_debug(TAG "get data error\n");
|
|
} else
|
|
pr_debug(TAG "ch[%d]raw =%d, data=%d.%.02d\n",
|
|
i, rawdata, data[0], data[1]);
|
|
|
|
res = IMM_auxadc_GetOneChannelValue_Cali(i,
|
|
&cali_voltage);
|
|
if (res < 0) {
|
|
pr_debug(TAG "get cali voltage error\n");
|
|
} else
|
|
pr_debug(TAG "channel[%d] cali_voltage =%d\n",
|
|
i, cali_voltage);
|
|
|
|
msleep(500);
|
|
|
|
}
|
|
msleep(500);
|
|
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
|
|
static ssize_t store_AUXADC_channel(struct device *dev,
|
|
struct device_attribute *attr, const char *buf, size_t size)
|
|
{
|
|
int start_flag = 0;
|
|
int error = 0;
|
|
int ret = 0;
|
|
|
|
if (buf == NULL) {
|
|
pr_debug(TAG "[%s] Invalid input!!\n", __func__);
|
|
return size;
|
|
}
|
|
|
|
ret = kstrtoint(buf, sizeof(int), &start_flag);
|
|
if (ret < 0) {
|
|
pr_debug(TAG "[%s] Invalid invalues!!\n", __func__);
|
|
return size;
|
|
}
|
|
|
|
pr_debug(TAG "start flag =%d\n", start_flag);
|
|
g_start_debug_thread = start_flag;
|
|
if (start_flag) {
|
|
thread = kthread_run(dbug_thread, 0, "AUXADC");
|
|
if (IS_ERR(thread)) {
|
|
error = PTR_ERR(thread);
|
|
pr_debug(TAG "create kthread fail: %d\n", error);
|
|
}
|
|
}
|
|
return size;
|
|
}
|
|
|
|
|
|
static DEVICE_ATTR(AUXADC_read_channel, 0664, show_AUXADC_channel,
|
|
store_AUXADC_channel);
|
|
|
|
static int mt_auxadc_create_device_attr(struct device *dev)
|
|
{
|
|
int ret = 0;
|
|
/* For EM */
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_register);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_read_channel);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#if ADC_CHANNEL_MAX > 0
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_0_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_0_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 1
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_1_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_1_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 2
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_2_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_2_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 3
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_3_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_3_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 4
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_4_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_4_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 5
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_5_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_5_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 6
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_6_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_6_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 7
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_7_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_7_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 8
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_8_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_8_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 9
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_9_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_9_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 10
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_10_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_10_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 11
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_11_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_11_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 12
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_12_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_12_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 13
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_13_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_13_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 14
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_14_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_14_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
#if ADC_CHANNEL_MAX > 15
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_15_Slope);
|
|
if (ret != 0)
|
|
goto exit;
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_15_Offset);
|
|
if (ret != 0)
|
|
goto exit;
|
|
#endif
|
|
ret = device_create_file(dev, &dev_attr_AUXADC_Channel_Is_Calibration);
|
|
if (ret != 0)
|
|
goto exit;
|
|
|
|
return 0;
|
|
exit:
|
|
return 1;
|
|
}
|
|
|
|
|
|
static int proc_utilization_show(struct seq_file *m, void *v)
|
|
{
|
|
int i, res, raw;
|
|
int data[4] = { 0, 0, 0, 0 };
|
|
int data_raw[4] = { 0, 0, 0, 0 };
|
|
|
|
seq_puts(m, "********** Auxadc status dump **********\n");
|
|
|
|
seq_printf(m, "reg=0x%x ADC_GE_A=%d ADC_OE_A=%d GE:%d OE:%dgain:0x%x\n",
|
|
cali_reg, cali_ge_a, cali_oe_a, cali_ge, cali_oe, gain);
|
|
#if defined(EFUSE_CALI)
|
|
seq_printf(m, "ADC_GE_A_MASK:0x%x ADC_GE_A_SHIFT:0x%x\n",
|
|
ADC_GE_A_MASK, ADC_GE_A_SHIFT);
|
|
seq_printf(m, "ADC_OE_A_MASK:0x%x ADC_OE_A_SHIFT:0x%x\n",
|
|
ADC_OE_A_MASK, ADC_OE_A_SHIFT);
|
|
seq_printf(m, "ADC_CALI_EN_A_MASK:0x%x ADC_CALI_EN_A_SHIFT:0x%x\n",
|
|
ADC_CALI_EN_A_MASK, ADC_CALI_EN_A_SHIFT);
|
|
#endif
|
|
for (i = 100; i <= 1000; i = i + 100) {
|
|
mt_auxadc_get_cali_data(i, data, true);
|
|
seq_printf(m, "raw:%d data:%d %d %d with cali\n",
|
|
i, data[0], data[1], data[2]);
|
|
mt_auxadc_get_cali_data(i, data, false);
|
|
seq_printf(m, "raw:%d data:%d %d %d without cali\n",
|
|
i, data[0], data[1], data[2]);
|
|
}
|
|
|
|
for (i = 0; i < 5; i++) {
|
|
res = IMM_auxadc_GetOneChannelValue(i, data, &raw);
|
|
if (res < 0)
|
|
seq_printf(m, "get data error res:%d\n", res);
|
|
else {
|
|
seq_printf(m, "channel[%d]=%d %d %d\n",
|
|
i, data[0], data[1], data[2]);
|
|
mt_auxadc_get_cali_data(raw, data_raw, false);
|
|
seq_printf(m, "channel[%d] raw data =%d %d %d\n",
|
|
i, data_raw[0], data_raw[1], data_raw[2]);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int proc_utilization_open(struct inode *inode, struct file *file)
|
|
{
|
|
return single_open(file, proc_utilization_show, NULL);
|
|
}
|
|
|
|
static const struct file_operations auxadc_debug_proc_fops = {
|
|
.open = proc_utilization_open,
|
|
.read = seq_read,
|
|
};
|
|
|
|
|
|
static void adc_debug_init(void)
|
|
{
|
|
struct proc_dir_entry *mt_auxadc_dir;
|
|
|
|
mt_auxadc_dir = proc_mkdir("mt-auxadc", NULL);
|
|
if (!mt_auxadc_dir) {
|
|
pr_err(TAG "fail to mkdir /proc/mt-auxadc\n");
|
|
return;
|
|
}
|
|
proc_create("dump_auxadc_status", 0644, mt_auxadc_dir,
|
|
&auxadc_debug_proc_fops);
|
|
pr_info(TAG "proc_create auxadc_debug_proc_fops\n");
|
|
}
|
|
|
|
|
|
|
|
/* platform_driver API */
|
|
static int mt_auxadc_probe(struct platform_device *dev)
|
|
{
|
|
int ret = 0;
|
|
struct device *adc_dev = NULL;
|
|
int used_channel_counter = 0;
|
|
int of_value = 0;
|
|
struct device_node *node;
|
|
|
|
pr_info(TAG "******** MT AUXADC driver probe!! ********\n");
|
|
|
|
/* Integrate with NVRAM */
|
|
ret = alloc_chrdev_region(&auxadc_cali_devno, 0, 1,
|
|
AUXADC_CALI_DEVNAME);
|
|
if (ret)
|
|
pr_err(TAG "Error: Can't Get Major number for auxadc_cali\n");
|
|
|
|
auxadc_cali_cdev = cdev_alloc();
|
|
auxadc_cali_cdev->owner = THIS_MODULE;
|
|
auxadc_cali_cdev->ops = &auxadc_cali_fops;
|
|
ret = cdev_add(auxadc_cali_cdev, auxadc_cali_devno, 1);
|
|
if (ret)
|
|
pr_err(TAG "auxadc_cali Error: cdev_add\n");
|
|
|
|
auxadc_cali_major = MAJOR(auxadc_cali_devno);
|
|
auxadc_cali_class = class_create(THIS_MODULE, AUXADC_CALI_DEVNAME);
|
|
adc_dev = (struct device *)device_create(auxadc_cali_class,
|
|
NULL, auxadc_cali_devno, NULL,
|
|
AUXADC_CALI_DEVNAME);
|
|
|
|
/* read calibration data from EFUSE */
|
|
mt_auxadc_hal_init(dev);
|
|
|
|
node = of_find_compatible_node(NULL, NULL, "mediatek,adc_channel");
|
|
if (node) {
|
|
ret = of_property_read_u32_array(node, "mediatek,temperature0",
|
|
&of_value, 1);
|
|
if (ret == 0) {
|
|
sprintf(g_adc_info[used_channel_counter].channel_name,
|
|
"ADC_RFTMP");
|
|
g_adc_info[used_channel_counter].channel_number =
|
|
of_value;
|
|
pr_info(TAG "find node TEMPERATURE:%d\n", of_value);
|
|
used_channel_counter++;
|
|
}
|
|
ret = of_property_read_u32_array(node, "mediatek,temperature1",
|
|
&of_value, 1);
|
|
if (ret == 0) {
|
|
sprintf(g_adc_info[used_channel_counter].channel_name,
|
|
"ADC_APTMP");
|
|
g_adc_info[used_channel_counter].channel_number =
|
|
of_value;
|
|
pr_info(TAG "find node TEMPERATURE1:%d\n", of_value);
|
|
used_channel_counter++;
|
|
}
|
|
ret = of_property_read_u32_array(node,
|
|
"mediatek,adc_fdd_rf_params_dynamic_custom_ch",
|
|
&of_value, 1);
|
|
if (ret == 0) {
|
|
sprintf(g_adc_info[used_channel_counter].channel_name,
|
|
"ADC_FDD_Rf_Params_Dynamic_Custom");
|
|
g_adc_info[used_channel_counter].channel_number =
|
|
of_value;
|
|
pr_info(TAG "find adc_fdd_rf node:%d\n", of_value);
|
|
used_channel_counter++;
|
|
}
|
|
ret = of_property_read_u32_array(node, "mediatek,hf_mic",
|
|
&of_value, 1);
|
|
if (ret == 0) {
|
|
sprintf(g_adc_info[used_channel_counter].channel_name,
|
|
"ADC_MIC");
|
|
g_adc_info[used_channel_counter].channel_number =
|
|
of_value;
|
|
pr_info(TAG "find node HF_MIC:%d\n", of_value);
|
|
used_channel_counter++;
|
|
}
|
|
ret = of_property_read_u32_array(node, "mediatek,lcm_voltage",
|
|
&of_value, 1);
|
|
if (ret == 0) {
|
|
sprintf(g_adc_info[used_channel_counter].channel_name,
|
|
"ADC_LCM_VOLTAGE");
|
|
g_adc_info[used_channel_counter].channel_number =
|
|
of_value;
|
|
pr_info(TAG "find node LCM_VOLTAGE:%d\n", of_value);
|
|
used_channel_counter++;
|
|
}
|
|
ret = of_property_read_u32_array(node,
|
|
"mediatek,battery_voltage", &of_value, 1);
|
|
if (ret == 0) {
|
|
sprintf(g_adc_info[used_channel_counter].channel_name,
|
|
"ADC_BATTERY_VOLTAGE");
|
|
g_adc_info[used_channel_counter].channel_number =
|
|
of_value;
|
|
pr_info(TAG "find node BATTERY_VOLTAGE:%d\n", of_value);
|
|
used_channel_counter++;
|
|
}
|
|
ret = of_property_read_u32_array(node,
|
|
"mediatek,charger_voltage", &of_value, 1);
|
|
if (ret == 0) {
|
|
sprintf(g_adc_info[used_channel_counter].channel_name,
|
|
"ADC_CHARGER_VOLTAGE");
|
|
g_adc_info[used_channel_counter].channel_number =
|
|
of_value;
|
|
pr_info(TAG "find node CHARGER_VOLTAGE:%d\n",
|
|
of_value);
|
|
used_channel_counter++;
|
|
}
|
|
ret = of_property_read_u32_array(node, "mediatek,utms",
|
|
&of_value, 1);
|
|
if (ret == 0) {
|
|
sprintf(g_adc_info[used_channel_counter].channel_name,
|
|
"ADC_UTMS");
|
|
g_adc_info[used_channel_counter].channel_number =
|
|
of_value;
|
|
pr_info(TAG "find node UTMS:%d\n", of_value);
|
|
used_channel_counter++;
|
|
}
|
|
ret = of_property_read_u32_array(node, "mediatek,ref_current",
|
|
&of_value, 1);
|
|
if (ret == 0) {
|
|
sprintf(g_adc_info[used_channel_counter].channel_name,
|
|
"ADC_REF_CURRENT");
|
|
g_adc_info[used_channel_counter].channel_number =
|
|
of_value;
|
|
pr_info(TAG "find node REF_CURRENT:%d\n", of_value);
|
|
used_channel_counter++;
|
|
}
|
|
ret = of_property_read_u32_array(node, "mediatek,board_id",
|
|
&of_value, 1);
|
|
if (ret == 0) {
|
|
sprintf(g_adc_info[used_channel_counter].channel_name,
|
|
"BOARD_ID");
|
|
g_adc_info[used_channel_counter].channel_number =
|
|
of_value;
|
|
pr_info(TAG "find node BOARD_ID:%d\n", of_value);
|
|
used_channel_counter++;
|
|
}
|
|
ret = of_property_read_u32_array(node, "mediatek,board_id_2",
|
|
&of_value, 1);
|
|
if (ret == 0) {
|
|
sprintf(g_adc_info[used_channel_counter].channel_name,
|
|
"BOARD_ID_2");
|
|
g_adc_info[used_channel_counter].channel_number =
|
|
of_value;
|
|
pr_info(TAG "find node BOARD_ID_2:%d\n", of_value);
|
|
used_channel_counter++;
|
|
}
|
|
ret = of_property_read_u32_array(node, "mediatek,board_id_3",
|
|
&of_value, 1);
|
|
if (ret == 0) {
|
|
sprintf(g_adc_info[used_channel_counter].channel_name,
|
|
"BOARD_ID_3");
|
|
g_adc_info[used_channel_counter].channel_number =
|
|
of_value;
|
|
pr_info(TAG "find node BOARD_ID_3:%d\n", of_value);
|
|
used_channel_counter++;
|
|
}
|
|
} else {
|
|
pr_err(TAG "find node failed\n");
|
|
}
|
|
|
|
clk_auxadc = devm_clk_get(&dev->dev, "auxadc-main");
|
|
if (IS_ERR(clk_auxadc)) {
|
|
pr_err(TAG "[AUXADC] devm_clk_get failed\n");
|
|
return PTR_ERR(clk_auxadc);
|
|
}
|
|
pr_debug(TAG "[AUXADC]: auxadc CLK:0x%p\n", clk_auxadc);
|
|
ret = clk_prepare_enable(clk_auxadc);
|
|
if (ret)
|
|
pr_err(TAG "hwEnableClock AUXADC failed.");
|
|
#if defined(AUXADC_CLK_CTR)
|
|
clk_top_auxadc1 = devm_clk_get(&dev->dev, "auxadc1");
|
|
if (IS_ERR(clk_top_auxadc1)) {
|
|
pr_err(TAG "[AUXADC] devm_clk_get auxadc1 failed\n");
|
|
return PTR_ERR(clk_top_auxadc1);
|
|
}
|
|
ret = clk_prepare_enable(clk_top_auxadc1);
|
|
if (ret)
|
|
pr_err(TAG "hwEnableClock auxadc1 failed.");
|
|
|
|
clk_top_auxadc2 = devm_clk_get(&dev->dev, "auxadc2");
|
|
if (IS_ERR(clk_top_auxadc2)) {
|
|
pr_err(TAG "[AUXADC] devm_clk_get auxadc2 failed\n");
|
|
return PTR_ERR(clk_top_auxadc2);
|
|
}
|
|
ret = clk_prepare_enable(clk_top_auxadc2);
|
|
if (ret)
|
|
pr_err(TAG "hwEnableClock auxadc2 failed.");
|
|
|
|
clk_top_aux_tp = devm_clk_get(&dev->dev, "auxadc-tp");
|
|
if (IS_ERR(clk_top_aux_tp)) {
|
|
pr_err(TAG "[AUXADC] devm_clk_get auxadc-tp failed\n");
|
|
return PTR_ERR(clk_top_aux_tp);
|
|
}
|
|
ret = clk_prepare_enable(clk_top_aux_tp);
|
|
if (ret)
|
|
pr_err(TAG "hwEnableClock auxadc-tp failed.");
|
|
#endif
|
|
|
|
adc_debug_init();
|
|
|
|
g_adc_init_flag = 1;
|
|
|
|
mt_auxadc_create_device_attr(adc_dev);
|
|
mt_auxadc_update_cali();
|
|
|
|
pr_info(TAG "MT AUXADC driver probe Done!\n");
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int mt_auxadc_remove(struct platform_device *dev)
|
|
{
|
|
pr_debug(TAG "******** MT auxadc driver remove!! ********\n");
|
|
return 0;
|
|
}
|
|
|
|
static void mt_auxadc_shutdown(struct platform_device *dev)
|
|
{
|
|
pr_debug(TAG "******** MT auxadc driver shutdown!! ********\n");
|
|
}
|
|
|
|
static int mt_auxadc_suspend(struct platform_device *dev, pm_message_t state)
|
|
{
|
|
mt_auxadc_hal_suspend();
|
|
return 0;
|
|
}
|
|
|
|
static int mt_auxadc_resume(struct platform_device *dev)
|
|
{
|
|
mt_auxadc_hal_resume();
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id mt_auxadc_of_match[] = {
|
|
{.compatible = "mediatek,mt6757-auxadc",},
|
|
{.compatible = "mediatek,mt8167-auxadc",},
|
|
{.compatible = "mediatek,auxadc",},
|
|
{},
|
|
};
|
|
|
|
static struct platform_driver mt_auxadc_driver = {
|
|
.probe = mt_auxadc_probe,
|
|
.remove = mt_auxadc_remove,
|
|
.shutdown = mt_auxadc_shutdown,
|
|
#ifdef CONFIG_PM
|
|
.suspend = mt_auxadc_suspend,
|
|
.resume = mt_auxadc_resume,
|
|
#endif
|
|
.driver = {
|
|
.name = "mt-auxadc",
|
|
.of_match_table = mt_auxadc_of_match,
|
|
},
|
|
};
|
|
|
|
static int __init mt_auxadc_init(void)
|
|
{
|
|
int ret;
|
|
|
|
ret = platform_driver_register(&mt_auxadc_driver);
|
|
if (ret) {
|
|
pr_err(TAG "Unable to register driver (%d)\n", ret);
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void __exit mt_auxadc_exit(void)
|
|
{
|
|
}
|
|
|
|
module_init(mt_auxadc_init);
|
|
module_exit(mt_auxadc_exit);
|
|
|
|
MODULE_AUTHOR("MTK");
|
|
MODULE_DESCRIPTION("MTK AUXADC Device Driver");
|
|
MODULE_LICENSE("GPL");
|